Manage BOOT_FLASH_SPINAND, with boot_device="spi-nand"
and treat this value in bootcmd_stm32mp.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
As the op-tee presence is detected by U-boot, the stm32mp15_optee_defconfig
is identical to stm32mp15_trusted_defconfig and can be removed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Activate OP-TEE driver for trusted and optee defconfig.
This driver allows detection of TEE presence for boot from flash;
CONFIG_STM32MP1_OPTEE is also removed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
This patch reduces the stm32mp1 environment size and builds
dynamically the MTD partitions with information from defconfig
(CONFIG_MTDPARTS_...).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
This patch reduces the stm32mp1 environment size and
builds dynamically the DFU board configuration with gpt
and mtd partitions and information from defconfig
(CONFIG_DFU_ALT_RAM0).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Move the stm32mp1 common code set_dfu_alt_info() in common directory,
this patch reduce the maintenance effort on this generic part (not board
dependent).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Move the stm32mp1 common code board_get_mtdparts() in common directory,
this patch reduce the maintenance effort on this generic part (not board
dependent).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
The DHCOR board does exist in multiple variants with different DDR3
DRAM sizes. To cater for all of them, implement DDR3 code handling.
There are two GPIOs which code the DRAM size populated on the SoM,
read them out and use the value to pick the correct DDR3 config.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
The AV96 board does exist in multiple variants. To cater for all of
them, implement board code handling. There are two GPIOs which code
the type of the board, read them out and use the value to pick the
correct device tree from an fitImage.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Change-Id: Iddb330b9a66500495885457cbe17edc0eacaaf43
Add default U-Boot configuration for the DHCOR SoM on AV96 board.
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
When variable setup_console_atag is unset then read default value from OMAP
atags which passed NOLO bootloader to U-Boot.
This would allow to boot Maemo Linux kernel from U-Boot with serial console
settings configured in NOLO bootloader (which loads U-Boot).
So serial console needs to be enabled only at one place, globally in NOLO.
Signed-off-by: Pali Rohár <pali@kernel.org>
Now when code for defining partitions is duplicated at two locations
(option CONFIG_MTDPARTS_DEFAULT in nokia_rx51_defconfig file and macro
OMAP_TAG_PARTITION_CONFIG in rx51.c file) there is no need to have common
macros. Lets inline PART* macros to rx51.c file.
Signed-off-by: Pali Rohár <pali@kernel.org>
In commit commit 278b90ce78 ("configs: Migrate CONFIG_SYS_TEXT_BASE") was
moved definition for CONFIG_SYS_TEXT_BASE option but author probably forgot
to move also comment for lines which are moving. So do it now!
Signed-off-by: Pali Rohár <pali@kernel.org>
Add code to check m4 partition booted or not, we will use this
to runtime set device tree file that passed to Linux Kernel.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Make sure that all devices that are powered up by SPL are powered down
before entering into the u-boot. Otherwise the subsystem/device will
never be powered down by SCFW, due to SPL and u-boot are in different
partitions.
Benefiting from power domain driver, this patch implements the function
"imx8_power_off_pd_devices" to power off all active devices.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Beacon EmbeddedWorks, formerly known as Logic PD, is releasing
a devkit based on the i.MX8M Mini SoC consisting of baseboard +
SOM.
It supports eMMC on the SOM, microSD on the baseboard, various
GPIO, the PINCTRL, and UART.
Signed-off-by: Adam Ford <aford173@gmail.com>
Add initial support for Technexion Pico-iMX8MQ SoM on PicoPI carrier
board. Currently working is ethernet, serial, eMMC. DT is imported
from Linux 5.4.28 ("462afcd6e7ea") .
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Move below defines which are used by mtest utility to Kconfig.
CONFIG_SYS_MEMTEST_START
CONFIG_SYS_MEMTEST_END
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
[trini: Fix kmcoge5ne board, re-run migration as well]
Signed-off-by: Tom Rini <trini@konsulko.com>
So far the Juno board wasn't implementing reset. Let's just use the
already existing PSCI_RESET based method to avoid any extra code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The Arm Juno board was still somewhat stuck in "hardcoded land", even
though there are stable DTs around, and one happens to actually be on
the memory mapped NOR flash.
Enable the configuration options to let the board use OF_CONTROL, and
add a routine to find the address of the DTB partition in NOR
flash, to use that for U-Boot's own purposes.
This can also passed on via $fdtcontroladdr to any kernel or EFI
application, removing the need to actually load a device tree.
Since the existing "afs" command and its flash routines require
flash_init() to be called before being usable, and this is done much
later in the boot process, we introduce a stripped-down partition finder
routine in vexpress64.c, to scan the NOR flash partitions for the
DT partition. This location is then used for U-Boot to find and probe
devices.
The name of the partition can be configured, if needed, but defaults
to "board.dtb", which is used by Linaro's firmware image provided.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
- Add DM model for P1010RDB
- Add I2C DM Model support for P1010RDB, T1042RDB, T2080, T4240RDB,
MPC8548CDS, T1024RDB, P4080, P3041DS, P2041RDB, P2020RDB, P1020RDB,
P5040DS
- Fix reference to READM.qe_firmware
- dts clean up to use -u-boot for px30, rk3399 boards
- dts sycn from upstream kernel for rk3328, rk3399
- add rockchip rng driver
- new board support: rk3328-roc-cc, rk3399-roc-pc,Nanopi M4 2GB
Coreboot is a first-stage bootloader mostly used on x86 devices as an
alternative to UEFI. Coreboot runs in 32-bit mode.
U-Boot currently supports booting from coreboot as a second-stage
bootloader, also in 32-bit mode. However it is useful to be able to run
U-Boot in 64-bit mode. To do this we can have a 32-bit SPL which switches
over the CPU and jumps to a 64-bit U-Boot proper.
Add a new 'coreboot64' board for running 64-bit U-Boot from coreboot. This
uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot.
This allows running 64-bit EFI images on x86, for example, without needing
a native U-Boot port for a board.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Compile the legacy PCIe initialization reoutines for P1010RDB
boards only when DM_PCI is not enabled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add initial support for Google's Coral Dev Board based on i.MX8MQ.
https://coral.ai/products/dev-board
The Phanbell naming has been used here to match the naming convention
used in Google's U-Boot source tree:
https://coral.googlesource.com/uboot-imx/
Co-developed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
Tested-by: Marco Franchi <marcofrk@gmail.com>
This patch adds skew register settings for KSZ9131. It checks first
which phy is on the board and then applies the correct skew settings.
Skew settings calculation for the KSZ9131:
The i.MX6 SoC has an output skew tolerance of -100ps to 900ps. All
PCB traces where routed exactly the same length so we can calculate
the skew settings without taking the length into consideration. The
traces are all length matched.
RXC skew (PHY to MAC):
- We use the 2ns DLL controlled delay on the PHY
- We do not use the skew registers
This results in the following values:
RXC
PHY fixed Delay 2000ps
PHY Added Delay 0ps
T_setup_R min 2.00ns
T_setup_R typ 2.00ns
T_setup_R max 2.00ns
T_hold_R min 1.60ns
T_hold_R typ 2.00ns
T_hold_R max 2.40ns
That means we are well within RGMII specs.
TXC skew (MAC to PHY):
- We use the 2ns DLL controlled delay on the PHY
- We then subtract ~0.6ns with TXD[0:3] and TXC clock pad skew
register in a resulting ~1.4ns delay.
This results in the following values under consideration of the
tolerances:
TXC min TXC typ TXC max
MAC min -100ps -100ps -100ps
MAC max 900ps 900ps 900ps
PHY fixed Delay 2000ps 2000ps 2000ps
PHY added Delay -340ps -600ps -859ps
T_setup_T min 1.56ns 1.30ns 1.04ns
T_setup_T typ 2.06ns 1.80ns 1.54ns
T_setup_T max 2.56ns 2.30ns 2.04ns
T_hold_T min 1.04ns 1.30ns 1.56ns
T_hold_T typ 1.94ns 2.20ns 2.46ns
T_hold_T max 2.84ns 3.10ns 3.36ns
This shows that T_hold_T min and T_setup_T min times are out of spec
for RGMII timing. However the KSZ9131 has a minimal value for this time
of 0.8ns which is met under all circumstances.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
This patch determines which phy is placed on the board with the PHY ID
then it sets the same settings for KSZ9031 as before but for KSZ9131
it enables both RXC and TXC delay lines in the PHY.
This will compensate the missing delay from the MAC. Other skew
settings are not needed as the traces on board are routed exactly the
same length
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Tested-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Igor Opaniuk <igor.opaniuk@toradex.com>
This patches uses the existing functions for interacting with the
KSZ9031 and uses the values appropriate for our board.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Tested-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Use the `do_reset` implementation of `arch/arm/lib/reset.c` in SPL
instead. It is very close to what is done here, anyway, and plays
more nicely with the rest of U-Boot than adding a custom `do_reset`
implementation into board files.
`do_reset` from `arch/arm/lib/reset.c` calls `reset_cpu` with 0 as the
addr parameter while the boards are passing WDOG1_BASE_ADDR. This is
ok because the `reset_cpu` implementation uses WDOG1_BASE_ADDR by
default if 0 is passed in.
Co-Authored-by: Harald Seiler <hws@denx.de>
Signed-off-by: Claudius Heine <ch@denx.de>
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Add a module to configure the tamper and secure violation of
the SNVS using the SCU API.
The module also adds some commands:
- snvs_cfg: Configure the SNVS HP and LP registers
- snvs_dgo_cfg: Configure the SNVS DGO bloc if present (8QXP)
- tamper_pin_cfg: Change the configuration of the tamper pins
- snvs_clear_status: Allow to write to LPSR and LPTDSR to clear
status bits
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
commit b2f5da9dd0 ("rockchip: rk3399: Add Nanopi M4 board support") added
support for Nanopi M4 board with Dual-Channel 4GB LPDDR3-1866 RAM.
This patch adds another variant of NanoPi M4 board with Dual-Channel
2GB DDR3-1866 RAM.
Signed-off-by: Deepak Das <deepakdas.linux@gmail.com>
Add Firefly ROC-RK3399-PC Mezzanine board which is an
extension board on top of roc-rk3399-pc.
Will drop the separate defconfig file, once we support
the board detection at runtime.
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
