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Merge tag 'u-boot-rockchip-20200501' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip

Browse Source 
- dts clean up to use -u-boot for px30, rk3399 boards
- dts sycn from upstream kernel for rk3328, rk3399
- add rockchip rng driver
- new board support: rk3328-roc-cc, rk3399-roc-pc,Nanopi M4 2GB
This commit is contained in:
Tom Rini 2020-05-04 07:28:14 -04:00
commit 04da42770b
67 changed files with 5134 additions and 2593 deletions
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3
arch/arm/dts/Makefile
View File

@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
rk3328-evb.dtb \
rk3328-roc-cc.dtb \
rk3328-rock64.dtb
dtb-$(CONFIG_ROCKCHIP_RK3368) += \
@ -125,12 +126,14 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-leez-p710.dtb \
rk3399-nanopc-t4.dtb \
rk3399-nanopi-m4.dtb \
rk3399-nanopi-m4-2gb.dtb \
rk3399-nanopi-neo4.dtb \
rk3399-orangepi.dtb \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
rk3399-roc-pc.dtb \
rk3399-roc-pc-mezzanine.dtb \
rk3399-rock-pi-4.dtb \
rk3399-rock960.dtb \
rk3399-rockpro64.dtb

10
arch/arm/dts/cros-ec-keyboard.dtsi
View File

@ -1,11 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Keyboard dts fragment for devices that use cros-ec-keyboard
*
* Copyright (c) 2014 Google, Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/input/input.h>
@ -22,6 +19,7 @@
MATRIX_KEY(0x00, 0x02, KEY_F1)
MATRIX_KEY(0x00, 0x03, KEY_B)
MATRIX_KEY(0x00, 0x04, KEY_F10)
MATRIX_KEY(0x00, 0x05, KEY_RO)
MATRIX_KEY(0x00, 0x06, KEY_N)
MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
@ -34,6 +32,7 @@
MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
MATRIX_KEY(0x01, 0x09, KEY_F9)
MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
MATRIX_KEY(0x01, 0x0c, KEY_HENKAN)
MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
MATRIX_KEY(0x02, 0x01, KEY_TAB)
@ -45,6 +44,7 @@
MATRIX_KEY(0x02, 0x07, KEY_102ND)
MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
MATRIX_KEY(0x02, 0x09, KEY_F8)
MATRIX_KEY(0x02, 0x0a, KEY_YEN)
MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
MATRIX_KEY(0x03, 0x02, KEY_F2)
@ -52,7 +52,9 @@
MATRIX_KEY(0x03, 0x04, KEY_F5)
MATRIX_KEY(0x03, 0x06, KEY_6)
MATRIX_KEY(0x03, 0x08, KEY_MINUS)
MATRIX_KEY(0x03, 0x09, KEY_F13)
MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
MATRIX_KEY(0x03, 0x0c, KEY_MUHENKAN)
MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
MATRIX_KEY(0x04, 0x01, KEY_A)

39
arch/arm/dts/cros-ec-sbs.dtsi
View File

@ -1,8 +1,45 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Smart battery dts fragment for devices that use cros-ec-sbs
*
* Copyright (c) 2015 Google, Inc
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
&i2c_tunnel {

80
arch/arm/dts/px30-evb-u-boot.dtsi
View File

@ -1,84 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
* (C) Copyright 2020 Rockchip Electronics Co., Ltd
*/
/ {
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
};
#include "px30-u-boot.dtsi"
chosen {
u-boot,spl-boot-order = &emmc, &sdmmc;
};
};
&dmc {
u-boot,dm-pre-reloc;
};
&uart2 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&uart5 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
/* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
u-boot,spl-fifo-mode;
};
&emmc {
u-boot,dm-pre-reloc;
/* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
u-boot,spl-fifo-mode;
};
&grf {
u-boot,dm-pre-reloc;
};
&pmugrf {
u-boot,dm-pre-reloc;
};
&xin24m {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
&pmucru {
u-boot,dm-pre-reloc;
};
&saradc {
u-boot,dm-pre-reloc;
&rng {
status = "okay";
};
&gpio0 {
u-boot,dm-pre-reloc;
};
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpio2 {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};

1
arch/arm/dts/px30-evb.dts
View File

@ -8,7 +8,6 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "px30.dtsi"
#include "px30-evb-u-boot.dtsi"
/ {
model = "Rockchip PX30 EVB";

82
arch/arm/dts/px30-firefly-u-boot.dtsi
View File

@ -1,84 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
* (C) Copyright 2020 Rockchip Electronics Co., Ltd
*/
/ {
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
};
chosen {
u-boot,spl-boot-order = &emmc, &sdmmc;
};
};
&dmc {
u-boot,dm-pre-reloc;
};
&uart2 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&uart5 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&emmc {
u-boot,dm-pre-reloc;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&grf {
u-boot,dm-pre-reloc;
};
&pmugrf {
u-boot,dm-pre-reloc;
};
&xin24m {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
&pmucru {
u-boot,dm-pre-reloc;
};
&saradc {
u-boot,dm-pre-reloc;
status = "okay";
};
&gpio0 {
u-boot,dm-pre-reloc;
};
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpio2 {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
#include "px30-u-boot.dtsi"

90
arch/arm/dts/px30-u-boot.dtsi Normal file
View File

@ -0,0 +1,90 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
/ {
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
};
chosen {
u-boot,spl-boot-order = &emmc, &sdmmc;
};
rng: rng@ff0b0000 {
compatible = "rockchip,cryptov2-rng";
reg = <0x0 0xff0b0000 0x0 0x4000>;
status = "disabled";
};
};
&dmc {
u-boot,dm-pre-reloc;
};
&uart2 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&uart5 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&emmc {
u-boot,dm-pre-reloc;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&grf {
u-boot,dm-pre-reloc;
};
&pmugrf {
u-boot,dm-pre-reloc;
};
&xin24m {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
&pmucru {
u-boot,dm-pre-reloc;
};
&saradc {
u-boot,dm-pre-reloc;
status = "okay";
};
&gpio0 {
u-boot,dm-pre-reloc;
};
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpio2 {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};

39
arch/arm/dts/rk3328-evb-u-boot.dtsi
View File

@ -6,6 +6,45 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr3-666.dtsi"
/{
gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_clkin";
#clock-cells = <0>;
};
vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
regulator-name = "vcc5v0_host_xhci";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&gmac2io {
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
pinctrl-names = "default";
pinctrl-0 = <&rgmiim1_pins>;
tx_delay = <0x26>;
rx_delay = <0x11>;
status = "okay";
};
&gmac2phy {
/* Integrated PHY unsupported by U-boot */
status = "broken";
};
&usb_host0_xhci {
vbus-supply = <&vcc5v0_host_xhci>;
status = "okay";

222
arch/arm/dts/rk3328-evb.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
@ -11,40 +11,51 @@
compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
chosen {
stdout-path = &uart2;
stdout-path = "serial2:1500000n8";
};
gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_clkin";
#clock-cells = <0>;
};
vcc3v3_sdmmc: sdmmc-pwren {
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc5v0_otg: vcc5v0-otg-drv {
compatible = "regulator-fixed";
enable-active-high;
regulator-name = "vcc5v0_otg";
gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
};
vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
enable-active-high;
regulator-name = "vcc5v0_host_xhci";
gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
gpio = <&gpio0 30 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0m1_gpio>;
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_io>;
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc_phy: vcc-phy-regulator {
@ -55,96 +66,60 @@
};
};
&saradc {
status = "okay";
};
&uart2 {
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
status = "okay";
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
supports-emmc;
disable-wp;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
&gmac2io {
&gmac2phy {
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
pinctrl-names = "default";
pinctrl-0 = <&rgmiim1_pins>;
tx_delay = <0x26>;
rx_delay = <0x11>;
status = "okay";
};
clock_in_out = "output";
assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
assigned-clock-rate = <50000000>;
assigned-clocks = <&cru SCLK_MAC2PHY>;
assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb20_otg {
vbus-supply = <&vcc5v0_otg>;
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
i2c-scl-falling-time-ns = <4>;
status = "okay";
rk805: pmic@18 {
compatible = "rockchip,rk805";
status = "okay";
reg = <0x18>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
gpio-controller;
#gpio-cells = <2>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_io>;
vcc6-supply = <&vcc_io>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <6001>;
regulator-boot-on;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
@ -155,19 +130,18 @@
regulator-name = "vdd_arm";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <6001>;
regulator-boot-on;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-boot-on;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
@ -177,32 +151,32 @@
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vdd_18: LDO_REG1 {
regulator-name = "vdd_18";
vcc_18: LDO_REG1 {
regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_18emmc: LDO_REG2 {
regulator-name = "vcc_18emmc";
vcc18_emmc: LDO_REG2 {
regulator-name = "vcc18_emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
@ -213,8 +187,8 @@
regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
@ -227,9 +201,71 @@
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins =
<2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio2_a6 */
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdio {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
max-frequency = <150000000>;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
vmmc-supply = <&vcc_sd>;
status = "okay";
};
&tsadc {
status = "okay";
};
&uart2 {
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_host {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&usb20_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};

47
arch/arm/dts/rk3328-roc-cc-u-boot.dtsi Normal file
View File

@ -0,0 +1,47 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
*/
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr4-666.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
};
};
&gpio0 {
u-boot,dm-spl;
};
&pinctrl {
u-boot,dm-spl;
};
&sdmmc0m1_gpio {
u-boot,dm-spl;
};
&pcfg_pull_up_4ma {
u-boot,dm-spl;
};
&usb_host0_xhci {
vbus-supply = <&vcc_host1_5v>;
status = "okay";
};
/*
* This makes XHCI responsible for toggling VBUS. This is needed to work
* around an issue where either XHCI only works with USB 2.0 or OTG doesn't
* work, depending on how VBUS is configured. Having USB 3.0 seems better.
*/
&vcc_host1_5v {
/delete-property/ regulator-always-on;
};
/* Need this and all the pinctrl/gpio stuff above to set pinmux */
&vcc_sd {
u-boot,dm-spl;
};

354
arch/arm/dts/rk3328-roc-cc.dts Normal file
View File

@ -0,0 +1,354 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
*/
/dts-v1/;
#include "rk3328.dtsi"
/ {
model = "Firefly roc-rk3328-cc";
compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
chosen {
stdout-path = "serial2:1500000n8";
};
gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_clkin";
#clock-cells = <0>;
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0m1_gpio>;
regulator-boot-on;
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_io>;
};
vcc_sdio: sdmmcio-regulator {
compatible = "regulator-gpio";
gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>;
states = <1800000 0x1
3300000 0x0>;
regulator-name = "vcc_sdio";
regulator-type = "voltage";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb20_host_drv>;
regulator-name = "vcc_host1_5v";
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
power {
label = "firefly:blue:power";
linux,default-trigger = "heartbeat";
gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
default-state = "on";
mode = <0x23>;
};
user {
label = "firefly:yellow:user";
linux,default-trigger = "mmc1";
gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
default-state = "off";
mode = <0x05>;
};
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
max-frequency = <150000000>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vcc18_emmc>;
status = "okay";
};
&gmac2io {
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
clock_in_out = "input";
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmiim1_pins>;
snps,aal;
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
snps,rxpbl = <0x4>;
snps,txpbl = <0x4>;
tx_delay = <0x24>;
rx_delay = <0x18>;
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmiphy {
status = "okay";
};
&i2c1 {
status = "okay";
rk805: pmic@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
interrupt-parent = <&gpio1>;
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_io>;
vcc6-supply = <&vcc_io>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_io: DCDC_REG4 {
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_18: LDO_REG1 {
regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc18_emmc: LDO_REG2 {
regulator-name = "vcc18_emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_10: LDO_REG3 {
regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
};
};
};
&io_domains {
status = "okay";
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc18_emmc>;
vccio3-supply = <&vcc_sdio>;
vccio4-supply = <&vcc_18>;
vccio5-supply = <&vcc_io>;
vccio6-supply = <&vcc_io>;
pmuio-supply = <&vcc_io>;
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
usb20_host_drv: usb20-host-drv {
rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vcc_sdio>;
status = "okay";
};
&tsadc {
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_host {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&uart2 {
status = "okay";
};
&usb20_otg {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};

11
arch/arm/dts/rk3328-rock64-u-boot.dtsi
View File

@ -12,5 +12,16 @@
};
&usb_host0_xhci {
vbus-supply = <&vcc_host_5v>;
status = "okay";
};
/*
* This makes XHCI responsible for toggling VBUS. This is needed to work
* around an issue where either XHCI only works with USB 2.0 or OTG doesn't
* work, depending on how VBUS is configured. Having USB 3.0 seems better.
*/
&vcc_host_5v {
/delete-property/ regulator-always-on;
/delete-property/ regulator-boot-on;
};

132
arch/arm/dts/rk3328-rock64.dts
View File

@ -43,6 +43,17 @@
vin-supply = <&vcc_sys>;
};
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&usb20_host_drv>;
regulator-name = "vcc_host1_5v";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
@ -51,6 +62,56 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&ir_int>;
pinctrl-names = "default";
};
leds {
compatible = "gpio-leds";
power {
gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
linux,default-trigger = "mmc0";
};
standby {
gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
sound {
compatible = "audio-graph-card";
label = "rockchip,rk3328";
dais = <&i2s1_p0
&spdif_p0>;
};
spdif-dit {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
port {
dit_p0_0: endpoint {
remote-endpoint = <&spdif_p0_0>;
};
};
};
};
&codec {
mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
status = "okay";
port@0 {
codec_p0_0: endpoint {
remote-endpoint = <&i2s1_p0_0>;
};
};
};
&cpu0 {
@ -98,16 +159,26 @@
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmiphy {
status = "okay";
};
&i2c1 {
status = "okay";
rk805: rk805@18 {
rk805: pmic@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
@ -169,7 +240,7 @@
};
vcc_18: LDO_REG1 {
regulator-name = "vdd_18";
regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
@ -181,7 +252,7 @@
};
vcc18_emmc: LDO_REG2 {
regulator-name = "vcc_18emmc";
regulator-name = "vcc18_emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
@ -207,6 +278,18 @@
};
};
&i2s1 {
status = "okay";
i2s1_p0: port {
i2s1_p0_0: endpoint {
dai-format = "i2s";
mclk-fs = <256>;
remote-endpoint = <&codec_p0_0>;
};
};
};
&io_domains {
status = "okay";
@ -220,6 +303,12 @@
};
&pinctrl {
ir {
ir_int: ir-int {
rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
@ -245,6 +334,17 @@
status = "okay";
};
&spdif {
pinctrl-0 = <&spdifm0_tx>;
status = "okay";
spdif_p0: port {
spdif_p0_0: endpoint {
remote-endpoint = <&dit_p0_0>;
};
};
};
&spi0 {
status = "okay";
@ -257,10 +357,28 @@
};
};
&tsadc {
rockchip,hw-tshut-mode = <0>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart2 {
status = "okay";
};
&u2phy {
status = "okay";
u2phy_host: host-port {
status = "okay";
};
u2phy_otg: otg-port {
status = "okay";
};
};
&usb20_otg {
dr_mode = "host";
status = "okay";
@ -273,3 +391,11 @@
&usb_host0_ohci {
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};

4
arch/arm/dts/rk3328-u-boot.dtsi
View File

@ -62,3 +62,7 @@
/* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
u-boot,spl-fifo-mode;
};
&usb20_otg {
hnp-srp-disable;
};

1415
arch/arm/dts/rk3328.dtsi
View File

File diff suppressed because it is too large Load Diff

12
arch/arm/dts/rk3399-evb-u-boot.dtsi
View File

@ -11,3 +11,15 @@
u-boot,spl-boot-order = &sdhci, &sdmmc;
};
};
&rng {
status = "okay";
};
&i2c0 {
u-boot,dm-pre-reloc;
};
&rk808 {
u-boot,dm-pre-reloc;
};

540
arch/arm/dts/rk3399-evb.dts
View File

@ -1,86 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*/
/dts-v1/;
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
/ {
model = "Rockchip RK3399 Evaluation Board";
compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
"google,rk3399evb-rev2";
chosen {
stdout-path = &uart2;
};
vdd_center: vdd-center {
compatible = "pwm-regulator";
pwms = <&pwm3 0 25000 1>;
regulator-name = "vdd_center";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-init-microvolt = <950000>;
regulator-always-on;
regulator-boot-on;
status = "okay";
};
vccsys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vccsys";
regulator-boot-on;
regulator-always-on;
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
vcc5v0_host: vcc5v0-host-en {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
};
vcc5v0_typec0: vcc5v0-typec0-en {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_typec0";
gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
};
vcc5v0_typec1: vcc5v0-typec1-en {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_typec1";
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
backlight: backlight {
compatible = "pwm-backlight";
power-supply = <&vccsys>;
enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
@ -116,18 +48,98 @@
248 249 250 251 252 253 254 255>;
default-brightness-level = <200>;
pwms = <&pwm0 0 25000 0>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
pwm-delay-us = <10000>;
status = "disabled";
};
panel:panel {
compatible = "simple-panel";
power-supply = <&vcc33_lcd>;
edp_panel: edp-panel {
compatible ="lg,lp079qx1-sp0v";
backlight = <&backlight>;
/*enable-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;*/
status = "disabled";
enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
power-supply = <&vcc3v3_s0>;
port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
};
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
vdd_center: vdd-center {
compatible = "pwm-regulator";
pwms = <&pwm3 0 25000 0>;
regulator-name = "vdd_center";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
status = "okay";
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
vin-supply = <&vcc5v0_sys>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
};
&edp {
status = "okay";
force-hpd;
ports {
edp_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
edp_out_panel: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in_edp>;
};
};
};
};
@ -135,6 +147,244 @@
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
};
&i2c0 {
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio1>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
vcc10-supply = <&vcc3v3_sys>;
vcc11-supply = <&vcc3v3_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc1v8_pmu>;
regulators {
vdd_log: DCDC_REG1 {
regulator-name = "vdd_log";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-name = "vdd_cpu_l";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-name = "vcc_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc1v8_dvp: LDO_REG1 {
regulator-name = "vcc1v8_dvp";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v0_tp: LDO_REG2 {
regulator-name = "vcc3v0_tp";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_pmu: LDO_REG3 {
regulator-name = "vcc1v8_pmu";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_sd: LDO_REG4 {
regulator-name = "vcc_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcca3v0_codec: LDO_REG5 {
regulator-name = "vcca3v0_codec";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v5: LDO_REG6 {
regulator-name = "vcc_1v5";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcca1v8_codec: LDO_REG7 {
regulator-name = "vcca1v8_codec";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v0: LDO_REG8 {
regulator-name = "vcc_3v0";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc3v3_s3: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&pwm0 {
status = "okay";
};
@ -147,15 +397,6 @@
status = "okay";
};
&saradc {
status = "okay";
};
&sdmmc {
bus-width = <4>;
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
@ -164,6 +405,36 @@
status = "okay";
};
&pcie_phy {
status = "disabled";
};
&pcie0 {
ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>;
status = "disabled";
};
&u2phy0 {
status = "okay";
};
&u2phy0_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&u2phy1 {
status = "okay";
};
&u2phy1_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&uart2 {
status = "okay";
};
@ -176,11 +447,6 @@
status = "okay";
};
&usbdrd3_0 {
vbus-supply = <&vcc5v0_typec0>;
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
@ -189,92 +455,26 @@
status = "okay";
};
&usbdrd3_1 {
vbus-supply = <&vcc5v0_typec1>;
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
i2c-scl-falling-time-ns = <50>;
i2c-scl-rising-time-ns = <100>;
u-boot,dm-pre-reloc;
rk808: pmic@1b {
compatible = "rockchip,rk808";
clock-output-names = "xin32k", "wifibt_32kin";
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
reg = <0x1b>;
rockchip,system-power-controller;
#clock-cells = <1>;
u-boot,dm-pre-reloc;
status = "okay";
vcc12-supply = <&vcc3v3_sys>;
regulators {
vcc33_lcd: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc33_lcd";
};
};
};
};
&mipi_dsi {
status = "disabled";
rockchip,panel = <&panel>;
display-timings {
timing0 {
bits-per-pixel = <24>;
clock-frequency = <160000000>;
hfront-porch = <120>;
hsync-len = <20>;
hback-porch = <21>;
hactive = <1200>;
vfront-porch = <21>;
vsync-len = <3>;
vback-porch = <18>;
vactive = <1920>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
<1 21 RK_FUNC_GPIO &pcfg_pull_up>;
<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
pmic_dvs2: pmic-dvs2 {
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins =
<1 18 RK_FUNC_GPIO &pcfg_pull_down>;
<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&gmac {
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
tx_delay = <0x28>;
rx_delay = <0x11>;
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};

6
arch/arm/dts/rk3399-ficus.dts
View File

@ -146,6 +146,12 @@
};
};
&spi1 {
/* On both Low speed and High speed expansion */
cs-gpios = <0>, <&gpio4 RK_PA6 0>, <&gpio4 RK_PA7 0>;
status = "okay";
};
&usbdrd_dwc3_0 {
dr_mode = "host";
};

251
arch/arm/dts/rk3399-firefly.dts
View File

@ -1,19 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
/ {
model = "Firefly-RK3399 Board";
compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
chosen {
stdout-path = &uart2;
stdout-path = "serial2:1500000n8";
};
backlight: backlight {
@ -63,6 +64,48 @@
#clock-cells = <0>;
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
linux,code = <KEY_POWER>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
work-led {
label = "work";
default-state = "on";
gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
};
diy-led {
label = "diy";
default-state = "off";
gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
};
};
rt5640-sound {
compatible = "simple-audio-card";
simple-audio-card,name = "rockchip,rt5640-codec";
@ -102,15 +145,27 @@
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8>;
};
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_drv>;
pinctrl-0 = <&pcie_pwr_en>;
regulator-name = "vcc3v3_pcie";
regulator-always-on;
regulator-boot-on;
vin-supply = <&dc_12v>;
};
vcc3v3_sys: vcc3v3-sys {
@ -120,32 +175,29 @@
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_sys>;
};
/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc5v0_sys: vcc5v0-sys {
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
vin-supply = <&dc_12v>;
};
vdd_log: vdd-log {
@ -156,16 +208,7 @@
regulator-boot-on;
regulator-min-microvolt = <430000>;
regulator-max-microvolt = <1400000>;
regulator-init-microvolt = <950000>;
};
vccadc_ref: vccadc-ref {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_sys>;
};
};
@ -201,15 +244,22 @@
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc_phy>;
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x33>;
rx_delay = <0x45>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
@ -231,16 +281,16 @@
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
vcc10-supply = <&vcc3v3_sys>;
vcc11-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc_sys>;
vcc10-supply = <&vcc_sys>;
vcc11-supply = <&vcc_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc1v8_pmu>;
@ -301,12 +351,12 @@
};
};
vcc3v0_tp: LDO_REG2 {
regulator-name = "vcc3v0_tp";
vcc2v8_dvp: LDO_REG2 {
regulator-name = "vcc2v8_dvp";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
@ -324,8 +374,8 @@
};
};
vcc_sd: LDO_REG4 {
regulator-name = "vcc_sd";
vcc_sdio: LDO_REG4 {
regulator-name = "vcc_sdio";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
@ -382,7 +432,7 @@
};
};
vcc3v3_s3: SWITCH_REG1 {
vcc3v3_s3: vcc_lan: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
@ -412,7 +462,7 @@
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
@ -429,7 +479,7 @@
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
vin-supply = <&vcc_sys>;
regulator-state-mem {
regulator-off-in-suspend;
@ -476,19 +526,16 @@
&i2s0 {
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
#sound-dai-cells = <0>;
status = "okay";
};
&i2s1 {
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
#sound-dai-cells = <0>;
status = "okay";
};
&i2s2 {
#sound-dai-cells = <0>;
status = "okay";
};
@ -497,7 +544,7 @@
bt656-supply = <&vcc1v8_dvp>;
audio-supply = <&vcca1v8_codec>;
sdmmc-supply = <&vcc_sd>;
sdmmc-supply = <&vcc_sdio>;
gpio1830-supply = <&vcc_3v0>;
};
@ -509,7 +556,7 @@
ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn>;
pinctrl-0 = <&pcie_clkreqn_cpm>;
status = "okay";
};
@ -532,7 +579,7 @@
};
pcie {
pcie_drv: pcie-drv {
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
@ -570,10 +617,26 @@
};
usb2 {
host_vbus_drv: host-vbus-drv {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
wifi_host_wake_l: wifi-host-wake-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
work_led_gpio: work_led-gpio {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
diy_led_gpio: diy_led-gpio {
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {
@ -585,24 +648,70 @@
};
&saradc {
vref-supply = <&vccadc_ref>;
vref-supply = <&vcca1v8_s3>;
status = "okay";
};
&sdio0 {
/* WiFi & BT combo module Ampak AP6356S */
bus-width = <4>;
cap-sdio-irq;
cap-sd-highspeed;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
/* Power supply */
vqmmc-supply = &vcc1v8_s3; /* IO line */
vmmc-supply = &vcc_sdio; /* card's power */
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wake";
brcm,drive-strength = <5>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
status = "okay";
};
&sdhci {
bus-width = <8>;
keep-power-in-suspend;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&tcphy0 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
@ -662,3 +771,37 @@
&usb_host1_ohci {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "otg";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

16
arch/arm/dts/rk3399-gru-bob.dts
View File

@ -18,11 +18,11 @@
"google,bob", "google,gru", "rockchip,rk3399";
edp_panel: edp-panel {
compatible = "boe,nv101wxmn51", "simple-panel";
compatible = "boe,nv101wxmn51";
backlight = <&backlight>;
power-supply = <&pp3300_disp>;
ports {
port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
@ -68,12 +68,22 @@
&spi0 {
status = "okay";
cr50@0 {
compatible = "google,cr50";
reg = <0>;
interrupt-parent = <&gpio0>;
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&h1_int_od_l>;
spi-max-frequency = <800000>;
};
};
&pinctrl {
tpm {
h1_int_od_l: h1-int-od-l {
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};

40
arch/arm/dts/rk3399-gru-chromebook.dtsi
View File

@ -194,20 +194,25 @@
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44
45 46 47 48 49 50 51 52 53 54 55 56 57 58
59 60 61 62 63 64 65 66 67 68 69 70 71 72
73 74 75 76 77 78 79 80 81 82 83 84 85 86
87 88 89 90 91 92 93 94 95 96 97 98 99 100>;
default-brightness-level = <51>;
enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
power-supply = <&pp3300_disp>;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwm-delay-us = <10000>;
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l>;
wake_on_bt: wake-on-bt {
label = "Wake-on-Bluetooth";
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
wakeup-source;
};
};
};
&ppvar_bigcpu {
@ -232,7 +237,6 @@
&edp {
status = "okay";
rockchip,panel = <&edp_panel>;
ports {
edp_out: port@1 {
reg = <1>;
@ -287,11 +291,9 @@ ap_i2c_tp: &i2c5 {
#pwm-cells = <1>;
};
usbc_extcon1: extcon@1 {
usbc_extcon1: extcon1 {
compatible = "google,extcon-usbc-cros-ec";
google,usb-port-id = <1>;
#extcon-cells = <0>;
};
};
@ -361,27 +363,27 @@ ap_i2c_tp: &i2c5 {
&pinctrl {
discrete-regulators {
pp1500_en: pp1500-en {
rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO
&pcfg_pull_none>;
};
pp1800_audio_en: pp1800-audio-en {
rockchip,pins = <RK_GPIO0 2 RK_FUNC_GPIO
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO
&pcfg_pull_down>;
};
pp3000_en: pp3000-en {
rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO
&pcfg_pull_none>;
};
pp3300_disp_en: pp3300-disp-en {
rockchip,pins = <RK_GPIO4 27 RK_FUNC_GPIO
rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO
&pcfg_pull_none>;
};
wlan_module_pd_l: wlan-module-pd-l {
rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO
&pcfg_pull_down>;
};
};
@ -389,10 +391,10 @@ ap_i2c_tp: &i2c5 {
&wifi {
wifi_perst_l: wifi-perst-l {
rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
wlan_host_wake_l: wlan-host-wake-l {
rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};

34
arch/arm/dts/rk3399-gru-kevin.dts
View File

@ -39,11 +39,25 @@
};
edp_panel: edp-panel {
compatible = "sharp,lq123p1jx31", "simple-panel";
compatible = "sharp,lq123p1jx31";
backlight = <&backlight>;
power-supply = <&pp3300_disp>;
ports {
panel-timing {
clock-frequency = <266666667>;
hactive = <2400>;
hfront-porch = <48>;
hback-porch = <84>;
hsync-len = <32>;
hsync-active = <0>;
vactive = <1600>;
vfront-porch = <3>;
vback-porch = <120>;
vsync-len = <10>;
vsync-active = <0>;
};
port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
@ -118,13 +132,17 @@
map0 {
trip = <&ppvar_bigcpu_alert>;
cooling-device =
<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <4096>;
};
map1 {
trip = <&ppvar_bigcpu_alert>;
cooling-device =
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
@ -286,24 +304,24 @@ ap_i2c_dig: &i2c2 {
digitizer {
/* Has external pullup */
cpu1_dig_irq_l: cpu1-dig-irq-l {
rockchip,pins = <2 4 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
/* Has external pullup */
cpu1_dig_pdct_l: cpu1-dig-pdct-l {
rockchip,pins = <2 5 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
discrete-regulators {
cpu3_pen_pwr_en: cpu3-pen-pwr-en {
rockchip,pins = <4 30 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pen {
cpu1_pen_eject: cpu1-pen-eject {
rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};

89
arch/arm/dts/rk3399-gru.dtsi
View File

@ -11,13 +11,7 @@
/ {
chosen {
u-boot,dm-pre-reloc;
stdout-path = "serial2:115200n8";
u-boot,spl-boot-order = &spi_flash;
};
config {
u-boot,spl-payload-offset = <0x40000>;
};
/*
@ -268,17 +262,11 @@
pp5000_usb_a_vbus: pp5000 {
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l>;
wake_on_bt: wake-on-bt {
label = "Wake-on-Bluetooth";
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
wakeup-source;
};
ap_rtc_clk: ap-rtc-clk {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "xin32k";
#clock-cells = <0>;
};
max98357a: max98357a {
@ -549,8 +537,7 @@ ap_i2c_audio: &i2c8 {
pinctrl-names = "default", "sleep";
pinctrl-1 = <&spi1_sleep>;
spi_flash: spiflash@0 {
u-boot,dm-pre-reloc;
spiflash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
@ -565,16 +552,12 @@ ap_i2c_audio: &i2c8 {
&spi5 {
status = "okay";
spi-activate-delay = <100>;
spi-max-frequency = <3000000>;
spi-deactivate-delay = <200>;
cros_ec: ec@0 {
compatible = "google,cros-ec-spi";
reg = <0>;
interrupt-parent = <&gpio0>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
ec-interrupt = <&gpio0 1 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ec_ap_int_l>;
spi-max-frequency = <3000000>;
@ -586,11 +569,9 @@ ap_i2c_audio: &i2c8 {
#size-cells = <0>;
};
usbc_extcon0: extcon@0 {
usbc_extcon0: extcon0 {
compatible = "google,extcon-usbc-cros-ec";
google,usb-port-id = <0>;
#extcon-cells = <0>;
};
};
};
@ -692,29 +673,29 @@ ap_i2c_audio: &i2c8 {
backlight-enable {
bl_en: bl-en {
rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
cros-ec {
ec_ap_int_l: ec-ap-int-l {
rockchip,pins = <RK_GPIO0 1 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
discrete-regulators {
sd_io_pwr_en: sd-io-pwr-en {
rockchip,pins = <RK_GPIO2 2 RK_FUNC_GPIO
rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO
&pcfg_pull_none>;
};
sd_pwr_1800_sel: sd-pwr-1800-sel {
rockchip,pins = <RK_GPIO2 28 RK_FUNC_GPIO
rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO
&pcfg_pull_none>;
};
sd_slot_pwr_en: sd-slot-pwr-en {
rockchip,pins = <RK_GPIO4 29 RK_FUNC_GPIO
rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO
&pcfg_pull_none>;
};
};
@ -722,17 +703,17 @@ ap_i2c_audio: &i2c8 {
codec {
/* Has external pullup */
headset_int_l: headset-int-l {
rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
};
mic_int: mic-int {
rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>;
rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
max98357a {
sdmode_en: sdmode-en {
rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>;
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
@ -743,7 +724,7 @@ ap_i2c_audio: &i2c8 {
* to hack this as gpio, so the EP could be able to
* de-assert it along and make ClockPM(CPM) work.
*/
rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@ -754,20 +735,20 @@ ap_i2c_audio: &i2c8 {
*/
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins =
<4 8 RK_FUNC_1 &pcfg_pull_none_8ma>,
<4 9 RK_FUNC_1 &pcfg_pull_none_8ma>,
<4 10 RK_FUNC_1 &pcfg_pull_none_8ma>,
<4 11 RK_FUNC_1 &pcfg_pull_none_8ma>;
<4 RK_PB0 1 &pcfg_pull_none_8ma>,
<4 RK_PB1 1 &pcfg_pull_none_8ma>,
<4 RK_PB2 1 &pcfg_pull_none_8ma>,
<4 RK_PB3 1 &pcfg_pull_none_8ma>;
};
sdmmc_clk: sdmmc-clk {
rockchip,pins =
<4 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
<4 RK_PB4 1 &pcfg_pull_none_8ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins =
<4 13 RK_FUNC_1 &pcfg_pull_none_8ma>;
<4 RK_PB5 1 &pcfg_pull_none_8ma>;
};
/*
@ -781,12 +762,12 @@ ap_i2c_audio: &i2c8 {
*/
sdmmc_cd: sdmmc-cd {
rockchip,pins =
<0 7 RK_FUNC_1 &pcfg_pull_none>;
<0 RK_PA7 1 &pcfg_pull_none>;
};
/* This is where we actually hook up CD; has external pull */
sdmmc_cd_gpio: sdmmc-cd-gpio {
rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@ -796,47 +777,47 @@ ap_i2c_audio: &i2c8 {
* Pull down SPI1 CLK/CS/RX/TX during suspend, to
* prevent leakage.
*/
rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>,
<1 10 RK_FUNC_GPIO &pcfg_pull_down>,
<1 7 RK_FUNC_GPIO &pcfg_pull_down>,
<1 8 RK_FUNC_GPIO &pcfg_pull_down>;
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>,
<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>,
<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>,
<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
touchscreen {
touch_int_l: touch-int-l {
rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
};
touch_reset_l: touch-reset-l {
rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
trackpad {
ap_i2c_tp_pu_en: ap-i2c-tp-pu-en {
rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>;
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>;
};
trackpad_int_l: trackpad-int-l {
rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
wifi: wifi {
wlan_module_reset_l: wlan-module-reset-l {
rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
/* Kevin has an external pull up, but Gru does not */
rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
write-protect {
ap_fw_wp: ap-fw-wp {
rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};

3
arch/arm/dts/rk3399-khadas-edge.dtsi
View File

@ -654,9 +654,12 @@
sd-uhs-sdr104;
vqmmc-supply = <&vcc1v8_s3>;
vmmc-supply = <&vccio_sd>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;

36
arch/arm/dts/rk3399-leez-p710.dts
View File

@ -42,14 +42,14 @@
regulator-max-microvolt = <5000000>;
};
vcc5v0_sys: vcc5v0-sys {
vcc3v3_lan: vcc3v3-lan {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-name = "vcc3v3_lan";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc5v_adp>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vim-supply = <&vcc3v3_sys>;
};
vcc3v3_sys: vcc3v3-sys {
@ -83,14 +83,14 @@
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_lan: vcc3v3-lan {
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_lan";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vim-supply = <&vcc3v3_sys>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc5v_adp>;
};
vdd_log: vdd-log {
@ -510,6 +510,14 @@
};
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
@ -522,14 +530,6 @@
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&tcphy0 {
status = "okay";
};

47
arch/arm/dts/rk3399-nanopc-t4.dts
View File

@ -52,13 +52,58 @@
pinctrl-names = "default";
pinctrl-0 = <&ir_rx>;
};
fan: pwm-fan {
compatible = "pwm-fan";
/*
* With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels
* work out to 0, ~1200, ~3000, and 5000RPM respectively.
*/
cooling-levels = <0 12 18 255>;
#cooling-cells = <2>;
fan-supply = <&vcc12v0_sys>;
pwms = <&pwm1 0 50000 0>;
};
};
&cpu_thermal {
trips {
cpu_warm: cpu_warm {
temperature = <55000>;
hysteresis = <2000>;
type = "active";
};
cpu_hot: cpu_hot {
temperature = <65000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map2 {
trip = <&cpu_warm>;
cooling-device = <&fan THERMAL_NO_LIMIT 1>;
};
map3 {
trip = <&cpu_hot>;
cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
};
};
};
&pcie0 {
num-lanes = <4>;
vpcie3v3-supply = <&vcc3v3_sys>;
};
&pinctrl {
ir {
ir_rx: ir-rx {
/* external pullup to VCC3V3_SYS, despite being 1.8V :/ */
rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>;
};
};
};

8
arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi Normal file
View File

@ -0,0 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
* Copyright (C) 2020 Deepak Das <deepakdas.linux@gmail.com>
*/
#include "rk3399-nanopi4-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1866.dtsi"

66
arch/arm/dts/rk3399-nanopi-m4-2gb.dts Normal file
View File

@ -0,0 +1,66 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* FriendlyElec NanoPi M4 board device tree source
*
* Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
* (http://www.friendlyarm.com)
*
* Copyright (c) 2018 Collabora Ltd.
* Copyright (c) 2019 Arm Ltd.
*/
/dts-v1/;
#include "rk3399-nanopi4.dtsi"
/ {
model = "FriendlyElec NanoPi M4";
compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399";
vdd_5v: vdd-5v {
compatible = "regulator-fixed";
regulator-name = "vdd_5v";
regulator-always-on;
regulator-boot-on;
};
vcc5v0_core: vcc5v0-core {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_core";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vdd_5v>;
};
vcc5v0_usb1: vcc5v0-usb1 {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb1";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_usb2: vcc5v0-usb2 {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb2";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
};
&vcc3v3_sys {
vin-supply = <&vcc5v0_core>;
};
&u2phy0_host {
phy-supply = <&vcc5v0_usb1>;
};
&u2phy1_host {
phy-supply = <&vcc5v0_usb2>;
};
&vbus_typec {
regulator-always-on;
vin-supply = <&vdd_5v>;
};

66
arch/arm/dts/rk3399-nanopi4.dtsi
View File

@ -48,7 +48,7 @@
};
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
vcc1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
@ -71,6 +71,27 @@
vin-supply = <&vcc3v3_sys>;
};
/*
* Really, this is supplied by vcc_1v8, and vcc1v8_s3 only
* drives the enable pin, but we can't quite model that.
*/
vcca0v9_s3: vcca0v9-s3 {
compatible = "regulator-fixed";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vcca0v9_s3";
vin-supply = <&vcc1v8_s3>;
};
/* As above, actually supplied by vcc3v3_sys */
vcca1v8_s3: vcca1v8-s3 {
compatible = "regulator-fixed";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_s3";
vin-supply = <&vcc1v8_s3>;
};
vbus_typec: vbus-typec {
compatible = "regulator-fixed";
regulator-min-microvolt = <5000000>;
@ -148,15 +169,28 @@
assigned-clocks = <&cru SCLK_RMII_SRC>;
clock_in_out = "input";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
phy-handle = <&rtl8211e>;
phy-mode = "rgmii";
phy-supply = <&vcc3v3_s3>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
rtl8211e: phy@1 {
reg = <1>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
};
};
};
&gpu {
@ -171,6 +205,10 @@
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <160>;
@ -446,6 +484,10 @@
status = "okay";
};
&i2s2 {
status = "okay";
};
&io_domains {
bt656-supply = <&vcc_1v8>;
audio-supply = <&vcca1v8_codec>;
@ -464,7 +506,9 @@
&pcie0 {
ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
max-link-speed = <2>;
num-lanes = <4>;
num-lanes = <2>;
vpcie0v9-supply = <&vcca0v9_s3>;
vpcie1v8-supply = <&vcca1v8_s3>;
status = "okay";
};
@ -481,6 +525,16 @@
};
};
phy {
phy_intb: phy-intb {
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
phy_rstb: phy-rstb {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
cpu_b_sleep: cpu-b-sleep {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;

79
arch/arm/dts/rk3399-orangepi.dts
View File

@ -136,13 +136,13 @@
vin-supply = <&vcc_sys>;
};
vcc5v0_typec0: vcc5v0-typec0-regulator {
vbus_typec: vbus-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec0_en>;
regulator-name = "vcc5v0_typec0";
pinctrl-0 = <&vcc5v0_typec_en>;
regulator-name = "vbus_typec";
vin-supply = <&vcc_sys>;
};
@ -202,14 +202,27 @@
clock_in_out = "input";
phy-supply = <&vcc3v3_s3>;
phy-mode = "rgmii";
phy-handle = <&rtl8211e>;
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
rtl8211e: phy@1 {
reg = <1>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
};
};
};
&gpu {
@ -419,6 +432,8 @@
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&cpu_b_sleep>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@ -436,6 +451,8 @@
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&gpu_sleep>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
@ -472,6 +489,7 @@
compatible = "asahi-kasei,ak09911";
reg = <0x0c>;
vdd-supply = <&vcc3v3_s3>;
vid-supply = <&vcc3v3_s3>;
};
mpu6500@68 {
@ -504,6 +522,16 @@
pinctrl-0 = <&light_int_l>;
vdd-supply = <&vcc3v3_s3>;
};
fusb302@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&chg_cc_int_l>;
vbus-supply = <&vbus_typec>;
};
};
&io_domains {
@ -526,7 +554,25 @@
};
};
phy {
phy_intb: phy-intb {
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
phy_rstb: phy-rstb {
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
cpu_b_sleep: cpu-b-sleep {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
gpu_sleep: gpu-sleep {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
pmic_int_l: pmic-int-l {
rockchip,pins =
<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
@ -536,7 +582,7 @@
sd {
sdmmc0_pwr_h: sdmmc0-pwr-h {
rockchip,pins =
<RK_GPIO0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
<0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@ -546,7 +592,7 @@
<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
vcc5v0_typec0_en: vcc5v0-typec0-en {
vcc5v0_typec_en: vcc5v0-typec-en {
rockchip,pins =
<1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
@ -595,6 +641,12 @@
rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
fusb302 {
chg_cc_int_l: chg-cc-int-l {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pwm0 {
@ -631,9 +683,12 @@
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
@ -676,7 +731,7 @@
status = "okay";
u2phy0_otg: otg-port {
phy-supply = <&vcc5v0_typec0>;
phy-supply = <&vbus_typec>;
status = "okay";
};
@ -707,12 +762,14 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
clock-names = "ext_clock";
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>;
vbat-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8>;
};
};

31
arch/arm/dts/rk3399-puma-u-boot.dtsi
View File

@ -13,7 +13,7 @@
chosen {
stdout-path = "serial0:115200n8";
u-boot,spl-boot-order = \
"same-as-spl", &spiflash, &sdhci, &sdmmc;
"same-as-spl", &norflash, &sdhci, &sdmmc;
};
aliases {
@ -21,4 +21,33 @@
spi1 = &spi5;
};
/*
* The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
* eMMC and SPI flash powered-down initially (in fact it keeps the
* reset signal asserted). Even though it is an enable signal, we
* model this as a regulator.
*/
bios_enable: bios_enable {
compatible = "regulator-fixed";
u-boot,dm-pre-reloc;
regulator-name = "bios_enable";
enable-active-high;
gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&norflash {
u-boot,dm-pre-reloc;
};

602
arch/arm/dts/rk3399-puma.dtsi
View File

@ -1,30 +1,74 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
*/
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
/ {
model = "Theobroma Systems RK3399-Q7 SoM";
compatible = "tsd,rk3399-q7", "tsd,puma", "rockchip,rk3399";
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins_puma>;
pinctrl-0 = <&led_pin_module>;
module_led {
module-led {
label = "module_led";
gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
panic-indicator;
};
};
sd_card_led {
label = "sd_card_led";
gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
/*
* Overwrite the opp-table for CPUB as this board uses a different
* regulator (FAN53555) that only allows 10mV steps and therefore
* can't reach the operation point target voltages from rk3399-opp.dtsi
*/
/delete-node/ opp-table1;
cluster1_opp: opp-table1 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <800000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <800000>;
};
opp02 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <830000>;
opp-suspend;
};
opp03 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <880000>;
};
opp04 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <950000>;
};
opp05 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1030000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <1100000>;
};
opp07 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1200000>;
};
opp08 {
opp-hz = /bits/ 64 <1992000000>;
opp-microvolt = <1230000>;
turbo-mode;
};
};
@ -35,79 +79,14 @@
#clock-cells = <0>;
};
dw_hdmi_audio: dw-hdmi-audio {
status = "enabled";
compatible = "rockchip,dw-hdmi-audio";
#sound-dai-cells = <0>;
};
hdmi_codec: hdmi-codec {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "HDMI-CODEC";
simple-audio-card,cpu {
sound-dai = <&i2s2>;
};
simple-audio-card,codec {
sound-dai = <&hdmi>;
};
};
hdmi_sound: hdmi-sound {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "rockchip,hdmi";
simple-audio-card,cpu {
sound-dai = <&i2s2>;
};
simple-audio-card,codec {
sound-dai = <&hdmi>;
};
};
usbhub_enable: usbhub_enable {
vcc1v2_phy: vcc1v2-phy {
compatible = "regulator-fixed";
regulator-name = "usbhub_enable";
enable-active-low;
gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
/*
* The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
* eMMC and SPI flash powered-down initially (in fact it keeps the
* reset signal asserted). Even though it is an enable signal, we
* model this as a regulator.
*/
bios_enable: bios_enable {
compatible = "regulator-fixed";
u-boot,dm-pre-reloc;
regulator-name = "bios_enable";
enable-active-high;
gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
regulator-name = "vcc1v2_phy";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vccadc_ref: vccadc-ref {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
vin-supply = <&vcc5v0_sys>;
};
vcc3v3_sys: vcc3v3-sys {
@ -117,16 +96,18 @@
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_otg: vcc5v0-otg-regulator {
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
enable-active-low;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc5v0_otg";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
regulator-always-on;
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_sys: vcc5v0-sys {
@ -137,48 +118,55 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
regulator-name = "vdd_log";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <950000>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&emmc_phy {
status = "okay";
drive-impedance-ohm = <33>;
};
&gmac {
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <2 10000 50000>;
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc1v2_phy>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x10>;
rx_delay = <0x10>;
status = "okay";
};
&hdmi {
#sound-dai-cells = <0>;
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
@ -188,37 +176,17 @@
i2c-scl-falling-time-ns = <4>;
clock-frequency = <400000>;
vdd_gpu: vdd_gpu {
status = "okay";
compatible = "fcs,fan53555";
reg = <0x60>;
vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_sys>;
regulator-compatible = "fan53555-reg";
regulator-name = "vdd_gpu";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1230000>;
regulator-ramp-delay = <1000>;
fcs,suspend-voltage-selector = <1>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio1>;
interrupts = <22 IRQ_TYPE_LEVEL_LOW>; // TODO check interrupt?
interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
@ -235,44 +203,44 @@
regulators {
vdd_center: DCDC_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd_center";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-name = "vdd_center";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd_cpu_l";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-name = "vdd_cpu_l";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
@ -280,32 +248,32 @@
};
vcc_ldo1: LDO_REG1 {
regulator-boot-on;
regulator-name = "vcc_ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_ldo1";
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_hdmi: LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc1v8_hdmi";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_hdmi";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_pmu: LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc1v8_pmu";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
@ -313,11 +281,11 @@
};
vcc_sd: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc_sd";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
@ -325,79 +293,105 @@
};
vcc_ldo5: LDO_REG5 {
regulator-boot-on;
regulator-name = "vcc_ldo5";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc_ldo5";
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ldo6: LDO_REG6 {
regulator-boot-on;
regulator-name = "vcc_ldo6";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc_ldo6";
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc0v9_hdmi: LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc0v9_hdmi";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vcc0v9_hdmi";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_efuse: LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_efuse";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_efuse";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s3: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc3v3_s3";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_gpu: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1230000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
};
};
&i2c7 {
status = "okay";
clock-frequency = <400000>;
fan: fan@18 {
compatible = "ti,amc6821";
reg = <0x18>;
#cooling-cells = <2>;
};
rtc_twi: rtc@6f {
compatible = "isil,isl1208";
reg = <0x6f>;
};
};
&i2c8 {
status = "okay";
clock-frequency = <400000>;
vdd_cpu_b: vdd_cpu_b {
status = "okay";
vdd_cpu_b: regulator@60 {
compatible = "fcs,fan53555";
reg = <0x60>;
vsel-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_sys>;
regulator-compatible = "fan53555-reg";
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1230000>;
@ -405,48 +399,36 @@
fcs,suspend-voltage-selector = <1>;
regulator-always-on;
regulator-boot-on;
regulator-initial-state = <3>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2s0 {
pinctrl-0 = <&i2s0_2ch_bus>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "okay";
rockchip,i2s-broken-burst-len;
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
#sound-dai-cells = <0>;
};
&i2s2 {
#sound-dai-cells = <0>;
status = "okay";
/*
* As Q7 does not specify neither a global nor a RX clock for I2S these
* signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO.
* Therefore we have to redefine the i2s0_2ch_bus definition to prevent
* conflicts.
*/
&i2s0_2ch_bus {
rockchip,pins =
<3 RK_PD0 1 &pcfg_pull_none>,
<3 RK_PD2 1 &pcfg_pull_none>,
<3 RK_PD3 1 &pcfg_pull_none>,
<3 RK_PD7 1 &pcfg_pull_none>;
};
&io_domains {
status = "okay";
bt656-supply = <&vcc_1v8>; /* bt656_gpio2ab_ms */
audio-supply = <&vcc_1v8>; /* audio_gpio3d4a_ms */
sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
gpio1830-supply = <&vcc_1v8>; /* gpio1833_gpio4cd_ms */
};
&pcie0 {
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
assigned-clock-rates = <100000000>;
ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn>;
status = "okay";
};
&pcie_phy {
status = "okay";
bt656-supply = <&vcc_1v8>;
audio-supply = <&vcc_1v8>;
sdmmc-supply = <&vcc_sd>;
gpio1830-supply = <&vcc_1v8>;
};
&pmu_io_domains {
@ -454,195 +436,99 @@
pmu1830-supply = <&vcc_1v8>;
};
&pwm0 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
supports-emmc;
non-removable;
keep-power-in-suspend;
mmc-hs400-enhanced-strobe;
status = "okay";
};
&sdmmc {
clock-frequency = <150000000>;
max-frequency = <40000000>;
supports-sd;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
num-slots = <1>;
vqmmc-supply = <&vcc_sd>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "disabled";
};
&usb_host0_ohci {
status = "disabled";
};
&usbdrd3_0 {
status = "okay";
};
&usb_host1_ehci {
status = "disabled";
};
&usb_host1_ohci {
status = "disabled";
};
&usbdrd3_1 {
status = "okay";
tsd,usb-port-power = "usbhub_enable";
};
&vopb {
status = "okay";
};
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&pinctrl {
/* Pins that are not explicitely used by any devices */
pinctrl-names = "default";
pinctrl-0 = <&puma_pin_hog>;
hog {
puma_pin_hog: puma_pin_hog {
i2c8 {
i2c8_xfer_a: i2c8-xfer {
rockchip,pins =
/* We need pull-ups on Q7 buttons */
<RK_GPIO0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, /* LID_BTN# */
<RK_GPIO0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, /* BATLOW# */
<RK_GPIO0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, /* SLP_BTN# */
<RK_GPIO0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; /* BIOS_DISABLE# */
<1 RK_PC4 1 &pcfg_pull_up>,
<1 RK_PC5 1 &pcfg_pull_up>;
};
};
leds {
led_pin_module: led-module-gpio {
rockchip,pins =
<2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
<RK_GPIO1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
<1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds_pins_puma: led_pins@0 {
rockchip,pins =
<RK_GPIO2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>,
<RK_GPIO1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
usb2 {
otg_vbus_drv: otg-vbus-drv {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins =
<RK_GPIO0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
host_vbus_drv: host-vbus-drv {
rockchip,pins =
<RK_GPIO4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
i2c8 {
i2c8_xfer_a: i2c8-xfer {
rockchip,pins =
<RK_GPIO1 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
<RK_GPIO1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
<4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
};
&i2c2 {
status = "okay";
clock-frequency = <400000>;
};
&i2c4 {
status = "okay";
clock-frequency = <400000>;
};
&i2c6 {
status = "okay";
clock-frequency = <400000>;
};
&i2c6_xfer {
/* Enable pull-ups, the pins would float otherwise. */
rockchip,pins =
<RK_GPIO2 RK_PB2 RK_FUNC_2 &pcfg_pull_up>,
<RK_GPIO2 RK_PB1 RK_FUNC_2 &pcfg_pull_up>;
};
&i2c7 {
status = "okay";
clock-frequency = <400000>;
rtc_twi: rtc@6f {
compatible = "isil,isl1208";
reg = <0x6f>;
};
fan: fan@18 {
compatible = "ti,amc6821";
reg = <0x18>;
cooling-min-state = <0>;
cooling-max-state = <9>;
#cooling-cells = <2>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts>;
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&sdmmc {
vqmmc-supply = <&vcc_sd>;
};
&spi1 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
spiflash: w25q32dw@0 {
u-boot,dm-pre-reloc;
norflash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <49500000>;
spi-cpol;
spi-cpha;
spi-max-frequency = <50000000>;
};
};
&spi5 {
&tcphy1 {
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>;
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy1 {
status = "okay";
u2phy1_otg: otg-port {
status = "okay";
};
u2phy1_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};

6
arch/arm/dts/rk3399-roc-pc-mezzanine-u-boot.dtsi Normal file
View File

@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2020 Amarula Solutions(India)
*/
#include "rk3399-roc-pc-u-boot.dtsi"

93
arch/arm/dts/rk3399-roc-pc-mezzanine.dts Normal file
View File

@ -0,0 +1,93 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
* Copyright (c) 2019 Markus Reichl <m.reichl@fivetechno.de>
*/
/dts-v1/;
#include "rk3399-roc-pc.dtsi"
/ {
model = "Firefly ROC-RK3399-PC Mezzanine Board";
compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
vcc3v3_ngff: vcc3v3-ngff {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_ngff";
enable-active-high;
gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_ngff_en>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
};
vcc3v3_pcie: vcc3v3-pcie {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
enable-active-high;
gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc3v3_pcie_en>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
};
};
&pcie_phy {
status = "okay";
};
&pcie0 {
ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_perst>;
vpcie3v3-supply = <&vcc3v3_pcie>;
vpcie1v8-supply = <&vcc1v8_pmu>;
vpcie0v9-supply = <&vcca_0v9>;
status = "okay";
};
&pinctrl {
ngff {
vcc3v3_ngff_en: vcc3v3-ngff-en {
rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
vcc3v3_pcie_en: vcc3v3-pcie-en {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_perst: pcie-perst {
rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdio0 {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_ngff>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
};

36
arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
View File

@ -14,9 +14,45 @@
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
vcc_hub_en: vcc_hub_en-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&hub_rst>;
regulator-name = "vcc_hub_en";
regulator-always-on;
};
};
/*
* should be placed inside mp8859, but not until mp8859 has
* its own dt-binding.
*/
&dc_12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
vin-supply = <&vcc_vbus_typec0>;
};
&vdd_log {
regulator-min-microvolt = <430000>;
regulator-init-microvolt = <950000>;
};
&vcc5v0_host {
regulator-always-on;
};
&vcc_sys {
regulator-always-on;
};
&vcc_sdio {
regulator-always-on;
};

3
arch/arm/dts/rk3399-roc-pc.dts
View File

@ -8,6 +8,5 @@
/ {
model = "Firefly ROC-RK3399-PC Board";
compatible = "libretech,roc-rk3399-pc", "firefly,roc-rk3399-pc",
"rockchip,rk3399";
compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
};

35
arch/arm/dts/rk3399-roc-pc.dtsi
View File

@ -110,20 +110,6 @@
regulator-max-microvolt = <5000000>;
};
/*
* should be placed inside mp8859, but not until mp8859 has
* its own dt-binding.
*/
dc_12v: mp8859-dcdc1 {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
vin-supply = <&vcc_vbus_typec0>;
};
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
@ -176,7 +162,6 @@
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en &hub_rst>;
regulator-name = "vcc5v0_host";
regulator-always-on;
vin-supply = <&vcc_sys>;
};
@ -198,7 +183,6 @@
pinctrl-names = "default";
pinctrl-0 = <&vcc_sys_en>;
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@ -392,7 +376,6 @@
vcc_sdio: LDO_REG4 {
regulator-name = "vcc_sdio";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
@ -549,6 +532,24 @@
vbus-supply = <&vcc_vbus_typec0>;
status = "okay";
};
mp8859: regulator@66 {
compatible = "mps,mp8859";
reg = <0x66>;
dc_12v: mp8859_dcdc {
regulator-name = "dc_12v";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_vbus_typec0>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <12000000>;
};
};
};
};
&i2s0 {

129
arch/arm/dts/rk3399-rock-pi-4.dts
View File

@ -25,6 +25,15 @@
#clock-cells = <0>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
vcc12v_dcin: dc-12v {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@ -44,6 +53,16 @@
vin-supply = <&vcc12v_dcin>;
};
vcc_0v9: vcc-0v9 {
compatible = "regulator-fixed";
regulator-name = "vcc_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vcc3v3_sys>;
};
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
@ -157,12 +176,22 @@
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
@ -444,13 +473,60 @@
pmu1830-supply = <&vcc_3v0>;
};
&pcie_phy {
status = "okay";
};
&pcie0 {
ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
max-link-speed = <2>;
num-lanes = <4>;
pinctrl-0 = <&pcie_clkreqnb_cpm>;
pinctrl-names = "default";
vpcie0v9-supply = <&vcc_0v9>;
vpcie1v8-supply = <&vcc_1v8>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_l: bt-wake-l {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio0 {
sdio0_bus4: sdio0-bus4 {
rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>,
<2 RK_PC5 1 &pcfg_pull_up_20ma>,
<2 RK_PC6 1 &pcfg_pull_up_20ma>,
<2 RK_PC7 1 &pcfg_pull_up_20ma>;
};
sdio0_cmd: sdio0-cmd {
rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up_20ma>;
};
sdio0_clk: sdio0-clk {
rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none_20ma>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
@ -476,6 +552,16 @@
rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
wifi_host_wake_l: wifi-host-wake-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm2 {
@ -488,6 +574,32 @@
vref-supply = <&vcc_1v8>;
};
&sdio0 {
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
clock-frequency = <50000000>;
cap-sdio-irq;
cap-sd-highspeed;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
@ -551,6 +663,23 @@
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
clock-names = "ext_clock";
device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
};
};
&uart2 {
status = "okay";
};

49
arch/arm/dts/rk3399-rock960.dts
View File

@ -114,6 +114,55 @@
};
};
&spi0 {
/* On Low speed expansion (LS-SPI0) */
status = "okay";
};
&spi4 {
/* On High speed expansion (HS-SPI1) */
status = "okay";
};
&thermal_zones {
cpu_thermal: cpu {
polling-delay-passive = <100>;
polling-delay = <1000>;
thermal-sensors = <&tsadc 0>;
sustainable-power = <1550>;
trips {
cpu_alert0: cpu_alert0 {
temperature = <65000>;
hysteresis = <2000>;
type = "passive";
};
cpu_alert1: cpu_alert1 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu_crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert1>;
cooling-device =
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
&usbdrd_dwc3_0 {
dr_mode = "otg";
};

13
arch/arm/dts/rk3399-rock960.dtsi
View File

@ -76,6 +76,15 @@
regulator-always-on;
vin-supply = <&vcc5v0_sys>;
};
vcc_0v9: vcc-0v9 {
compatible = "regulator-fixed";
regulator-name = "vcc_0v9";
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vcc3v3_sys>;
};
};
&cpu_l0 {
@ -384,6 +393,8 @@
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>;
vpcie0v9-supply = <&vcc_0v9>;
vpcie1v8-supply = <&vcca_1v8>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
@ -531,7 +542,7 @@
cap-mmc-highspeed;
cap-sd-highspeed;
clock-frequency = <100000000>;
clock-freq-min-max = <100000 100000000>;
max-frequency = <100000000>;
cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
disable-wp;
sd-uhs-sdr104;

751
arch/arm/dts/rk3399-rockpro64.dts
View File

@ -2,752 +2,29 @@
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
* Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
* Copyright (c) 2019 Katsuhiro Suzuki <katsuhiro@katsuster.net>
*/
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
#include "rk3399-rockpro64.dtsi"
/ {
model = "Pine64 RockPro64";
compatible = "pine64,rockpro64", "rockchip,rk3399";
chosen {
stdout-path = "serial2:1500000n8";
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
linux,code = <KEY_POWER>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
work-led {
label = "work";
default-state = "on";
gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
};
diy-led {
label = "diy";
default-state = "off";
gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
};
};
fan: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
fan-supply = <&vcc12v_dcin>;
pwms = <&pwm1 0 50000 0>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8>;
};
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_pwr_en>;
regulator-name = "vcc3v3_pcie";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc12v_dcin>;
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
regulator-always-on;
vin-supply = <&vcc5v0_usb>;
};
vcc5v0_typec: vcc5v0-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec_en>;
regulator-name = "vcc5v0_typec";
regulator-always-on;
vin-supply = <&vcc5v0_usb>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb: vcc5v0-usb {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1700000>;
vin-supply = <&vcc5v0_sys>;
};
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&emmc_phy {
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
i2c-scl-falling-time-ns = <4>;
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio3>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc5v0_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcca_1v8>;
regulators {
vdd_center: DCDC_REG1 {
regulator-name = "vdd_center";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-name = "vdd_cpu_l";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc1v8_dvp: LDO_REG1 {
regulator-name = "vcc1v8_dvp";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v0_touch: LDO_REG2 {
regulator-name = "vcc3v0_touch";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca_1v8: LDO_REG3 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_sdio: LDO_REG4 {
regulator-name = "vcc_sdio";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcca3v0_codec: LDO_REG5 {
regulator-name = "vcca3v0_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v5: LDO_REG6 {
regulator-name = "vcc_1v5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcca1v8_codec: LDO_REG7 {
regulator-name = "vcca1v8_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v0: LDO_REG8 {
regulator-name = "vcc_3v0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc3v3_s3: vcc_lan: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&vsel1_gpio>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&vsel2_gpio>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
model = "Pine64 RockPro64 v2.1";
compatible = "pine64,rockpro64-v2.1", "pine64,rockpro64", "rockchip,rk3399";
};
&i2c1 {
i2c-scl-rising-time-ns = <300>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
es8316: codec@11 {
compatible = "everest,es8316";
reg = <0x11>;
clocks = <&cru SCLK_I2S_8CH_OUT>;
clock-names = "mclk";
#sound-dai-cells = <0>;
&i2c3 {
i2c-scl-rising-time-ns = <450>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&i2c4 {
i2c-scl-rising-time-ns = <600>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
fusb0: typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&fusb0_int>;
vbus-supply = <&vcc5v0_typec>;
status = "okay";
};
};
&i2s0 {
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
status = "okay";
};
&i2s1 {
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "okay";
};
&i2s2 {
status = "okay";
};
&io_domains {
status = "okay";
bt656-supply = <&vcc1v8_dvp>;
audio-supply = <&vcc_3v0>;
sdmmc-supply = <&vcc_sdio>;
gpio1830-supply = <&vcc_3v0>;
};
&pcie0 {
ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_perst>;
vpcie12v-supply = <&vcc12v_dcin>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pmu_io_domains {
pmu1830-supply = <&vcc_3v0>;
status = "okay";
};
&pinctrl {
buttons {
pwrbtn: pwrbtn {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
fusb302x {
fusb0_int: fusb0-int {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
work_led_gpio: work_led-gpio {
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
diy_led_gpio: diy_led-gpio {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_perst: pcie-perst {
rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
vsel1_gpio: vsel1-gpio {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_gpio: vsel2-gpio {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb-typec {
vcc5v0_typec_en: vcc5v0_typec_en {
rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
port {
es8316_p0_0: endpoint {
remote-endpoint = <&i2s1_p0_0>;
};
};
};
};
&pwm0 {
status = "okay";
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&saradc {
vref-supply = <&vcca1v8_s3>;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
status = "okay";
};
&spi1 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
};
};
&tcphy0 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
/* tshut polarity 0:LOW 1:HIGH */
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy0 {
status = "okay";
u2phy0_otg: otg-port {
status = "okay";
};
u2phy0_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&u2phy1 {
status = "okay";
u2phy1_otg: otg-port {
status = "okay";
};
u2phy1_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "otg";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

797
arch/arm/dts/rk3399-rockpro64.dtsi Normal file
View File

@ -0,0 +1,797 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
* Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
*/
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
/ {
chosen {
stdout-path = "serial2:1500000n8";
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
linux,code = <KEY_POWER>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
work-led {
label = "work";
default-state = "on";
gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
};
diy-led {
label = "diy";
default-state = "off";
gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
};
};
fan: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
fan-supply = <&vcc12v_dcin>;
pwms = <&pwm1 0 50000 0>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
sound {
compatible = "audio-graph-card";
label = "rockchip,rk3399";
dais = <&i2s1_p0>;
};
vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8>;
};
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_pwr_en>;
regulator-name = "vcc3v3_pcie";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc12v_dcin>;
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
regulator-always-on;
vin-supply = <&vcc5v0_usb>;
};
vcc5v0_typec: vcc5v0-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec_en>;
regulator-name = "vcc5v0_typec";
regulator-always-on;
vin-supply = <&vcc5v0_usb>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb: vcc5v0-usb {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1700000>;
vin-supply = <&vcc5v0_sys>;
};
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&emmc_phy {
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
i2c-scl-falling-time-ns = <4>;
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio3>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc6-supply = <&vcc5v0_sys>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
vcc10-supply = <&vcc5v0_sys>;
vcc11-supply = <&vcc5v0_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcca_1v8>;
regulators {
vdd_center: DCDC_REG1 {
regulator-name = "vdd_center";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-name = "vdd_cpu_l";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc1v8_dvp: LDO_REG1 {
regulator-name = "vcc1v8_dvp";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v0_touch: LDO_REG2 {
regulator-name = "vcc3v0_touch";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca_1v8: LDO_REG3 {
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_sdio: LDO_REG4 {
regulator-name = "vcc_sdio";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcca3v0_codec: LDO_REG5 {
regulator-name = "vcca3v0_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v5: LDO_REG6 {
regulator-name = "vcc_1v5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcca1v8_codec: LDO_REG7 {
regulator-name = "vcca1v8_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v0: LDO_REG8 {
regulator-name = "vcc_3v0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc3v3_s3: vcc_lan: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&vsel1_gpio>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&vsel2_gpio>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c1 {
i2c-scl-rising-time-ns = <300>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&i2c3 {
i2c-scl-rising-time-ns = <450>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&i2c4 {
i2c-scl-rising-time-ns = <600>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
fusb0: typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&fusb0_int>;
vbus-supply = <&vcc5v0_typec>;
status = "okay";
};
};
&i2s0 {
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
status = "okay";
};
&i2s1 {
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "okay";
i2s1_p0: port {
i2s1_p0_0: endpoint {
dai-format = "i2s";
mclk-fs = <256>;
remote-endpoint = <&es8316_p0_0>;
};
};
};
&i2s2 {
status = "okay";
};
&io_domains {
status = "okay";
bt656-supply = <&vcc1v8_dvp>;
audio-supply = <&vcc_3v0>;
sdmmc-supply = <&vcc_sdio>;
gpio1830-supply = <&vcc_3v0>;
};
&pcie0 {
ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_perst>;
vpcie12v-supply = <&vcc12v_dcin>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pmu_io_domains {
pmu1830-supply = <&vcc_3v0>;
status = "okay";
};
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
};
bt_wake_l: bt-wake-l {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
buttons {
pwrbtn: pwrbtn {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
fusb302x {
fusb0_int: fusb0-int {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
work_led_gpio: work_led-gpio {
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
diy_led_gpio: diy_led-gpio {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_perst: pcie-perst {
rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
vsel1_gpio: vsel1-gpio {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_gpio: vsel2-gpio {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb-typec {
vcc5v0_typec_en: vcc5v0_typec_en {
rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {
status = "okay";
};
&pwm1 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&saradc {
vref-supply = <&vcca1v8_s3>;
status = "okay";
};
&sdio0 {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
disable-wp;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
status = "okay";
};
&spi1 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
};
};
&tcphy0 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
/* tshut polarity 0:LOW 1:HIGH */
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy0 {
status = "okay";
u2phy0_otg: otg-port {
status = "okay";
};
u2phy0_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&u2phy1 {
status = "okay";
u2phy1_otg: otg-port {
status = "okay";
};
u2phy1_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
vbat-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8>;
};
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "otg";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

7
arch/arm/dts/rk3399-u-boot.dtsi
View File

@ -25,6 +25,12 @@
clock-names = "pclk_ddr_mon";
};
rng: rng@ff8b8000 {
compatible = "rockchip,cryptov1-rng";
reg = <0x0 0xff8b8000 0x0 0x1000>;
status = "disabled";
};
dmc: dmc {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-dmc";
@ -79,6 +85,7 @@
};
&sdhci {
max-frequency = <200000000>;
u-boot,dm-pre-reloc;
};

583
arch/arm/dts/rk3399.dtsi
View File

File diff suppressed because it is too large Load Diff

2
board/firefly/roc-pc-rk3399/MAINTAINERS
View File

@ -1,6 +1,8 @@
ROC-RK3399-PC
M: Levin Du <djw@t-chip.com.cn>
M: Suniel Mahesh <sunil@amarulasolutions.com>
S: Maintained
F: board/firefly/roc-pc-rk3399
F: include/configs/roc-pc-rk3399.h
F: configs/roc-pc-rk3399_defconfig
F: configs/roc-pc-mezzanine-rk3399_defconfig

16
board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
View File

@ -10,7 +10,6 @@
#include <spl_gpio.h>
#include <asm/io.h>
#include <asm/arch-rockchip/gpio.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#ifndef CONFIG_SPL_BUILD
int board_early_init_f(void)
@ -34,26 +33,13 @@ out:
#if defined(CONFIG_TPL_BUILD)
#define PMUGRF_BASE 0xff320000
#define GPIO0_BASE 0xff720000
int board_early_init_f(void)
{
struct rockchip_gpio_regs * const gpio0 = (void *)GPIO0_BASE;
struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
/**
* 1. Glow yellow LED, termed as low power
* 2. Poll for on board power key press
* 3. Once 2 done, off yellow and glow red LED, termed as full power
* 4. Continue booting...
*/
spl_gpio_output(gpio0, GPIO(BANK_A, 2), 1);
spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_A, 5), GPIO_PULL_NORMAL);
while (readl(&gpio0->ext_port) & 0x20);
spl_gpio_output(gpio0, GPIO(BANK_A, 2), 0);
/* Turn on red LED, indicating full power mode */
spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1);
return 0;

7
board/rockchip/evb_rk3328/MAINTAINERS
View File

@ -5,6 +5,13 @@ F: board/rockchip/evb_rk3328
F: include/configs/evb_rk3328.h
F: configs/evb-rk3328_defconfig
ROC-RK3328-CC
M: Loic Devulder <ldevulder@suse.com>
M: Chen-Yu Tsai <wens@csie.org>
S: Maintained
F: configs/roc-cc-rk3328_defconfig
F: arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
ROCK64-RK3328
M: Matwey V. Kornilov <matwey.kornilov@gmail.com>
S: Maintained

7
board/rockchip/evb_rk3399/MAINTAINERS
View File

@ -42,6 +42,13 @@ S: Maintained
F: configs/nanopi-m4-rk3399_defconfig
F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
NANOPI-M4-2GB
M: Jagan Teki <jagan@amarulasolutions.com>
M: Deepak Das <deepakdas.linux@gmail.com>
S: Maintained
F: configs/nanopi-m4-2gb-rk3399_defconfig
F: arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi
NANOPI-NEO4
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained

2
configs/evb-px30_defconfig
View File

@ -85,6 +85,8 @@ CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_ROCKCHIP_SDRAM_COMMON=y
CONFIG_DM_RESET=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y
# CONFIG_SPECIFY_CONSOLE_INDEX is not set
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_SKIP_INIT=y

1
configs/evb-rk3328_defconfig
View File

@ -61,7 +61,6 @@ CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y

2
configs/evb-rk3399_defconfig
View File

@ -39,6 +39,8 @@ CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_DM_RNG=y
CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y

63
configs/nanopi-m4-2gb-rk3399_defconfig Normal file
View File

@ -0,0 +1,63 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4-2gb"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_KEYBOARD=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_BPP16=y
CONFIG_VIDEO_BPP32=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y

102
configs/roc-cc-rk3328_defconfig Normal file
View File

@ -0,0 +1,102 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3328=y
CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SMBIOS_PRODUCT_NAME="roc-rk3328-cc"
CONFIG_DEBUG_UART=y
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc"
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_TPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_FASTBOOT_BUF_ADDR=0x800800
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_DM_RESET=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYSRESET=y
# CONFIG_TPL_SYSRESET is not set
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_SMBIOS_MANUFACTURER="firefly"

67
configs/roc-pc-mezzanine-rk3399_defconfig Normal file
View File

@ -0,0 +1,67 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_ROC_PC_RK3399=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
CONFIG_TPL_GPIO_SUPPORT=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc-mezzanine"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM_RK3399_LPDDR4=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_KEYBOARD=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_BPP16=y
CONFIG_VIDEO_BPP32=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_DISPLAY_ROCKCHIP_HDMI=y

1
configs/rock64-rk3328_defconfig
View File

@ -60,7 +60,6 @@ CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y

4
doc/README.rockchip
View File

@ -52,10 +52,12 @@ Two RK3308 boards are supported:
- EVB RK3308 - use evb-rk3308 configuration
- ROC-CC-RK3308 - use roc-cc-rk3308 configuration
Two RK3328 board are supported:
Three RK3328 boards are supported:
- EVB RK3328 - use evb-rk3328_defconfig
- Pine64 Rock64 board - use rock64-rk3328_defconfig
- Firefly / Libre Computer Project ROC-RK3328-CC board -
use roc-cc-rk3328_defconfig
Size RK3399 boards are supported (aarch64):

1
drivers/clk/rockchip/clk_rk3399.c
View File

@ -996,6 +996,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
break;
case ACLK_VOP1:
case HCLK_VOP1:
case HCLK_SD:
/**
* assigned-clocks handling won't require for vopl, so
* return 0 to satisfy clk_set_defaults during device probe.

8
drivers/rng/Kconfig
View File

@ -31,4 +31,12 @@ config RNG_STM32MP1
help
Enable STM32MP1 rng driver.
config RNG_ROCKCHIP
bool "Enable random number generator for rockchip crypto rng"
depends on ARCH_ROCKCHIP && DM_RNG
default n
help
Enable random number generator for rockchip.This driver is
support rng module of crypto v1 and crypto v2.
endif

1
drivers/rng/Makefile
View File

@ -7,3 +7,4 @@ obj-$(CONFIG_DM_RNG) += rng-uclass.o
obj-$(CONFIG_RNG_MESON) += meson-rng.o
obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o

224
drivers/rng/rockchip_rng.c Normal file
View File

@ -0,0 +1,224 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
*/
#include <asm/arch-rockchip/hardware.h>
#include <asm/io.h>
#include <common.h>
#include <dm.h>
#include <linux/iopoll.h>
#include <linux/string.h>
#include <rng.h>
#define RK_HW_RNG_MAX 32
#define _SBF(s, v) ((v) << (s))
/* start of CRYPTO V1 register define */
#define CRYPTO_V1_CTRL 0x0008
#define CRYPTO_V1_RNG_START BIT(8)
#define CRYPTO_V1_RNG_FLUSH BIT(9)
#define CRYPTO_V1_TRNG_CTRL 0x0200
#define CRYPTO_V1_OSC_ENABLE BIT(16)
#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x)
#define CRYPTO_V1_TRNG_DOUT_0 0x0204
/* end of CRYPTO V1 register define */
/* start of CRYPTO V2 register define */
#define CRYPTO_V2_RNG_CTL 0x0400
#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00)
#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01)
#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02)
#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03)
#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00)
#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01)
#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02)
#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03)
#define CRYPTO_V2_RNG_ENABLE BIT(1)
#define CRYPTO_V2_RNG_START BIT(0)
#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404
#define CRYPTO_V2_RNG_DOUT_0 0x0410
/* end of CRYPTO V2 register define */
#define RK_RNG_TIME_OUT 50000 /* max 50ms */
struct rk_rng_soc_data {
int (*rk_rng_read)(struct udevice *dev, void *data, size_t len);
};
struct rk_rng_platdata {
fdt_addr_t base;
struct rk_rng_soc_data *soc_data;
};
static int rk_rng_read_regs(fdt_addr_t addr, void *buf, size_t size)
{
u32 count = RK_HW_RNG_MAX / sizeof(u32);
u32 reg, tmp_len;
if (size > RK_HW_RNG_MAX)
return -EINVAL;
while (size && count) {
reg = readl(addr);
tmp_len = min(size, sizeof(u32));
memcpy(buf, &reg, tmp_len);
addr += sizeof(u32);
buf += tmp_len;
size -= tmp_len;
count--;
}
return 0;
}
static int rk_v1_rng_read(struct udevice *dev, void *data, size_t len)
{
struct rk_rng_platdata *pdata = dev_get_priv(dev);
u32 reg = 0;
int retval;
if (len > RK_HW_RNG_MAX)
return -EINVAL;
/* enable osc_ring to get entropy, sample period is set as 100 */
writel(CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100),
pdata->base + CRYPTO_V1_TRNG_CTRL);
rk_clrsetreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START,
CRYPTO_V1_RNG_START);
retval = readl_poll_timeout(pdata->base + CRYPTO_V1_CTRL, reg,
!(reg & CRYPTO_V1_RNG_START),
RK_RNG_TIME_OUT);
if (retval)
goto exit;
rk_rng_read_regs(pdata->base + CRYPTO_V1_TRNG_DOUT_0, data, len);
exit:
/* close TRNG */
rk_clrreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START);
return 0;
}
static int rk_v2_rng_read(struct udevice *dev, void *data, size_t len)
{
struct rk_rng_platdata *pdata = dev_get_priv(dev);
u32 reg = 0;
int retval;
if (len > RK_HW_RNG_MAX)
return -EINVAL;
/* enable osc_ring to get entropy, sample period is set as 100 */
writel(100, pdata->base + CRYPTO_V2_RNG_SAMPLE_CNT);
reg |= CRYPTO_V2_RNG_256_BIT_LEN;
reg |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
reg |= CRYPTO_V2_RNG_ENABLE;
reg |= CRYPTO_V2_RNG_START;
rk_clrsetreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff, reg);
retval = readl_poll_timeout(pdata->base + CRYPTO_V2_RNG_CTL, reg,
!(reg & CRYPTO_V2_RNG_START),
RK_RNG_TIME_OUT);
if (retval)
goto exit;
rk_rng_read_regs(pdata->base + CRYPTO_V2_RNG_DOUT_0, data, len);
exit:
/* close TRNG */
rk_clrreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff);
return retval;
}
static int rockchip_rng_read(struct udevice *dev, void *data, size_t len)
{
unsigned char *buf = data;
unsigned int i;
int ret = -EIO;
struct rk_rng_platdata *pdata = dev_get_priv(dev);
if (!len)
return 0;
if (!pdata->soc_data || !pdata->soc_data->rk_rng_read)
return -EINVAL;
for (i = 0; i < len / RK_HW_RNG_MAX; i++, buf += RK_HW_RNG_MAX) {
ret = pdata->soc_data->rk_rng_read(dev, buf, RK_HW_RNG_MAX);
if (ret)
goto exit;
}
if (len % RK_HW_RNG_MAX)
ret = pdata->soc_data->rk_rng_read(dev, buf,
len % RK_HW_RNG_MAX);
exit:
return ret;
}
static int rockchip_rng_ofdata_to_platdata(struct udevice *dev)
{
struct rk_rng_platdata *pdata = dev_get_priv(dev);
memset(pdata, 0x00, sizeof(*pdata));
pdata->base = (fdt_addr_t)dev_read_addr_ptr(dev);
if (!pdata->base)
return -ENOMEM;
return 0;
}
static int rockchip_rng_probe(struct udevice *dev)
{
struct rk_rng_platdata *pdata = dev_get_priv(dev);
pdata->soc_data = (struct rk_rng_soc_data *)dev_get_driver_data(dev);
return 0;
}
static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
.rk_rng_read = rk_v1_rng_read,
};
static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
.rk_rng_read = rk_v2_rng_read,
};
static const struct dm_rng_ops rockchip_rng_ops = {
.read = rockchip_rng_read,
};
static const struct udevice_id rockchip_rng_match[] = {
{
.compatible = "rockchip,cryptov1-rng",
.data = (ulong)&rk_rng_v1_soc_data,
},
{
.compatible = "rockchip,cryptov2-rng",
.data = (ulong)&rk_rng_v2_soc_data,
},
{},
};
U_BOOT_DRIVER(rockchip_rng) = {
.name = "rockchip-rng",
.id = UCLASS_RNG,
.of_match = rockchip_rng_match,
.ops = &rockchip_rng_ops,
.probe = rockchip_rng_probe,
.ofdata_to_platdata = rockchip_rng_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct rk_rng_platdata),
};

1
drivers/video/rockchip/rk3288_mipi.c
View File

@ -8,7 +8,6 @@
#include <clk.h>
#include <display.h>
#include <dm.h>
#include <fdtdec.h>
#include <panel.h>
#include <regmap.h>
#include "rk_mipi.h"

1
drivers/video/rockchip/rk3399_mipi.c
View File

@ -8,7 +8,6 @@
#include <clk.h>
#include <display.h>
#include <dm.h>
#include <fdtdec.h>
#include <panel.h>
#include <regmap.h>
#include "rk_mipi.h"

2
drivers/video/rockchip/rk_edp.c
View File

@ -997,7 +997,7 @@ static int rk_edp_ofdata_to_platdata(struct udevice *dev)
{
struct rk_edp_priv *priv = dev_get_priv(dev);
priv->regs = (struct rk3288_edp *)devfdt_get_addr(dev);
priv->regs = dev_read_addr_ptr(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
return 0;

13
drivers/video/rockchip/rk_lvds.c
View File

@ -161,8 +161,7 @@ int rk_lvds_enable(struct udevice *dev, int panel_bpp,
int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing)
{
if (fdtdec_decode_display_timing
(gd->fdt_blob, dev_of_offset(dev), 0, timing)) {
if (ofnode_decode_display_timing(dev_ofnode(dev), 0, timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
}
@ -173,13 +172,11 @@ int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing)
static int rk_lvds_ofdata_to_platdata(struct udevice *dev)
{
struct rk_lvds_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
int ret;
priv->regs = (void *)devfdt_get_addr(dev);
priv->regs = dev_read_addr_ptr(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
ret = fdtdec_get_int(blob, node, "rockchip,output", -1);
ret = dev_read_s32_default(dev, "rockchip,output", -1);
if (ret != -1) {
priv->output = ret;
debug("LVDS output : %d\n", ret);
@ -188,7 +185,7 @@ static int rk_lvds_ofdata_to_platdata(struct udevice *dev)
priv->output = LVDS_OUTPUT_RGB;
}
ret = fdtdec_get_int(blob, node, "rockchip,data-mapping", -1);
ret = dev_read_s32_default(dev, "rockchip,data-mapping", -1);
if (ret != -1) {
priv->format = ret;
debug("LVDS data-mapping : %d\n", ret);
@ -197,7 +194,7 @@ static int rk_lvds_ofdata_to_platdata(struct udevice *dev)
priv->format = LVDS_FORMAT_JEIDA;
}
ret = fdtdec_get_int(blob, node, "rockchip,data-width", -1);
ret = dev_read_s32_default(dev, "rockchip,data-width", -1);
if (ret != -1) {
debug("LVDS data-width : %d\n", ret);
if (ret == 24) {

14
drivers/video/rockchip/rk_mipi.c
View File

@ -8,7 +8,6 @@
#include <clk.h>
#include <display.h>
#include <dm.h>
#include <fdtdec.h>
#include <panel.h>
#include <regmap.h>
#include "rk_mipi.h"
@ -29,8 +28,7 @@ int rk_mipi_read_timing(struct udevice *dev,
{
int ret;
ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
0, timing);
ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, timing);
if (ret) {
debug("%s: Failed to decode display timing (ret=%d)\n",
__func__, ret);
@ -77,7 +75,7 @@ static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val)
int rk_mipi_dsi_enable(struct udevice *dev,
const struct display_timing *timing)
{
int node, timing_node;
ofnode node, timing_node;
int val;
struct rk_mipi_priv *priv = dev_get_priv(dev);
uintptr_t regs = priv->regs;
@ -120,10 +118,10 @@ int rk_mipi_dsi_enable(struct udevice *dev,
rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0);
/* Set dpi color coding depth 24 bit */
timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev),
"display-timings");
node = fdt_first_subnode(gd->fdt_blob, timing_node);
val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1);
timing_node = ofnode_find_subnode(dev->node, "display-timings");
node = ofnode_first_subnode(timing_node);
val = ofnode_read_u32_default(node, "bits-per-pixel", -1);
switch (val) {
case 16:
rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1);

212
include/dt-bindings/clock/rk3328-cru.h
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
* Author: Elaine <zhangqing@rock-chips.com>
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
@ -90,119 +91,118 @@
#define SCLK_MAC2IO_EXT 102
/* dclk gates */
#define DCLK_LCDC 180
#define DCLK_HDMIPHY 181
#define HDMIPHY 182
#define USB480M 183
#define DCLK_LCDC_SRC 184
#define DCLK_LCDC 120
#define DCLK_HDMIPHY 121
#define HDMIPHY 122
#define USB480M 123
#define DCLK_LCDC_SRC 124
/* aclk gates */
#define ACLK_AXISRAM 190
#define ACLK_VOP_PRE 191
#define ACLK_USB3OTG 192
#define ACLK_RGA_PRE 193
#define ACLK_DMAC 194
#define ACLK_GPU 195
#define ACLK_BUS_PRE 196
#define ACLK_PERI_PRE 197
#define ACLK_RKVDEC_PRE 198
#define ACLK_RKVDEC 199
#define ACLK_RKVENC 200
#define ACLK_VPU_PRE 201
#define ACLK_VIO_PRE 202
#define ACLK_VPU 203
#define ACLK_VIO 204
#define ACLK_VOP 205
#define ACLK_GMAC 206
#define ACLK_H265 207
#define ACLK_H264 208
#define ACLK_MAC2PHY 209
#define ACLK_MAC2IO 210
#define ACLK_DCF 211
#define ACLK_TSP 212
#define ACLK_PERI 213
#define ACLK_RGA 214
#define ACLK_IEP 215
#define ACLK_CIF 216
#define ACLK_HDCP 217
#define ACLK_AXISRAM 130
#define ACLK_VOP_PRE 131
#define ACLK_USB3OTG 132
#define ACLK_RGA_PRE 133
#define ACLK_DMAC 134
#define ACLK_GPU 135
#define ACLK_BUS_PRE 136
#define ACLK_PERI_PRE 137
#define ACLK_RKVDEC_PRE 138
#define ACLK_RKVDEC 139
#define ACLK_RKVENC 140
#define ACLK_VPU_PRE 141
#define ACLK_VIO_PRE 142
#define ACLK_VPU 143
#define ACLK_VIO 144
#define ACLK_VOP 145
#define ACLK_GMAC 146
#define ACLK_H265 147
#define ACLK_H264 148
#define ACLK_MAC2PHY 149
#define ACLK_MAC2IO 150
#define ACLK_DCF 151
#define ACLK_TSP 152
#define ACLK_PERI 153
#define ACLK_RGA 154
#define ACLK_IEP 155
#define ACLK_CIF 156
#define ACLK_HDCP 157
/* pclk gates */
#define PCLK_GPIO0 300
#define PCLK_GPIO1 301
#define PCLK_GPIO2 302
#define PCLK_GPIO3 303
#define PCLK_GRF 304
#define PCLK_I2C0 305
#define PCLK_I2C1 306
#define PCLK_I2C2 307
#define PCLK_I2C3 308
#define PCLK_SPI 309
#define PCLK_UART0 310
#define PCLK_UART1 311
#define PCLK_UART2 312
#define PCLK_TSADC 313
#define PCLK_PWM 314
#define PCLK_TIMER 315
#define PCLK_BUS_PRE 316
#define PCLK_PERI_PRE 317
#define PCLK_HDMI_CTRL 318
#define PCLK_HDMI_PHY 319
#define PCLK_GMAC 320
#define PCLK_H265 321
#define PCLK_MAC2PHY 322
#define PCLK_MAC2IO 323
#define PCLK_USB3PHY_OTG 324
#define PCLK_USB3PHY_PIPE 325
#define PCLK_USB3_GRF 326
#define PCLK_USB2_GRF 327
#define PCLK_HDMIPHY 328
#define PCLK_DDR 329
#define PCLK_PERI 330
#define PCLK_HDMI 331
#define PCLK_HDCP 332
#define PCLK_DCF 333
#define PCLK_SARADC 334
#define PCLK_GPIO0 200
#define PCLK_GPIO1 201
#define PCLK_GPIO2 202
#define PCLK_GPIO3 203
#define PCLK_GRF 204
#define PCLK_I2C0 205
#define PCLK_I2C1 206
#define PCLK_I2C2 207
#define PCLK_I2C3 208
#define PCLK_SPI 209
#define PCLK_UART0 210
#define PCLK_UART1 211
#define PCLK_UART2 212
#define PCLK_TSADC 213
#define PCLK_PWM 214
#define PCLK_TIMER 215
#define PCLK_BUS_PRE 216
#define PCLK_PERI_PRE 217
#define PCLK_HDMI_CTRL 218
#define PCLK_HDMI_PHY 219
#define PCLK_GMAC 220
#define PCLK_H265 221
#define PCLK_MAC2PHY 222
#define PCLK_MAC2IO 223
#define PCLK_USB3PHY_OTG 224
#define PCLK_USB3PHY_PIPE 225
#define PCLK_USB3_GRF 226
#define PCLK_USB2_GRF 227
#define PCLK_HDMIPHY 228
#define PCLK_DDR 229
#define PCLK_PERI 230
#define PCLK_HDMI 231
#define PCLK_HDCP 232
#define PCLK_DCF 233
#define PCLK_SARADC 234
#define PCLK_ACODECPHY 235
#define PCLK_WDT 236
/* hclk gates */
#define HCLK_PERI 408
#define HCLK_TSP 409
#define HCLK_GMAC 410
#define HCLK_I2S0_8CH 411
#define HCLK_I2S1_8CH 413
#define HCLK_I2S2_2CH 413
#define HCLK_SPDIF_8CH 414
#define HCLK_VOP 415
#define HCLK_NANDC 416
#define HCLK_SDMMC 417
#define HCLK_SDIO 418
#define HCLK_EMMC 419
#define HCLK_SDMMC_EXT 420
#define HCLK_RKVDEC_PRE 421
#define HCLK_RKVDEC 422
#define HCLK_RKVENC 423
#define HCLK_VPU_PRE 424
#define HCLK_VIO_PRE 425
#define HCLK_VPU 426
#define HCLK_VIO 427
#define HCLK_BUS_PRE 428
#define HCLK_PERI_PRE 429
#define HCLK_H264 430
#define HCLK_CIF 431
#define HCLK_OTG_PMU 432
#define HCLK_OTG 433
#define HCLK_HOST0 434
#define HCLK_HOST0_ARB 435
#define HCLK_CRYPTO_MST 436
#define HCLK_CRYPTO_SLV 437
#define HCLK_PDM 438
#define HCLK_IEP 439
#define HCLK_RGA 440
#define HCLK_HDCP 441
#define HCLK_PERI 308
#define HCLK_TSP 309
#define HCLK_GMAC 310
#define HCLK_I2S0_8CH 311
#define HCLK_I2S1_8CH 312
#define HCLK_I2S2_2CH 313
#define HCLK_SPDIF_8CH 314
#define HCLK_VOP 315
#define HCLK_NANDC 316
#define HCLK_SDMMC 317
#define HCLK_SDIO 318
#define HCLK_EMMC 319
#define HCLK_SDMMC_EXT 320
#define HCLK_RKVDEC_PRE 321
#define HCLK_RKVDEC 322
#define HCLK_RKVENC 323
#define HCLK_VPU_PRE 324
#define HCLK_VIO_PRE 325
#define HCLK_VPU 326
#define HCLK_BUS_PRE 328
#define HCLK_PERI_PRE 329
#define HCLK_H264 330
#define HCLK_CIF 331
#define HCLK_OTG_PMU 332
#define HCLK_OTG 333
#define HCLK_HOST0 334
#define HCLK_HOST0_ARB 335
#define HCLK_CRYPTO_MST 336
#define HCLK_CRYPTO_SLV 337
#define HCLK_PDM 338
#define HCLK_IEP 339
#define HCLK_RGA 340
#define HCLK_HDCP 341
#define CLK_NR_CLKS (HCLK_HDCP + 1)
#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
/* soft-reset indices */
#define SRST_CORE0_PO 0
#define SRST_CORE1_PO 1

19
include/dt-bindings/power/rk3328-power.h Normal file
View File

@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__
#define __DT_BINDINGS_POWER_RK3328_POWER_H__
/**
* RK3328 idle id Summary.
*/
#define RK3328_PD_CORE 0
#define RK3328_PD_GPU 1
#define RK3328_PD_BUS 2
#define RK3328_PD_MSCH 3
#define RK3328_PD_PERI 4
#define RK3328_PD_VIDEO 5
#define RK3328_PD_HEVC 6
#define RK3328_PD_SYS 7
#define RK3328_PD_VPU 8
#define RK3328_PD_VIO 9
#endif