After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Jump into full u-boot mode if a 'c' character is received on the uart.
We need to adjust the spl bss/malloc area to not overlap with the
loadaddr of the kernel (sdram + 32k), so move it past u-boot instead.
For raw mmc, we store the kernel parameter area in the free space after
the MBR (if used). For nand, we use the last sector of the partition
reserved for u-boot.
This also enables the spl command in the full u-boot so the kernel
parameter area snapshot can be created.
Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
No need to use the 'status' variable, so just remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
Add a DT simple-framebuffer node to DT when booting the Linux kernel.
This will allow the kernel to inherit the framebuffer configuration from
U-Boot, and display a graphical boot console, and even run a full SW-
rendered X server.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Simon Glass <sjg@chromium.org>
We need to call the save_omap_boot_params function on am33xx/ti81xx and
other newer TI SoCs, so move the function to boot-common. Only OMAP4+
has the omap_hw_init_context function so add ifdefs to not call it on
am33xx/ti81xx. Call save_omap_boot_params from s_init on am33xx/ti81xx
boards.
Reviewed-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Add minimal support (only boot from mmc device) for the Congatec
Conga-QEVAl Evaluation Carrier Board with conga-Qmx6q (i.MX6 Quad
processor) module.
Signed-off-by: Leo Sartre <lsartre@adeneo-embedded.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
This requires that cpu_is_exynos4/5 should be made available before tzpc_init.
Hence this patch also makes necessary changes to have cpu_info in spl and
invokes arch_cpu_init before tzpc_init in low_level_init.S for smdk5250.
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
tzpc_init is common for all exynos5 boards, hence move it to
armv7/exynos so that all other boards can use it.
Also update the smdk5250 Makefile and config file.
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The number of gpio signal is packed inside CONFIG_SF_DEFAULT_CS macro
(shifted and or'ed with chip select), so it's incorrect to pass
that macro directly as an argument to gpio_direction_output() call.
Also, SPI driver sets the direction and initial value of a gpio,
used as a chip select signal, before any actual activity happens
on the bus.
So, it is safe to just remove the gpio_direction_output call,
that works incorrectly, thus making no effect, anyway.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Tested-by: Robert Winkler <robert.winkler@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
There are 3 IO expanders on the mx6qsabreauto all reset by the
same GPIO, just set it to high to use the IO.
Signed-off-by: Renato Frias <b13784@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Add i2c2 and 3 to mx6qsabreauto board, i2c3 is multiplexed
use gpio to set steering.
Signed-off-by: Renato Frias <b13784@freescale.com>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
VF610TWR is a board based on Vybrid VF610 SoC.
This patch adds basic support for Vybrid VF610TWR board.
Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This patch is essentially an update of u-boot MTD subsystem to
the state of Linux-3.7.1 with exclusion of some bits:
- the update is concentrated on NAND, no onenand or CFI/NOR/SPI
flashes interfaces are updated EXCEPT for API changes.
- new large NAND chips support is there, though some updates
have got in Linux-3.8.-rc1, (which will follow on top of this patch).
To produce this update I used tag v3.7.1 of linux-stable repository.
The update was made using application of relevant patches,
with changes relevant to U-Boot-only stuff sticked together
to keep bisectability. Then all changes were grouped together
to this patch.
Signed-off-by: Sergey Lapin <slapin@ossfans.org>
[scottwood@freescale.com: some eccstrength and build fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Did a 'strings u-boot-dtb-tegra.bin | less' and saw that both
board and board_name == beaver. Didn't test as I have no T30
Beaver board here.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Current driver of p5040 assumes 10G port follows 1G port DTSEC5 in
eth port enum structure, it will assign mdio mux depend on this assumption.
This is not true with Fman V3, which added more 1G ports after port DTSEC5
in eth port enum structure, then 10G ports on p5040 will have wrong mdio mux.
So we use dynamic index for 10G ports instead of hardcoded enum value
when doing mdio mux for 10G ports.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
PC board has different serdes clock setting with PB board, it uses same
serdes frequency setting on bank2 as on bank1. PC board can be distingushed
from PB board by checking CPLD version, if running on PC board, then fix
the serdes reference clock frequency of bank2.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Crossbar switches were wrongly programmed to
route the CPRI lanes to SFP as the connectivity table
was not correct.
Modified it correctly for SFPs connections.
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
QSGMII card has different PHY address against previous SGMII card.
We check the type of card in slots and set correct PHY address to
avoid complainning "PHY reset timed out" during u-boot booting up.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
SW7[4] is the new bit which controls the mapping of eMMC vs SDHC.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
The PHY addresses of Teranetics PHY on XAUI riser card are assigned
based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
and slot2
- Configure MDIO for 10Gig Mac
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Debug trace buffers are memory mapped in DCSR space beyond 4M.
Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Provided a default RCW for P5040, then it can use PBL to build
ramboot image.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Use QIXIS measurement registers to obtain sysclk and ddr clock. This
allows using non-standard clock speeds, set by directly writing to
clock chip or store the values in qixis clock data eeprom.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
QIXIS includes frequency measurement functions for each major processor
clock input. After reset (and after clocks are stable), QIXIS measures
the clocks against a reference frequency and stores the results in
CLK_FREQ registers. A base register supplies a multiplier which allows
directly obtaining the measured value, without requiring knowledge of
the target system or QIXIS core frequency.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use
PBL tool to produce the ramboot image.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Allow VDD voltage overriding with a command. This is an add-on feasture of
VID. To override VDD, use command vdd_override with the value of voltage
in mV, for example
vdd_override <voltage in mV, eg. 1050>
The above example will set the VDD to 1.050 volt. Any wrong value out of
range of 0.8188 to 1.2125 volt or invalid string is ignored.
In addition to the command, if overriding VDD is needed earlier in booting
process, save an variable and reboot:
setenv t4240qds_vdd_mv <voltage in mV>
saveenv
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Print more detail information including core voltage, RCW source, switch
settings, etc. with bdinfo command.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Tom Rini <trini@ti.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add Seagate GoFlex Home support
Start with dockstar configuration
define support for RTC, DATE, SATA and EXT4FS
Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
This patch creates a new config for the A5 dual core tile that includes the
generic config for the Versatile Express platform.
The generic config has been modified to provide support for the Extended
Memory Map, as used on the A5 core tile. A5 does not support the legacy
memory map.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
The current ca9x4_ct_vxp platform contains support for a Versatile
Express motherboard with a quad core A9 core tile.
This patch separates the Versatile Express motherboard code and the
A9 specific code, to ease supporting more core tiles in the next
patches.
Andre: merged the first two of Ryan's original patches and did some
checkpatch fixes.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Add sama5d3xek support with following feature
- boot from NAND flash, PMECC support, 4bit ECC @ 512 bytes sector
- boot from SPI flash support
- boot from SD card support
- LCD support
- EMAC support
- USB OHCI support
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The Freescale MPC8220 Power Architecture processors have long reached
EOL; Freescale does not even list these any more on their web site.
Remove the code to avoid wasting maitaining efforts on dead stuff.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
QSGMII card assumed to be used by default, but if SGMII card is used,
it will use different PHY address, but we don't know which card is used
until we access PHY on the card. So we check the card type slot by slot,
if we can read a PHY ID by reading a SGMII PHY address on a slot, then
the slot must have a SGMII card pluged, we mark all ports on that slot,
and fix dts to use the SGMII card PHY address when doing dts fixup
for the marked ports.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Only clear IRE bit in qixis brdcfg5 register and keep other bits
unchanged.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address.
This is the requirement for DSP cores to run in 32-bit address space.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card
PHY address is variable depends on different slot.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
1, Implemented board_ft_fman_fixup_port() to fix port for kernel.
2, Implemented fdt_fixup_board_enet() to fix node status of different
slots and interfaces.
3, Adding detection of slot present for XGMII interface.
4, There is no PHY for XFI, so removed related phy address settings.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
T4240 has voltage ID fuse. Read the fuse and configure the voltage
correctly. Core voltage has higher tolerance on over side than below.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Update the timing table to support more rank density, based on the theory
that similar density DIMMs have similar clock adjust and write level start
timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron
MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Reverse the bit sequence to set and display serdes clock frequency
correctly. The correct bit maps in BRDCFG2 are
0 1 2 3 4 5 6 7
S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0]
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add softswitch_output command for bf609-ezkit to enable softswitches.
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Set up soft switch pins properly in board init code.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Scott Jiang <scott.jiang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Add support for following features:
- nand boot, with PMECC 2bit ECC for 512 bytes sector
- SPI flash boot
- SD card boot
- LCD support
Signed-off-by: Josh Wu <josh.wu@atmel.com>
[fix -Wimplicit-function-declaration for at91_lcd_hw_init()]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Currently the cm-t35 support code lives under board/cm_t35 directory.
Some of the code can be shared with other/future CompuLab boards,
so move the cm-t35 to live under board/compulab/cm_t35 directory.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
Fix the device tree loading for panda(4430) and panda-es(4460)
Modify the board name if a 4460 panda or panda-es is detected
at run time.
In the findfdt add a check for the panda-es board name and load
the panda-es device tree blob.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
The IGEP COM AQUILA and CYGNUS are industrial processors modules with
following highlights:
o AM3352/AM3354 Texas Instruments processor
o Cortex-A8 ARM CPU
o 3.3 volts Inputs / Outputs use industrial
o 256 MB DDR3 SDRAM / 128 Megabytes FLASH
o MicroSD card reader on-board
o Ethernet controller on-board
o JTAG debug connector available
o Designed for industrial range purposes
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
We are able to tell the difference between xM Rev Ax/Bx and xM Rev Cx,
and have been for some time. The comment above the function however did
not list this, so update.
Signed-off-by: Tom Rini <trini@ti.com>
Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs,
rename twl6035_init_settings with an more generic palmas_init_settings
Signed-off-by: Nishanth Menon <nm@ti.com>
TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs
Rename twl6035 to palmas to allow reuse across multiple current and
future platforms
As part of this change, change the CONFIG_TWL6035_POWER to
CONFIG_PALMAS_POWER and update usage of header file accordingly.
Signed-off-by: Nishanth Menon <nm@ti.com>
u-boot standard i2c read prototype is
i2c_read(addr, reg, 1, &buf, 1)
twl4030_i2c_read_u8(u8 addr, u8 *val, u8 reg)
does not provide consistency, so switch the prototype to be
consistent with rest of u-boot i2c operations:
twl4030_i2c_read_u8(u8 addr, u8 reg, u8 *val)
Signed-off-by: Nishanth Menon <nm@ti.com>
u-boot standard i2c register write prototype is
i2c_reg_write(u8 addr, u8 reg, u8 val)
twl4030_i2c_write_u8(u8 addr, u8 val, u8 reg)
does not provide consistency, so switch the prototype to be
consistent with rest of u-boot i2c operations:
twl4030_i2c_write_u8(u8 addr, u8 reg, u8 val)
Signed-off-by: Nishanth Menon <nm@ti.com>
Adds CPSW support to the TI814X EVM configured with
an ET1011C PHY in GMII mode.
Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Since there are two memory areas defined, vectors and ram,
the linker will error when neither of them are specified for a
section.
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Many boot image configuration files refer to the
appropriate documentation file, but these references
contain typos in the directory and file name. Fix
them. Also fix reference to doc/README.SPL file.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Microblaze uses gpio which is connected to the system reset.
Currently gpio subsystem wasn't used for it.
Add gpio driver and change Microblaze reset logic to be done
via gpio subsystem.
There are various configurations which Microblaze can have
that's why gpio_alloc/gpio_alloc_dual(for dual channel)
function has been introduced and gpio can be allocated
dynamically.
Adding several gpios IP is also possible and supported.
For listing gpio configuration please use "gpio status" command
This patch also remove one compilation warning:
microblaze-generic.c: In function 'do_reset':
microblaze-generic.c:38:47: warning: operation on '*1073741824u'
may be undefined [-Wsequence-point]
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
MUX2_CTR is on GPIO1[5], not GPIO2[5], and it needs to be set high in order to
connect the FEC.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Devcfg device requires to load bitstream in binary format.
But u-boot also has an option for loading bitstream in bit
format. Let's handle both cases by zynqpl driver.
Also add suport for loading partial bitstreams.
The first driver version was done by:
Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
There is no change of behavior, except for the folloing line that has been
removed because the iomux mode was not set accordingly and the pad used for OTG
OC is not this one:
mxc_iomux_set_input(MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT, 1);
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
There is no change of behavior, except for older silicon revisions for which
support is removed.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
There is no change of behavior, except for older silicon revisions for which
support is removed.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Matt Sealey <matt@genesi-usa.com>
There is no change of behavior, except for older silicon revisions for which
support is removed.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
In ALT1 mode, EIM_CS2 is GPIO2[27], not ESDHC1.CD. Hence, rename
MX51_PAD_EIM_CS2__SD1_CD to MX51_PAD_EIM_CS2__GPIO2_27.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
The signal connected from this pin to the PMIC is WDOG_B, i.e. ALT0 mode, not
ALT1 (which even corresponds to nothing).
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
There is no change of behavior, even if some pad control values could probably
be simplified.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
There is no change of behavior, even if some pad control values could probably
be simplified.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
There is no change of behavior, even if some pad control values could probably
be simplified.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
