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powerpc/b4860qds: Assign DDR address in board file
B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address. This is the requirement for DSP cores to run in 32-bit address space. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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@ -13,6 +13,7 @@
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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#include <asm/fsl_law.h>
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#include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -188,3 +189,74 @@ phys_size_t initdram(int board_type)
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puts(" DDR: ");
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return dram_size;
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}
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unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
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unsigned int dbw_cap_adj[])
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{
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int i, j;
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unsigned long long total_mem, current_mem_base, total_ctlr_mem;
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unsigned long long rank_density, ctlr_density = 0;
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current_mem_base = 0ull;
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total_mem = 0;
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/*
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* This board has soldered DDR chips. DDRC1 has two rank.
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* DDRC2 has only one rank.
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* Assigning DDRC2 to lower address and DDRC1 to higher address.
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*/
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if (pinfo->memctl_opts[0].memctl_interleaving) {
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rank_density = pinfo->dimm_params[0][0].rank_density >>
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dbw_cap_adj[0];
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ctlr_density = rank_density;
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debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
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rank_density, ctlr_density);
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for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
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switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
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case FSL_DDR_CACHE_LINE_INTERLEAVING:
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case FSL_DDR_PAGE_INTERLEAVING:
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case FSL_DDR_BANK_INTERLEAVING:
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case FSL_DDR_SUPERBANK_INTERLEAVING:
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total_ctlr_mem = 2 * ctlr_density;
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break;
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default:
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panic("Unknown interleaving mode");
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}
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pinfo->common_timing_params[i].base_address =
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current_mem_base;
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pinfo->common_timing_params[i].total_mem =
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total_ctlr_mem;
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total_mem = current_mem_base + total_ctlr_mem;
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debug("ctrl %d base 0x%llx\n", i, current_mem_base);
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debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
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}
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} else {
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/*
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* Simple linear assignment if memory
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* controllers are not interleaved.
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*/
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for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
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total_ctlr_mem = 0;
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pinfo->common_timing_params[i].base_address =
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current_mem_base;
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
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/* Compute DIMM base addresses. */
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unsigned long long cap =
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pinfo->dimm_params[i][j].capacity;
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pinfo->dimm_params[i][j].base_address =
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current_mem_base;
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debug("ctrl %d dimm %d base 0x%llx\n",
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i, j, current_mem_base);
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current_mem_base += cap;
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total_ctlr_mem += cap;
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}
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debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
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pinfo->common_timing_params[i].total_mem =
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total_ctlr_mem;
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total_mem += total_ctlr_mem;
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}
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}
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debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
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return total_mem;
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}
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