mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-01 00:50:43 +09:00
imx: vision2: Convert to iomux-v3
There is no change of behavior, except for older silicon revisions for which support is removed. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This commit is contained in:
Benoît Thébaudeau
Stefano Babic
parent
3426a62a16
commit
6ea4217fd0
@ -26,10 +26,9 @@
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx5x_pins.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/iomux-mx51.h>
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#include <asm/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <i2c.h>
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@ -68,85 +67,67 @@ void hw_watchdog_reset(void)
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int val;
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/* toggle watchdog trigger pin */
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val = gpio_get_value(66);
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val = gpio_get_value(IMX_GPIO_NR(3, 2));
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val = val ? 0 : 1;
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gpio_set_value(66, val);
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gpio_set_value(IMX_GPIO_NR(3, 2), val);
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}
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#endif
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static void init_drive_strength(void)
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{
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
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static const iomux_v3_cfg_t ddr_pads[] = {
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NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0),
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NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE),
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NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0),
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NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP),
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NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS,
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PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS,
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PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE),
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NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0),
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NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0),
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NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0),
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NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0),
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NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0),
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NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP),
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NEW_PAD_CTRL(MX51_GRP_INMODE1, 0),
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NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED),
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NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED),
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NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED),
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NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED),
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/* Setting pad options */
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0,
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MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1,
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MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK,
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MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0,
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MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1,
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MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2,
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MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3,
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MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
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}
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int dram_init(void)
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@ -170,134 +151,102 @@ static void setup_weim(void)
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static void setup_uart(void)
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{
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unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
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PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
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/* console RX on Pin EIM_D25 */
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mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
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/* console TX on Pin EIM_D26 */
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mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
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static const iomux_v3_cfg_t uart_pads[] = {
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MX51_PAD_EIM_D25__UART3_RXD, /* console RX */
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MX51_PAD_EIM_D26__UART3_TXD, /* console TX */
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};
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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}
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#ifdef CONFIG_MXC_SPI
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void spi_io_init(void)
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{
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/* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
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mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
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static const iomux_v3_cfg_t spi_pads[] = {
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NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS |
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PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS |
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PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS |
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PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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};
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/* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
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/* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
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PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
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/*
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* SS1 will be used as GPIO because of uninterrupted
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* long SPI transmissions (GPIO4_25)
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*/
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mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
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PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
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/* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7);
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mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
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PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
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/* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
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imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
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}
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static void reset_peripherals(int reset)
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{
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#ifdef CONFIG_VISION2_HW_1_0
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static const iomux_v3_cfg_t fec_cfg_pads[] = {
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/* RXD1 */
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NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL),
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/* RXD2 */
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NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL),
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/* RXD3 */
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NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL),
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/* RXER */
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NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL),
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/* COL */
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NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL),
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/* RCLK */
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NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL),
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/* RXD0 */
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NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL),
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};
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static const iomux_v3_cfg_t fec_pads[] = {
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NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
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NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
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NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
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MX51_PAD_NANDF_D9__FEC_RDATA0,
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NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
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MX51_PAD_EIM_CS4__FEC_RX_ER,
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NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
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};
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#endif
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if (reset) {
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/* reset_n is on NANDF_D15 */
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gpio_direction_output(89, 0);
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gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
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#ifdef CONFIG_VISION2_HW_1_0
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/*
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* set FEC Configuration lines
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* set levels of FEC config lines
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*/
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gpio_direction_output(75, 0);
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gpio_direction_output(74, 1);
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gpio_direction_output(95, 1);
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gpio_direction_output(IMX_GPIO_NR(3, 11), 0);
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gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
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gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
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/* set direction of FEC config lines */
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gpio_direction_output(59, 0);
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gpio_direction_output(60, 0);
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gpio_direction_output(61, 0);
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gpio_direction_output(55, 1);
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gpio_direction_output(IMX_GPIO_NR(2, 27), 0);
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gpio_direction_output(IMX_GPIO_NR(2, 28), 0);
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gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
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gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
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/* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
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mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
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/* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
|
||||
mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1);
|
||||
/* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
|
||||
mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1);
|
||||
/* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
|
||||
mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1);
|
||||
/* FEC_COL - sel GPIO (3-10) for configuration -> 1 */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3);
|
||||
/* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3);
|
||||
/* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3);
|
||||
imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
|
||||
ARRAY_SIZE(fec_cfg_pads));
|
||||
#endif
|
||||
|
||||
/*
|
||||
* activate reset_n pin
|
||||
* Select mux mode: ALT3 mux port: NAND D15
|
||||
*/
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D15,
|
||||
PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX);
|
||||
/* activate reset_n pin */
|
||||
imx_iomux_v3_setup_pad(
|
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25,
|
||||
PAD_CTL_DSE_MAX));
|
||||
} else {
|
||||
/* set FEC Control lines */
|
||||
gpio_direction_input(89);
|
||||
gpio_direction_input(IMX_GPIO_NR(3, 25));
|
||||
udelay(500);
|
||||
|
||||
#ifdef CONFIG_VISION2_HW_1_0
|
||||
/* FEC RDATA[3] */
|
||||
mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
|
||||
|
||||
/* FEC RDATA[2] */
|
||||
mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
|
||||
|
||||
/* FEC RDATA[1] */
|
||||
mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
|
||||
|
||||
/* FEC RDATA[0] */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
|
||||
|
||||
/* FEC RX_CLK */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
|
||||
|
||||
/* FEC RX_ER */
|
||||
mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
|
||||
|
||||
/* FEC COL */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
|
||||
imx_iomux_v3_setup_multiple_pads(fec_pads,
|
||||
ARRAY_SIZE(fec_pads));
|
||||
#endif
|
||||
}
|
||||
}
|
||||
@ -376,155 +325,94 @@ static void power_init_mx51(void)
|
||||
|
||||
static void setup_gpios(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t gpio_pads_1[] = {
|
||||
NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE |
|
||||
PAD_CTL_DSE_MED), /* CAM_SUP_DISn */
|
||||
NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE |
|
||||
PAD_CTL_DSE_MED), /* DAB Display EN */
|
||||
NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE |
|
||||
PAD_CTL_DSE_MED), /* WDOG_TRIGGER */
|
||||
};
|
||||
|
||||
static const iomux_v3_cfg_t gpio_pads_2[] = {
|
||||
NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE |
|
||||
PAD_CTL_DSE_MED), /* Display2 TxEN */
|
||||
NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE |
|
||||
PAD_CTL_DSE_MED), /* DAB Light EN */
|
||||
NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE |
|
||||
PAD_CTL_DSE_MED), /* AUDIO_MUTE */
|
||||
NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE |
|
||||
PAD_CTL_DSE_MED), /* SPARE_OUT */
|
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE |
|
||||
PAD_CTL_DSE_MED), /* BEEPER_EN */
|
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE |
|
||||
PAD_CTL_DSE_MED), /* POWER_OFF */
|
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE |
|
||||
PAD_CTL_DSE_MED), /* FRAM_WE */
|
||||
NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE |
|
||||
PAD_CTL_DSE_MED), /* EXPANSION_EN */
|
||||
MX51_PAD_GPIO1_2__PWM1_PWMO,
|
||||
};
|
||||
|
||||
unsigned int i;
|
||||
|
||||
/* CAM_SUP_DISn, GPIO1_7 */
|
||||
mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82);
|
||||
|
||||
/* DAB Display EN, GPIO3_1 */
|
||||
mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
|
||||
mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82);
|
||||
|
||||
/* WDOG_TRIGGER, GPIO3_2 */
|
||||
mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
|
||||
mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82);
|
||||
imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1));
|
||||
|
||||
/* Now we need to trigger the watchdog */
|
||||
WATCHDOG_RESET();
|
||||
|
||||
/* Display2 TxEN, GPIO3_3 */
|
||||
mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
|
||||
mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82);
|
||||
|
||||
/* DAB Light EN, GPIO3_4 */
|
||||
mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
|
||||
mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82);
|
||||
|
||||
/* AUDIO_MUTE, GPIO3_5 */
|
||||
mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4);
|
||||
mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82);
|
||||
|
||||
/* SPARE_OUT, GPIO3_6 */
|
||||
mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
|
||||
mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82);
|
||||
|
||||
/* BEEPER_EN, GPIO3_26 */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82);
|
||||
|
||||
/* POWER_OFF, GPIO3_27 */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82);
|
||||
|
||||
/* FRAM_WE, GPIO3_30 */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82);
|
||||
|
||||
/* EXPANSION_EN, GPIO4_26 */
|
||||
mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
|
||||
|
||||
/* PWM Output GPIO1_2 */
|
||||
mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
|
||||
imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2));
|
||||
|
||||
/*
|
||||
* Set GPIO1_4 to high and output; it is used to reset
|
||||
* the system on reboot
|
||||
*/
|
||||
gpio_direction_output(4, 1);
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
|
||||
|
||||
gpio_direction_output(7, 0);
|
||||
for (i = 65; i < 71; i++)
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
|
||||
for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++)
|
||||
gpio_direction_output(i, 0);
|
||||
|
||||
gpio_direction_output(94, 0);
|
||||
gpio_direction_output(IMX_GPIO_NR(3, 30), 0);
|
||||
|
||||
/* Set POWER_OFF high */
|
||||
gpio_direction_output(91, 1);
|
||||
gpio_direction_output(IMX_GPIO_NR(3, 27), 1);
|
||||
|
||||
gpio_direction_output(90, 0);
|
||||
gpio_direction_output(IMX_GPIO_NR(3, 26), 0);
|
||||
|
||||
gpio_direction_output(122, 0);
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
|
||||
|
||||
gpio_direction_output(121, 1);
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 25), 1);
|
||||
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
static void setup_fec(void)
|
||||
{
|
||||
/*FEC_MDIO*/
|
||||
mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD);
|
||||
static const iomux_v3_cfg_t fec_pads[] = {
|
||||
NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
|
||||
PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
|
||||
MX51_PAD_NANDF_CS3__FEC_MDC,
|
||||
NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
|
||||
NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
|
||||
NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
|
||||
MX51_PAD_NANDF_D9__FEC_RDATA0,
|
||||
MX51_PAD_NANDF_CS6__FEC_TDATA3,
|
||||
MX51_PAD_NANDF_CS5__FEC_TDATA2,
|
||||
MX51_PAD_NANDF_CS4__FEC_TDATA1,
|
||||
MX51_PAD_NANDF_D8__FEC_TDATA0,
|
||||
MX51_PAD_NANDF_CS7__FEC_TX_EN,
|
||||
MX51_PAD_NANDF_CS2__FEC_TX_ER,
|
||||
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
|
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
|
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
|
||||
MX51_PAD_EIM_CS5__FEC_CRS,
|
||||
MX51_PAD_EIM_CS4__FEC_RX_ER,
|
||||
NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
|
||||
};
|
||||
|
||||
/*FEC_MDC*/
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
|
||||
|
||||
/* FEC RDATA[3] */
|
||||
mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
|
||||
|
||||
/* FEC RDATA[2] */
|
||||
mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
|
||||
|
||||
/* FEC RDATA[1] */
|
||||
mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
|
||||
|
||||
/* FEC RDATA[0] */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
|
||||
|
||||
/* FEC TDATA[3] */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
|
||||
|
||||
/* FEC TDATA[2] */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
|
||||
|
||||
/* FEC TDATA[1] */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
|
||||
|
||||
/* FEC TDATA[0] */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
|
||||
|
||||
/* FEC TX_EN */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
|
||||
|
||||
/* FEC TX_ER */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
|
||||
|
||||
/* FEC TX_CLK */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
|
||||
|
||||
/* FEC TX_COL */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
|
||||
|
||||
/* FEC RX_CLK */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
|
||||
|
||||
/* FEC RX_CRS */
|
||||
mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
|
||||
|
||||
/* FEC RX_ER */
|
||||
mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
|
||||
|
||||
/* FEC RX_DV */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
|
||||
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
|
||||
}
|
||||
|
||||
struct fsl_esdhc_cfg esdhc_cfg[1] = {
|
||||
@ -536,7 +424,7 @@ int get_mmc_getcd(u8 *cd, struct mmc *mmc)
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
|
||||
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
|
||||
*cd = gpio_get_value(0);
|
||||
*cd = gpio_get_value(IMX_GPIO_NR(1, 0));
|
||||
else
|
||||
*cd = 0;
|
||||
|
||||
@ -546,56 +434,24 @@ int get_mmc_getcd(u8 *cd, struct mmc *mmc)
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
mxc_request_iomux(MX51_PIN_SD1_CMD,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX51_PIN_SD1_CLK,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA0,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA1,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA2,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA3,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
|
||||
PAD_CTL_PUE_PULL |
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
||||
PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
|
||||
PAD_CTL_PUE_PULL |
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
|
||||
PAD_CTL_PUE_PULL |
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
|
||||
PAD_CTL_PUE_PULL |
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
|
||||
PAD_CTL_PUE_PULL |
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
|
||||
PAD_CTL_PUE_PULL |
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
||||
mxc_request_iomux(MX51_PIN_GPIO1_0,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
|
||||
PAD_CTL_HYS_ENABLE);
|
||||
mxc_request_iomux(MX51_PIN_GPIO1_1,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
|
||||
PAD_CTL_HYS_ENABLE);
|
||||
static const iomux_v3_cfg_t sd1_pads[] = {
|
||||
NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
|
||||
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
|
||||
NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
|
||||
PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
|
||||
NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
|
||||
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
|
||||
NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
|
||||
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
|
||||
NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
|
||||
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
|
||||
NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
|
||||
PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
|
||||
NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
|
||||
NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
|
||||
|
||||
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
|
||||
@ -604,13 +460,18 @@ int board_mmc_init(bd_t *bis)
|
||||
|
||||
void lcd_enable(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t lcd_pads[] = {
|
||||
MX51_PAD_DI1_PIN2__DI1_PIN2,
|
||||
MX51_PAD_DI1_PIN3__DI1_PIN3,
|
||||
};
|
||||
|
||||
int ret;
|
||||
|
||||
mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
|
||||
mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
|
||||
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
|
||||
|
||||
gpio_set_value(2, 1);
|
||||
mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
|
||||
gpio_set_value(IMX_GPIO_NR(1, 2), 1);
|
||||
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2,
|
||||
NO_PAD_CTRL));
|
||||
|
||||
ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
|
||||
if (ret)
|
||||
@ -624,9 +485,9 @@ int board_early_init_f(void)
|
||||
init_drive_strength();
|
||||
|
||||
/* Setup debug led */
|
||||
gpio_direction_output(6, 0);
|
||||
mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
|
||||
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
|
||||
PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST));
|
||||
|
||||
/* wait a little while to give the pll time to settle */
|
||||
sdelay(100000);
|
||||
@ -644,12 +505,12 @@ int board_early_init_f(void)
|
||||
static void backlight(int on)
|
||||
{
|
||||
if (on) {
|
||||
gpio_set_value(65, 1);
|
||||
gpio_set_value(IMX_GPIO_NR(3, 1), 1);
|
||||
udelay(10000);
|
||||
gpio_set_value(68, 1);
|
||||
gpio_set_value(IMX_GPIO_NR(3, 4), 1);
|
||||
} else {
|
||||
gpio_set_value(65, 0);
|
||||
gpio_set_value(68, 0);
|
||||
gpio_set_value(IMX_GPIO_NR(3, 1), 0);
|
||||
gpio_set_value(IMX_GPIO_NR(3, 4), 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user