Commit Graph

1388 Commits

Author SHA1 Message Date
Kumar Gala
97b3ecb575 85xx: Fix detection of MP cpu spin up
We were looking at the wrong memory offset to determine of a secondary
cpu had been spun up or not.  Also added a warning message if the
all the secondary cpus we expect don't spin up.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-11 17:32:56 -05:00
Kumar Gala
f3e04bdc3f 85xx: Use SVR_SOC_VER instead of SVR_VER
The recent change introduced by 'Update SVR numbers to expand support'
now requires that we use SVR_SOC_VER instead of SVR_VER if we want
to compare against a particular processor id.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-11 17:32:51 -05:00
Wolfgang Denk
950a392464 Revert merge of git://www.denx.de/git/u-boot-arm, commit 62479b18:
Reverting became necessary after it turned out that the patches in
the u-boot-arm repo were modified, and in some cases corrupted.

This reverts the following commits:

	066bebd635
	7a837b7310
	c88ae20580
	a147e56f03
	d6674e0e2a
	8c8463cce4
	c98b47ad24
	8bf69d8178
	8c16cb0d3b
	a574a73852
	1377b5583a
	1704dc2091

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-04-11 15:11:26 +02:00
Wolfgang Denk
aeff6d503b Merge branch 'master' of git://www.denx.de/git/u-boot-fdt 2008-04-08 00:20:52 +02:00
Wolfgang Denk
a1b215e2a2 Merge branch 'master' of git://www.denx.de/git/u-boot-at91 2008-04-08 00:16:36 +02:00
Wolfgang Denk
2c78febd11 Merge branch 'master' of git://www.denx.de/git/u-boot-coldfire 2008-04-08 00:10:17 +02:00
Wolfgang Denk
34e6cb8d1d Merge branch 'master' of git://www.denx.de/git/u-boot-blackfin 2008-04-08 00:06:47 +02:00
Wolfgang Denk
62479b1814 Merge branch 'master' of git://www.denx.de/git/u-boot-arm 2008-04-08 00:05:42 +02:00
Wolfgang Denk
5c395393cc Merge branch 'master' of git://www.denx.de/git/u-boot-sh 2008-04-08 00:04:39 +02:00
Wolfgang Denk
e59af4b611 Merge branch 'master' of git://www.denx.de/git/u-boot-mpc83xx
Conflicts:

	lib_ppc/board.c

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-04-07 23:59:10 +02:00
Stefan Roese
e54ec0f016 ppc4xx: Fix 4xx enet driver to support 460GT EMAC2+3
This patch fixes a problem with the RGMII setup of the 460GT. The 460GT
has 2 RGMII instances and we need to configure the 2nd RGMII instance
for the EMAC2+3 channels.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-03 14:50:34 +02:00
Jean-Christophe PLAGNIOL-VILLARD
c2a545ce33 MPC8xx: Fix libfdt support introduced in commit 77ff7b74
fdt.c: In function 'ft_cpu_setup':
fdt.c:33: warning: implicit declaration of function 'do_fixup_by_prop_u32'
fdt.c:39: warning: implicit declaration of function 'do_fixup_by_compat_u32'
fdt.c:43: warning: implicit declaration of function 'fdt_fixup_ethernet'
fdt.c:45: warning: implicit declaration of function 'fdt_fixup_memory'

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-04-02 11:07:20 -04:00
Jean-Christophe PLAGNIOL-VILLARD
1762f13b4a AT91SAM9: Move CONFIG_HAS_DATAFLASH to Makefile
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-04-01 01:46:12 +02:00
Stelian Pop
983c1db04c Port AT91CAP9 to the new headers
Adapt the existing AT91CAP9 code to the new headers and APIs.

Signed-off-by: Stelian Pop <stelian@popies.net>
2008-04-01 01:45:50 +02:00
Stelian Pop
a8a78f2d99 Move at91cap9 specific files to at91sam9 directory
AT91CAP9 and AT91SAM9 SoCs are very close hardware wise, so a
common infrastructure can be used. Let this infrastructure be
named after the AT91SAM9 family, and move the existing AT91CAP9
files to the new place.

Signed-off-by: Stelian Pop <stelian@popies.net>
2008-04-01 01:44:18 +02:00
Stelian Pop
61106a5658 Use timer_init() instead of board supplied interrupt_init()
The timer on AT91CAP9/AT91SAM9 is supplied by the SoC, and not by
the board, so use timer_init() instead of interrupt_init().

Signed-off-by: Stelian Pop <stelian@popies.net>
2008-04-01 01:44:05 +02:00
TsiChung Liew
9b46432fc6 ColdFire: Fix alignment issue after CONFIG_IDENT_STRING in start.S
When the version_string function in start.S is not 4-byte align,
it will cause the compiler generates "unaligned opcodes detected
in executable segment". This issue affects all ColdFire CPUs.
By adding .align 4 after CONFIG_IDENT_STRING, it will pad 0's if
it is not aligned.

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Acked-by: John Rigby <jrigby@freescale.com>
2008-03-31 15:10:32 -06:00
TsiChung Liew
bae61eefe1 ColdFire: Add dspi and serial flash support for MCF5445x
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Acked-by: John Rigby <jrigby@freescale.com>
2008-03-31 15:10:29 -06:00
TsiChung Liew
48ead7a7a9 ColdFire: Remove R5200 board
This board never went into production

Signed-off-by: Zachary P. Landau <zachary.landau@labxtechnologies.com>
Acked-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Acked-by: John Rigby <jrigby@freescale.com>
2008-03-31 15:10:24 -06:00
Matthew Fettke
f71d9d91a2 ColdFire: Added MCF5275 cpu support.
Signed-off-by: Matthew Fettke <mfettke@videon-central.com>
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Acked-by: John Rigby <jrigby@freescale.com>
2008-03-31 15:09:08 -06:00
TsiChung Liew
43d6064239 ColdFire: Update correct FLASHBAR and RAMBAR1 for MCF5282
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Acked-by: John Rigby <jrigby@freescale.com>
2008-03-31 15:17:10 -05:00
Larry Johnson
eb14ebe813 ppc4xx: Add CFG_MEM_TOP_HIDE to Denali SPD-based SDRAM setup
Signed-off-by: Larry Johnson <lrj@acm.org>
2008-03-31 12:20:59 +02:00
Mike Frysinger
9171fc8172 Blackfin: unify cpu and boot modes
All of the duplicated code for Blackfin processors and boot modes have been
unified.  After all, the core is the same for all processors, just the
peripheral set differs (which gets handled in the drivers).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-03-30 15:50:19 -04:00
David Brownell
480ed1dea1 use correct at91rm9200 register name
This fixes a naming bug for at91rm9200 lowlevel init code:
NOR boot flash is on chipselect 0, not chipselect 2.  This
makes code use the register name from chip datasheets.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2008-03-30 15:38:05 +02:00
Peter Pearse
066bebd635 Bracket READ_TIMER macro in cpu/arm1136/omap24xx/interrupts.c
to prevent compilation error.

Signed-off-by: Peter Pearse <peter.pearse@arm.com>
2008-03-30 11:34:09 +01:00
Sascha Hauer
c98b47ad24 core support for Freescale mx31
This patch adds the core support for Freescale mx31

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
2008-03-30 11:30:43 +01:00
Sascha Hauer
8bf69d8178 Separate omap24xx specific code from arm1136
Move omap24xx code to cpu/arm1136/omap24xx, rename include/asm-arm/arch-arm1136 to cpu/arm1136/omap24xx.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
2008-03-30 11:28:46 +01:00
Pieter Voorthuijsen
1377b5583a Removes all board specific code from the arch. part for DM644x (DaVinci) boards
Signed-off-by: Pieter Voorthuijsen <pv@prodrive.nl>
2008-03-30 11:11:34 +01:00
Dirk Behme
1704dc2091 - Remove *_masked() functions as noted by Wolfgang
- Adapt register naming to recent TI spec (sprue26, March 2007)
- Fix reset_timer() handling
- As reported by Pieter [1] the overflow fix introduced a
delay of factor 16 (e.g 2 seconds became 32). While the
overflow fix is basically okay, it missed to divide udelay by
16, too. Fix this.
[1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/38179
- Remove software division of timer count value (DIV(x)
macro) and do it in hardware (TIM_CLK_DIV).
Many thanks to Troy Kisky <troy.kisky@boundarydevices.com>
and Pieter Voorthuijsen <pieter.voorthuijsen@Prodrive.nl> for
the hints & testing!

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>

Acked-by: Pieter Voorthuijsen <pieter.voorthuijsen@Prodrive.nl>
2008-03-30 11:09:01 +01:00
Joakim Tjernlund
70431e8a73 Make MPC83xx one step closer to full relocation.
Remove a few absolute references to CFG_MONITOR_BASE for ppc/mpc83xx
and use GOT relative reference.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28 18:51:54 -05:00
Kim Phillips
e5c4ade4db mpc83xx: cleanup System Part and Revision ID Register (SPRIDR) code
in the spirit of commit 1ced121600,
85xx's "Update SVR numbers to expand support", simplify SPRIDR processing
and processor ID display.  Add REVID_{MAJ,MIN}OR macros to make
REVID dependent code simpler.  Also added PARTID_NO_E and IS_E_PROCESSOR
convenience macros.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28 16:01:06 -05:00
Kim Phillips
81fd52c6c8 mpc83xx: display ddr frequency in board_add_ram_info banner
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28 14:32:09 -05:00
Kim Phillips
35cf155c5e mpc83xx: unreinvent mem_clk
delete ddr_clk and use mem_clk instead.  Rename other ddr_*_clk to
mem_*_clk for consistency's sake.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28 14:32:07 -05:00
Nobuhiro Iwamatsu
e92c95180b sh: Add support SH4 cache control
Add support SH4 cache control and flash_cache function

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28 14:16:13 +09:00
Nobuhiro Iwamatsu
ab8f4d40d0 sh: Move SuperH PCI driver from cpu/sh4 to drivers/pci
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28 14:16:13 +09:00
Yusuke Goda
1a2334a4eb sh: Add support PCI of SuperH and SH7780
This patch add support PCI of SuperH base code and SH7780 specific code.

Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28 14:16:12 +09:00
Markus Brunner
f766cdf89b ppc4xx: PPC405EP Set EMAC noise filter bits
This bug was introduced with commit aee747f19b
which enabled CFG_4xx_GPIO_TABLE for PPC405 and unintentionally
disabled the setting of the emac noise filter bits for PPC405EP when CFG_4xx_GPIO_TABLE is set.

Signed-off-by: Markus Brunner <super.firetwister@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27 10:47:28 +01:00
Mike Nuss
f66e2c8b25 ppc4xx: Reconfigure PLL for 667MHz processor for PPC440EPx
On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured
after startup to change the speed of the clocks. This patch adds the
option CFG_PLL_RECONFIG. If this option is set to 667, the CPU
initialization code will reconfigure the PLL to run the system with a CPU
frequency of 667MHz and PLB frequency of 166MHz, without the need for an
external EEPROM.

Signed-off-by: Mike Nuss <mike@terascala.com>
Acked-by: Stefan Roese <sr@denx.de>
2008-03-27 10:38:54 +01:00
Stefan Roese
9ad31989de ppc4xx: Fix compilation warning in 4xx_enet.c
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27 09:54:41 +01:00
Stefan Roese
4c9e855734 ppc4xx: Add AMCC Glacier 406GT eval board support
This patch adds support for the AMCC Glacier 460GT eval board.
The main difference to the Canyonlands board are listed here:

- 4 ethernet ports instead of 2
- no SATA port
- no USB port

Currently EMAC2+3 are not working. This will be fixed in a later
release.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27 09:54:41 +01:00
Stefan Roese
d8bd643141 ppc4xx: Mask 'vec' with 0x1f in uic_interrupt() for bit set/clear
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27 09:54:03 +01:00
Kumar Gala
dd6c910aad 85xx: Add cpu_mp_lmb_reserve helper to reserve boot page
Provide a board_lmb_reserve helper function to ensure we reserve
the page of memory we are using for the boot page translation code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
Kumar Gala
79679d8002 85xx: Update multicore boot mechanism to ePAPR v0.81 spec
The following changes are needed to be inline with ePAPR v0.81:

* r4, r5 and now always set to 0 on boot release
* r7 is used to pass the size of the initial map area (IMA)
* EPAPR_MAGIC value changed for book-e processors
* changes in the spin table layout
* spin table supports a 64-bit physical release address

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
Kumar Gala
a5af4b358a 85xx: Fix merge duplication
ft_fixup_cpu() got duplicated in some merge snafu.  Remove the duplicate.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
James Yang
a3e77fa535 85xx: Speed up get_ddr_freq() and get_bus_freq()
get_ddr_freq() and get_bus_freq() used get_sys_info() each time they were
called.  However, get_sys_info() recalculates extraneous information when
called each time.  Have get_ddr_freq() and get_bus_freq() return memoized
values from global_data instead.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
James Yang
e9ea679918 85xx: Show DDR memory data rate in addition to the memory clock frequency.
Show the DDR memory data rate in addition to the memory clock
frequency.  For DDR/DDR2 memories the memory data rate is 2x the
memory clock.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
James Yang
591933ca6e 85xx: get_tbclk() speed up and rounding fix
Speed up get_tbclk() by referencing pre-computed bus clock
frequency value from global data instead of sys_info_t.  Fix
rounding of result to nearest; previously it was rounding
upwards.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
Andy Fleming
1ced121600 Update SVR numbers to expand support
FSL has taken to using SVR[16:23] as an SOC sub-version field.  This
is used to distinguish certain variants within an SOC family.  To
account for this, we add the SVR_SOC_VER() macro, and update the SVR_*
constants to reflect the larger value.  We also add SVR numbers for all
of the current variants.  Finally, to make things neater, rather than
use an enormous switch statement to print out the CPU type, we create
and array of SVR/name pairs (using a macro), and print out the CPU name
that matches the SVR SOC version.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-03-26 11:43:04 -05:00
Kumar Gala
7aff0c051a 85xx: Added support for multicore boot mechanism
Added the cpu command that provides a generic mechanism to get status,
reset, and release secondary cores in multicore processors.

Added support for using the ePAPR defined spin-table mechanism on 85xx.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-03-26 11:43:03 -05:00
Kumar Gala
ec2b74ffd3 85xx: Added support for multicore boot mechanism
Added the cpu command that provides a generic mechanism to get status,
reset, and release secondary cores in multicore processors.

Added support for using the ePAPR defined spin-table mechanism on 85xx.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:03 -05:00