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https://github.com/brain-hackers/u-boot-brain
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Update SVR numbers to expand support
FSL has taken to using SVR[16:23] as an SOC sub-version field. This is used to distinguish certain variants within an SOC family. To account for this, we add the SVR_SOC_VER() macro, and update the SVR_* constants to reflect the larger value. We also add SVR numbers for all of the current variants. Finally, to make things neater, rather than use an enormous switch statement to print out the CPU type, we create and array of SVR/name pairs (using a macro), and print out the CPU name that matches the SVR SOC version. Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Andy Fleming
Andrew Fleming-AFLEMING
parent
b83eef440c
commit
1ced121600
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@ -1,5 +1,5 @@
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/*
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* Copyright 2004,2007 Freescale Semiconductor, Inc.
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* Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
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* (C) Copyright 2002, 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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@ -30,6 +30,39 @@
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#include <command.h>
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#include <asm/cache.h>
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struct cpu_type {
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char name[15];
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u32 soc_ver;
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};
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#define CPU_TYPE_ENTRY(x) {#x, SVR_##x}
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struct cpu_type cpu_type_list [] = {
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CPU_TYPE_ENTRY(8533),
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CPU_TYPE_ENTRY(8533_E),
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CPU_TYPE_ENTRY(8540),
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CPU_TYPE_ENTRY(8541),
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CPU_TYPE_ENTRY(8541_E),
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CPU_TYPE_ENTRY(8543),
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CPU_TYPE_ENTRY(8543_E),
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CPU_TYPE_ENTRY(8544),
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CPU_TYPE_ENTRY(8544_E),
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CPU_TYPE_ENTRY(8545),
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CPU_TYPE_ENTRY(8545_E),
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CPU_TYPE_ENTRY(8547_E),
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CPU_TYPE_ENTRY(8548),
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CPU_TYPE_ENTRY(8548_E),
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CPU_TYPE_ENTRY(8555),
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CPU_TYPE_ENTRY(8555_E),
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CPU_TYPE_ENTRY(8560),
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CPU_TYPE_ENTRY(8567),
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CPU_TYPE_ENTRY(8567_E),
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CPU_TYPE_ENTRY(8568),
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CPU_TYPE_ENTRY(8568_E),
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CPU_TYPE_ENTRY(8572),
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CPU_TYPE_ENTRY(8572_E),
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};
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int checkcpu (void)
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{
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sys_info_t sysinfo;
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@ -39,47 +72,26 @@ int checkcpu (void)
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uint fam;
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uint ver;
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uint major, minor;
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int i;
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u32 ddr_ratio;
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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svr = get_svr();
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ver = SVR_VER(svr);
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ver = SVR_SOC_VER(svr);
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major = SVR_MAJ(svr);
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minor = SVR_MIN(svr);
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puts("CPU: ");
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switch (ver) {
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case SVR_8540:
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puts("8540");
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break;
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case SVR_8541:
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puts("8541");
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break;
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case SVR_8555:
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puts("8555");
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break;
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case SVR_8560:
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puts("8560");
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break;
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case SVR_8548:
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puts("8548");
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break;
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case SVR_8548_E:
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puts("8548_E");
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break;
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case SVR_8544:
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puts("8544");
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break;
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case SVR_8544_E:
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puts("8544_E");
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break;
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case SVR_8568_E:
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puts("8568_E");
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break;
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default:
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for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
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if (cpu_type_list[i].soc_ver == ver) {
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puts(cpu_type_list[i].name);
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break;
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}
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if (i == ARRAY_SIZE(cpu_type_list))
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puts("Unknown");
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break;
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}
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
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pvr = get_pvr();
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@ -142,10 +154,9 @@ int checkcpu (void)
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printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
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}
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if (ver == SVR_8560) {
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printf("CPM: %lu Mhz\n",
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sysinfo.freqSystemBus / 1000000);
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}
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#ifdef CONFIG_CPM2
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printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
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#endif
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puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
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@ -69,7 +69,7 @@ checkcpu(void)
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
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svr = get_svr();
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ver = SVR_VER(svr);
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ver = SVR_SOC_VER(svr);
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major = SVR_MAJ(svr);
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minor = SVR_MIN(svr);
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@ -879,22 +879,42 @@
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#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
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#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
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/* Some parts define SVR[0:23] as the SOC version */
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#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */
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/*
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* SVR_VER() Version Values
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* SVR_SOC_VER() Version Values
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*/
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#define SVR_8540 0x8030
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#define SVR_8560 0x8070
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#define SVR_8555 0x8079
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#define SVR_8541 0x807A
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#define SVR_8544 0x8034
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#define SVR_8544_E 0x803C
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#define SVR_8548 0x8031
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#define SVR_8548_E 0x8039
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#define SVR_8610 0x80A0
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#define SVR_8641 0x8090
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#define SVR_8568_E 0x807D
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#define SVR_8533 0x803400
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#define SVR_8533_E 0x803C00
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#define SVR_8540 0x803000
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#define SVR_8541 0x807200
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#define SVR_8541_E 0x807A00
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#define SVR_8543 0x803200
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#define SVR_8543_E 0x803A00
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#define SVR_8544 0x803401
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#define SVR_8544_E 0x803C01
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#define SVR_8545 0x803102
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#define SVR_8545_E 0x803902
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#define SVR_8547_E 0x803901
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#define SVR_8548 0x803100
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#define SVR_8548_E 0x803900
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#define SVR_8555 0x807100
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#define SVR_8555_E 0x807900
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#define SVR_8560 0x807000
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#define SVR_8567 0x807600
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#define SVR_8567_E 0x807E00
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#define SVR_8568 0x807500
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#define SVR_8568_E 0x807D00
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#define SVR_8572 0x80E000
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#define SVR_8572_E 0x80E800
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#define SVR_8610 0x80A000
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#define SVR_8641 0x809000
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#define SVR_8641D 0x809001
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/* I am just adding a single entry for 8260 boards. I think we may be
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