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https://github.com/brain-hackers/u-boot-brain
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ColdFire: Remove R5200 board
This board never went into production Signed-off-by: Zachary P. Landau <zachary.landau@labxtechnologies.com> Acked-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com> Acked-by: John Rigby <jrigby@freescale.com>
This commit is contained in:
TsiChung Liew
John Rigby
parent
545c8e0a7c
commit
48ead7a7a9
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@ -654,10 +654,6 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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TASREG MCF5249
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Zachary P. Landau <zachary.landau@labxtechnologies.com>
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r5200 mcf52x2
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TsiChung Liew <Tsi-Chung.Liew@freescale.com>
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M52277EVB mcf5227x
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1
MAKEALL
1
MAKEALL
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@ -667,7 +667,6 @@ LIST_coldfire=" \
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M54455EVB \
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M5475AFE \
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M5485AFE \
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r5200 \
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TASREG \
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"
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3
Makefile
3
Makefile
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@ -1828,9 +1828,6 @@ M5282EVB_config : unconfig
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TASREG_config : unconfig
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@$(MKCONFIG) $(@:_config=) m68k mcf52x2 tasreg esd
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r5200_config : unconfig
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@$(MKCONFIG) $(@:_config=) m68k mcf52x2 r5200
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M5329AFEE_config \
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M5329BFEE_config : unconfig
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@case "$@" in \
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@ -1,44 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o mii.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -1,25 +0,0 @@
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0x10000000
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@ -1,303 +0,0 @@
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/*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fec.h>
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#include <asm/immap.h>
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#include <config.h>
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#include <net.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
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#undef MII_DEBUG
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#undef ET_DEBUG
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int fecpin_setclear(struct eth_device *dev, int setclear)
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{
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if (setclear) {
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/* Enable Ethernet pins */
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mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
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} else {
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}
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return 0;
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}
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#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
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#include <miiphy.h>
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/* Make MII read/write commands for the FEC. */
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#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18))
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#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff))
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/* PHY identification */
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#define PHY_ID_LXT970 0x78100000 /* LXT970 */
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#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
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#define PHY_ID_82555 0x02a80150 /* Intel 82555 */
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#define PHY_ID_QS6612 0x01814400 /* QS6612 */
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#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
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#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
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#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
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#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */
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#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */
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#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */
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#define STR_ID_LXT970 "LXT970"
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#define STR_ID_LXT971 "LXT971"
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#define STR_ID_82555 "Intel82555"
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#define STR_ID_QS6612 "QS6612"
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#define STR_ID_AMD79C784 "AMD79C784"
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#define STR_ID_LSI80225 "LSI80225"
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#define STR_ID_LSI80225B "LSI80225/B"
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#define STR_ID_DP83848VV "N83848"
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#define STR_ID_DP83849 "N83849"
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#define STR_ID_KS8721BL "KS8721BL"
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/****************************************************************************
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* mii_init -- Initialize the MII for MII command without ethernet
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* This function is a subset of eth_init
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****************************************************************************
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*/
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void mii_reset(struct fec_info_s *info)
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{
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volatile fec_t *fecp = (fec_t *) (info->miibase);
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int i;
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fecp->ecr = FEC_ECR_RESET;
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for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
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udelay(1);
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}
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if (i == FEC_RESET_DELAY) {
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printf("FEC_RESET_DELAY timeout\n");
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}
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}
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/* send command to phy using mii, wait for result */
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uint mii_send(uint mii_cmd)
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{
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struct fec_info_s *info;
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struct eth_device *dev;
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volatile fec_t *ep;
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uint mii_reply;
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int j = 0;
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/* retrieve from register structure */
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dev = eth_get_dev();
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info = dev->priv;
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ep = (fec_t *) info->miibase;
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ep->mmfr = mii_cmd; /* command to phy */
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/* wait for mii complete */
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while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
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udelay(1);
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j++;
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}
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if (j >= MCFFEC_TOUT_LOOP) {
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printf("MII not complete\n");
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return -1;
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}
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mii_reply = ep->mmfr; /* result from phy */
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ep->eir = FEC_EIR_MII; /* clear MII complete */
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#ifdef ET_DEBUG
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printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
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__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
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#endif
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return (mii_reply & 0xffff); /* data read from phy */
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}
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#endif /* CFG_DISCOVER_PHY || (CONFIG_CMD_MII) */
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#if defined(CFG_DISCOVER_PHY)
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int mii_discover_phy(struct eth_device *dev)
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{
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#define MAX_PHY_PASSES 11
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struct fec_info_s *info = dev->priv;
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int phyaddr, pass;
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uint phyno, phytype;
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if (info->phyname_init)
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return info->phy_addr;
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phyaddr = -1; /* didn't find a PHY yet */
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for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
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if (pass > 1) {
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/* PHY may need more time to recover from reset.
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* The LXT970 needs 50ms typical, no maximum is
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* specified, so wait 10ms before try again.
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* With 11 passes this gives it 100ms to wake up.
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*/
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udelay(10000); /* wait 10ms */
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}
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for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
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phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
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#ifdef ET_DEBUG
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printf("PHY type 0x%x pass %d type\n", phytype, pass);
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#endif
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if (phytype != 0xffff) {
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phyaddr = phyno;
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phytype <<= 16;
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phytype |=
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mii_send(mk_mii_read(phyno, PHY_PHYIDR2));
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switch (phytype & 0xffffffff) {
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case PHY_ID_KS8721BL:
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strcpy(info->phy_name,
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STR_ID_KS8721BL);
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info->phyname_init = 1;
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break;
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default:
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strcpy(info->phy_name, "unknown");
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info->phyname_init = 1;
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break;
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}
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#ifdef ET_DEBUG
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printf("PHY @ 0x%x pass %d type ", phyno, pass);
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switch (phytype & 0xffffffff) {
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case PHY_ID_KS8721BL:
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printf(STR_ID_KS8721BL);
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break;
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default:
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printf("0x%08x\n", phytype);
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break;
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}
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#endif
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}
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}
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}
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if (phyaddr < 0)
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printf("No PHY device found.\n");
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return phyaddr;
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}
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#endif /* CFG_DISCOVER_PHY */
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int mii_init(void) __attribute__((weak,alias("__mii_init")));
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void __mii_init(void)
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{
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volatile fec_t *fecp;
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struct fec_info_s *info;
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struct eth_device *dev;
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int miispd = 0, i = 0;
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u16 autoneg = 0;
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/* retrieve from register structure */
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dev = eth_get_dev();
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info = dev->priv;
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fecp = (fec_t *) info->miibase;
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fecpin_setclear(dev, 1);
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mii_reset(info);
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/* We use strictly polling mode only */
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fecp->eimr = 0;
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/* Clear any pending interrupt */
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fecp->eir = 0xffffffff;
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/* Set MII speed */
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miispd = (gd->bus_clk / 1000000) / 5;
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fecp->mscr = miispd << 1;
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info->phy_addr = mii_discover_phy(dev);
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#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
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while (i < MCFFEC_TOUT_LOOP) {
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autoneg = 0;
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miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
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i++;
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if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
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break;
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udelay(500);
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}
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if (i >= MCFFEC_TOUT_LOOP) {
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printf("Auto Negotiation not complete\n");
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}
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/* adapt to the half/full speed settings */
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info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
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info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
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}
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/*****************************************************************************
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* Read and write a MII PHY register, routines used by MII Utilities
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*
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* FIXME: These routines are expected to return 0 on success, but mii_send
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* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
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* no PHY connected...
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* For now always return 0.
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* FIXME: These routines only work after calling eth_init() at least once!
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* Otherwise they hang in mii_send() !!! Sorry!
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*****************************************************************************/
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int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg,
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unsigned short *value)
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{
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short rdreg; /* register working value */
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#ifdef MII_DEBUG
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printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
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#endif
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rdreg = mii_send(mk_mii_read(addr, reg));
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*value = rdreg;
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#ifdef MII_DEBUG
|
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printf("0x%04x\n", *value);
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#endif
|
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|
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return 0;
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}
|
||||
|
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int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
|
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unsigned short value)
|
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{
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short rdreg; /* register working value */
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|
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#ifdef MII_DEBUG
|
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printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
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#endif
|
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rdreg = mii_send(mk_mii_write(addr, reg, value));
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#ifdef MII_DEBUG
|
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printf("0x%04x\n", value);
|
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#endif
|
||||
|
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return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
|
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|
|
@ -1,124 +0,0 @@
|
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/*
|
||||
* (C) Copyright 2000-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/m5271.h>
|
||||
#include <asm/immap_5271.h>
|
||||
|
||||
|
||||
int checkboard (void) {
|
||||
puts ("Board: R5200 Ethernet Module\n");
|
||||
return 0;
|
||||
};
|
||||
|
||||
long int initdram (int board_type) {
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Set CS2 pin to be SD_CS0
|
||||
*/
|
||||
mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
|
||||
| MCF_GPIO_PAR_CS_PAR_CS2);
|
||||
|
||||
mbar_writeByte(MCF_GPIO_PAR_SDRAM, mbar_readByte(MCF_GPIO_PAR_SDRAM)
|
||||
| MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(0x01));
|
||||
|
||||
/*
|
||||
* Check to see if the SDRAM has already been initialized
|
||||
* by a run control tool
|
||||
*/
|
||||
if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
|
||||
/*
|
||||
* Initialize DRAM Control Register: DCR
|
||||
*/
|
||||
mbar_writeShort(MCF_SDRAMC_DCR, MCF_SDRAMC_DCR_RTIM(0x01)
|
||||
| MCF_SDRAMC_DCR_RC(0x30));
|
||||
|
||||
/*
|
||||
* Initialize DACR0
|
||||
*/
|
||||
mbar_writeLong(MCF_SDRAMC_DACR0,
|
||||
MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18)
|
||||
| MCF_SDRAMC_DACRn_CASL(0)
|
||||
| MCF_SDRAMC_DACRn_CBM(3)
|
||||
| MCF_SDRAMC_DACRn_PS(2));
|
||||
|
||||
/*
|
||||
* Initialize DMR0
|
||||
*/
|
||||
mbar_writeLong(MCF_SDRAMC_DMR0,
|
||||
MCF_SDRAMC_DMRn_BAM_8M
|
||||
| MCF_SDRAMC_DMRn_V);
|
||||
|
||||
/*
|
||||
* Set IP bit in DACR
|
||||
*/
|
||||
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
|
||||
| MCF_SDRAMC_DACRn_IP);
|
||||
|
||||
/*
|
||||
* Wait at least 20ns to allow banks to precharge
|
||||
*/
|
||||
for (i = 0; i < 5; i++)
|
||||
asm(" nop");
|
||||
|
||||
/*
|
||||
* Write to this block to initiate precharge
|
||||
*/
|
||||
*(u16 *)(CFG_SDRAM_BASE) = 0x9696;
|
||||
|
||||
/*
|
||||
* Set RE bit in DACR
|
||||
*/
|
||||
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
|
||||
| MCF_SDRAMC_DACRn_RE);
|
||||
|
||||
|
||||
/*
|
||||
* Wait for at least 8 auto refresh cycles to occur
|
||||
*/
|
||||
for (i = 0; i < 2000; i++)
|
||||
asm(" nop");
|
||||
|
||||
/*
|
||||
* Finish the configuration by issuing the MRS.
|
||||
*/
|
||||
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
|
||||
| MCF_SDRAMC_DACRn_MRS);
|
||||
|
||||
|
||||
/*
|
||||
* Write to the SDRAM Mode Register
|
||||
*/
|
||||
*(u16 *)(CFG_SDRAM_BASE + 0x1000) = 0x9696;
|
||||
}
|
||||
|
||||
return CFG_SDRAM_SIZE * 1024 * 1024;
|
||||
};
|
||||
|
||||
int testdram (void) {
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf ("DRAM test not implemented!\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -1,144 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(m68k)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mcf52x2/start.o (.text)
|
||||
lib_m68k/traps.o (.text)
|
||||
cpu/mcf52x2/interrupts.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/environment.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
|
||||
.reloc :
|
||||
{
|
||||
__got_start = .;
|
||||
*(.got)
|
||||
__got_end = .;
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
_sbss = .;
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -56,9 +56,7 @@
|
|||
_vectors:
|
||||
|
||||
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
|
||||
#if defined(CONFIG_R5200)
|
||||
.long 0x400
|
||||
#elif defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
|
||||
#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
|
||||
.long _start - TEXT_BASE
|
||||
#else
|
||||
.long _START
|
||||
|
|
@ -185,18 +183,6 @@ _after_flashbar_copy:
|
|||
movec %d0, %VBR
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_R5200
|
||||
move.l #(_flash_setup-CFG_FLASH_BASE), %a0
|
||||
move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1
|
||||
move.l #(CFG_INIT_RAM_ADDR), %a2
|
||||
_copy_flash:
|
||||
move.l (%a0)+, (%a2)+
|
||||
cmp.l %a0, %a1
|
||||
bgt.s _copy_flash
|
||||
jmp CFG_INIT_RAM_ADDR
|
||||
_after_flash_copy:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_M5275
|
||||
/* Initialize IPSBAR */
|
||||
move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
|
||||
|
|
@ -230,24 +216,6 @@ _after_flash_copy:
|
|||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
|
||||
#ifdef CONFIG_R5200
|
||||
_flash_setup:
|
||||
/* CSAR0 */
|
||||
move.l #((CFG_FLASH_BASE & 0xffff0000) >> 16), %d0
|
||||
move.w %d0, 0x40000080
|
||||
|
||||
/* CSCR0 */
|
||||
move.l #0x2180, %d0 /* 8 wait states, 16bit port, auto ack, */
|
||||
move.w %d0, 0x4000008A
|
||||
|
||||
/* CSMR0 */
|
||||
move.l #0x001f0001, %d0 /* 2 MB, valid */
|
||||
move.l %d0, 0x40000084
|
||||
|
||||
jmp _after_flash_copy.L
|
||||
_flash_setup_end:
|
||||
#endif
|
||||
|
||||
/*
|
||||
* void relocate_code (addr_sp, gd, addr_moni)
|
||||
*
|
||||
|
|
|
|||
|
|
@ -1,204 +0,0 @@
|
|||
/*
|
||||
* Configuation settings for the R5200 board
|
||||
*
|
||||
* (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
|
||||
* Based on Motorola MC5272C3 board config
|
||||
* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef _R5200_H
|
||||
#define _R5200_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_MCF52x2 /* define processor family */
|
||||
#define CONFIG_M5271 /* define processor type */
|
||||
#define CONFIG_R5200 /* define board type */
|
||||
|
||||
#define CONFIG_MCFTMR
|
||||
|
||||
#define CONFIG_MCFUART
|
||||
#define CFG_UART_PORT (0)
|
||||
#define CONFIG_BAUDRATE 19200
|
||||
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
|
||||
|
||||
#define CONFIG_WATCHDOG
|
||||
#define CONFIG_WATCHDOG_TIMEOUT 0xFFFF /* clock modulus */
|
||||
|
||||
/* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash
|
||||
*/
|
||||
#ifndef CONFIG_MONITOR_IS_IN_RAM
|
||||
#define CFG_ENV_OFFSET 0x20000
|
||||
#define CFG_ENV_SECT_SIZE 0x20000
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_IS_EMBEDDED 1
|
||||
#else
|
||||
#define CFG_ENV_ADDR 0xf0020000
|
||||
#define CFG_ENV_SECT_SIZE 0x2000
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_NET
|
||||
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#undef CONFIG_CMD_LOADB
|
||||
|
||||
#define CONFIG_MCFFEC
|
||||
#ifdef CONFIG_MCFFEC
|
||||
# define CONFIG_NET_MULTI 1
|
||||
# define CONFIG_MII 1
|
||||
# define CFG_DISCOVER_PHY
|
||||
# define CFG_RX_ETH_BUFFER 8
|
||||
# define CFG_FAULT_ECHO_LINK_DOWN
|
||||
|
||||
# define CFG_FEC0_PINMUX 0
|
||||
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
|
||||
# define MCFFEC_TOUT_LOOP 50000
|
||||
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
|
||||
# ifndef CFG_DISCOVER_PHY
|
||||
# define FECDUPLEX FULL
|
||||
# define FECSPEED _100BASET
|
||||
# else
|
||||
# ifndef CFG_FAULT_ECHO_LINK_DOWN
|
||||
# define CFG_FAULT_ECHO_LINK_DOWN
|
||||
# endif
|
||||
# endif /* CFG_DISCOVER_PHY */
|
||||
#endif
|
||||
|
||||
/* Note: We only copy one sectors worth of application code from location
|
||||
* 10200000 for speed purposes. Increase the size if necessary */
|
||||
#define CONFIG_BOOTCOMMAND "cp.b 10200000 0 20000; go 400"
|
||||
#define CONFIG_BOOTDELAY 1
|
||||
|
||||
#define CFG_PROMPT "u-boot> "
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x00002000
|
||||
|
||||
#define CFG_MEMTEST_START 0x400
|
||||
#define CFG_MEMTEST_END 0x380000
|
||||
|
||||
#define CFG_HZ 1000000
|
||||
#define CFG_CLK 100000000
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
|
||||
#define CFG_MBAR 0x40000000 /* Register Base Addrs */
|
||||
|
||||
#define CFG_ENET_BD_BASE 0x480000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR 0x20000000
|
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
|
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */
|
||||
#define CFG_FLASH_BASE 0x10000000
|
||||
|
||||
#ifdef CONFIG_MONITOR_IS_IN_RAM
|
||||
#define CFG_MONITOR_BASE 0x20000
|
||||
#else
|
||||
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
|
||||
#endif
|
||||
|
||||
#define CFG_MONITOR_LEN 0x20001
|
||||
#define CFG_MALLOC_LEN (256 << 10)
|
||||
#define CFG_BOOTPARAMS_LEN 64*1024
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization ??
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
|
||||
#define CFG_FLASH_ERASE_TOUT 1000
|
||||
|
||||
#define CFG_FLASH_CFI 1
|
||||
#define CFG_FLASH_CFI_DRIVER 1
|
||||
#define CFG_FLASH_SIZE 0x800000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 16
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Memory bank definitions
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Port configuration
|
||||
*/
|
||||
#define CFG_FECI2C 0xF0
|
||||
|
||||
#endif /* _R5200_H */
|
||||
Loading…
Reference in New Issue
Block a user