Commit Graph

57026 Commits

Author SHA1 Message Date
Jagan Teki
d7a672e35f test/dm: clk: Add clk_get_by_index[_nodev] test
Add sample dm clk test for clk_get_by_index and
clk_get_by_index_nodev functionality code.

Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-09 00:44:13 +05:30
Jagan Teki
dcb63fcd16 clk: Use clk_get_by_index_tail()
clk_get_by_index_tail() now handle common clk get by index
code so use it from clk_get_by_indexed_prop().

Cc: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-09 00:44:13 +05:30
Jagan Teki
75f98314f9 clk: Get the CLK by index without device
Getting a CLK by index with device is not straight forward
for some use-cases like handling clock operations for child
node in parent driver. So we need to process the child node
in parent probe via ofnode and process CLK operation for child
without udevice but with ofnode.

So add clk_get_by_index_nodev() and move the common code
in clk_get_by_index_tail() to use for clk_get_by_index()

Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-09 00:44:13 +05:30
Jagan Teki
b24f9057e8 serial: sifive: Change include order
Like clk_get_by_index, there is requirement for
clk_get_by_index_nodev. In this case to make common
code functionalities for dev and nodev, clk_get_by_index
is trying to get the index of clock by passing ofnode
instead of actual dev like current gpio uclass does.

In these scenarios with current order of include files
the serial_sifive driver is unable to find CONFIG_ENV_SIZE.

In file included from arch/riscv/include/asm/u-boot.h:23:0,
                 from include/dm/of.h:10,
                 from include/dm/ofnode.h:12,
                 from include/clk.h:11,
                 from drivers/serial/serial_sifive.c:6:
include/environment.h:145:19: error: 'CONFIG_ENV_SIZE'
undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'?
 #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)

So, fix consists of changing the order of include files
in serial_sifive.c to include first common.h file.

Cc: Anup Patel <Anup.Patel@wdc.com>
Cc: Rick Chen <rick@andestech.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-09 00:44:08 +05:30
Jagan Teki
db2f696147 clk: sifive: fu540-prci: Change include order
Like clk_get_by_index, there is requirement for
clk_get_by_index_nodev. In this case to make common
code functionalities for dev and nodev, clk_get_by_index
is trying to get the index of clock by passing ofnode
instead of actual dev like current gpio uclass does.

In these scenarios with current order of include files
the fu540-prci driver is unable to find CONFIG_ENV_SIZE.

In file included from arch/riscv/include/asm/u-boot.h:23:0,
                 from include/dm/of.h:10,
                 from include/dm/ofnode.h:12,
                 from include/clk.h:11,
                 from include/clk-uclass.h:13,
                 from drivers/clk/sifive/fu540-prci.c:32:
include/environment.h:145:19: error: 'CONFIG_ENV_SIZE'
undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'?
 #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)

So, fix consists of changing the order of include files
in fu540-prci.c to include first common.h file.

Cc: Anup Patel <Anup.Patel@wdc.com>
Cc: Rick Chen <rick@andestech.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-09 00:43:59 +05:30
Jagan Teki
0cbee8544b spi: atcspi200: Change include order
Like clk_get_by_index, there is requirement for
clk_get_by_index_nodev. In this case to make common
code functionalities for dev and nodev, clk_get_by_index
is trying to get the index of clock by passing ofnode
instead of actual dev like current gpio uclass does.

In these scenarios with current order of include files
the atcspi200_spi driver is unable to find CONFIG_ENV_SIZE.

In file included from arch/nds32/include/asm/u-boot.h:24,
                 from include/dm/of.h:10,
                 from include/dm/ofnode.h:12,
                 from include/clk.h:11,
                 from drivers/spi/atcspi200_spi.c:9:
include/environment.h:145:19: error: 'CONFIG_ENV_SIZE'
undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'?
 #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)

So, fix consists of changing the order of include files
in atcspi200_spi.c to include first common.h file.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-09 00:42:55 +05:30
Tom Rini
8c66fb88e3 Merge git://git.denx.de/u-boot-x86
- Allow x86 boards to use TPL, SPL and U-Boot proper
- Update sysreset x86 driver to utilize ACPI registers to do power off
- Add a new chromebook_samus_tpl board for TPL support
- Several minor changes in binman tool
2019-05-08 09:20:19 -04:00
Tom Rini
d4c352138c Pull request for UEFI sub-system for v2019.07-rc2 (2)
Fix a bunch of errors in the UEFI sub-system:
 
 * implement missing UnloadImage(),
 * implement missing RegisterProtocolNotify(),
 * unload images in Exit(),
 * parameter checks.
 
 Provide a unit test for UnloadImage().
 Remove a redundant function for unit tests.
 Clean up the UEFI sub-system initialization
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAlzSbVcACgkQxIHbvCwF
 GsTU5g/+Neyv0zcVdtqutCP3/GjPnDfGTkQBXGh8nXZW+57Ld4lhEYgNV6wQXcIE
 VSfUe6KQoTYDsfMRliT+ACytP2y70ZlVMR+qFsA9VX+TummeojWrJ892yj1eIu8R
 GBj+aEul5kBwegW+ZEuFogXC7UI6tVcrsQsTrypyjWyz1An8CxaOPwfntnJ2Ln8I
 lJZ9PZX5r62Sj5i72xcq5c6nxKzSnW0LAKLJTpTBpAAksdz0AAb3blwEnkFZiF+6
 U44901/qBo7CORnkgwhoR+fK0HAecEaYHC98oCFQ0ARRKTaRvbG2U070V016nUK+
 IY/6Ni43fZRKrb05p/OaB19y7HvhBDMH+XmY2DlNv5r5n/ZKRYxFcLDM4RUu/G7h
 q21h53DutZg/+DVif3UBGlUhLOh4lvw9n4TwEfF3a/ujQasL2IUGM7jMaq5h1Kbb
 NzyN1UCeQ5to80uh80FTXf8j5yk1zbRrOnTUdvMpgFLxIHuHThkjpdnjBvxBEiUy
 5RVjhuMMtZ7cOnOvoUNhVX7+xJv4ig8+SEJd6VU3p3a/5Cji5mbufUQDmRy4NX++
 E+2w+uqO998A7HaYJVHCDBT8SdZ1wg2hkxieN+4wrTGhZzu/2/p/93A2JMWQegC5
 jJDsXEPJWembUpEoKevad6VbtW30USn5wHMk1vA/rPeccYvl1EM=
 =4a34
 -----END PGP SIGNATURE-----

Merge tag 'efi-2019-07-rc2-2' of git://git.denx.de/u-boot-efi

Pull request for UEFI sub-system for v2019.07-rc2 (2)

Fix a bunch of errors in the UEFI sub-system:

* implement missing UnloadImage(),
* implement missing RegisterProtocolNotify(),
* unload images in Exit(),
* parameter checks.

Provide a unit test for UnloadImage().
Remove a redundant function for unit tests.
Clean up the UEFI sub-system initialization
2019-05-08 09:20:04 -04:00
Jagan Teki
d364e6bdd7 rockchip: dts: rk3399: Sync rk3399-nanopi4.dtsi from Linux
Sync rk3399-nanopi4.dtsi from Linux 5.1-rc2 tag.

Linux commit details about the rk3399-nanopi4.dtsi sync:
"arm64: dts: rockchip: Add nanopi4 bluetooth"
(sha1: 3e2f0bb72be36aa6c14ee7f11ac4dd8014801030)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:13 +08:00
Jagan Teki
2666bd42c6 arm: rockchip: rk3399: Move common configs in Kconfig
Few SPL and U-Boot proper configs are common to all rk3399 target
defconfigs, move them and select it from platform kconfig.

Moved configs:
-  SPL_ATF
-  SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
-  SPL_LOAD_FIT
-  SPL_CLK if SPL
-  SPL_PINCTRL if SPL
-  SPL_RAM if SPL
-  SPL_REGMAP if SPL
-  SPL_SYSCON if SPL
-  CLK
-  FIT
-  PINCTRL
-  RAM
-  REGMAP
-  SYSCON
-  DM_PMIC
-  DM_REGULATOR_FIXED

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:13 +08:00
Jagan Teki
695dca9a47 Kconfig: Add default SPL_FIT_GENERATOR for rockchip
Add default SPL_FIT_GENERATOR py script for rockchip platforms if
specific target enabled SPL_LOAD_FIT.

So, this would help get rid of explicitly mentioning the default
SPL FIT generator in defconfigs. however some targets, like puma_rk3399
still require their own FIT generator so in those cases the default will
override with defconfig defined generator.

Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:13 +08:00
Jagan Teki
e0bca2821f rockchip: dts: rk3399: Sync pwm2_pin_pull_down from Linux 5.1-rc2
To make successful build with dts(i) files syncing from Linux 5.1-rc2
the rk3399.dtsi would require pwm2_pin_pull_down.

So, sync the pwm2_pin_pull_down node from Linux 5.1-rc2.  Since this
node is strictly not part of any commit alone, I have mentioned
Linux 5.1-rc2 tag for future reference of where would this sync
coming from.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:13 +08:00
Jagan Teki
0d31044eb6 rockchip: rk3399: orangepi: Add SPL_TEXT_BASE
CONFIG_SPL_TEXT_BASE was available in configs/rk3399_common.h
when the OrangePI rk3399 board supported during first
version patch.

But, later below change which move this config into Kconfig and
same has been merged in mainline tree.
"configs: move CONFIG_SPL_TEXT_BASE to Kconfig"
(sha1: f89d6133ee)

Unfortunately, the maintainer applied the initial version patch,
instead of looking for next version changes.

Fix it by adding SPL_TEXT_BASE in orangepi-rk3399 defconfig.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:13 +08:00
Jagan Teki
90430fa895 arm64: rockchip: dts: rk3399: Use rk3399-u-boot.dtsi
Now we have
- board specific -u-boot.dtsi files for board specific u-boot
  dts changes.
- soc specific rk3399-u-boot.dtsi for soc specific u-boot
  dts changes.

So, include the rk3399-u-boot-dtsi on respective board -u-boot.dtsi
and drop the properties which are globally available in rk3399-u-boot.dtsi

Right now rk3399-u-boot.dtsi has sdmmc, spi1 u-boot,dm-pre-reloc
property and more properties and nodes can be move further based
on the requirements.

This would fix, the -u-boot.dtsi inclusion for evb, firefly, puma
boards that was accidentally merged on below commit.
"rockchip: dts: rk3399: Create initial rk3399-u-boot.dtsi"
(sha1: e05b4a4fa8)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:13 +08:00
Jagan Teki
b5f88913a6 rockchip: dts: rk3399-u-boot: Add u-boot, dm-pre-reloc for spi1
Add u-boot,dm-pre-reloc property for spi1, so-that the
subsequent rk3399 boards which boot from SPI.

This help to separate the u-boot specific properties away
from base dts files so-that the Linux sync become easy and
meaningful.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:13 +08:00
Jagan Teki
ddf49cbf35 arm64: rockchip: dts: rk3399: Add board -u-boot.dtsi files
Devicetree files in RK3399 platform is synced from Linux, like other
platforms does. Apart from these u-boot in rk3399 would also require
some u-boot specific node like dmc.

dmc node has big chunk of DDR timing parameters which are specific
to specific board, and maintained with rk3399-sdram*.dtsi.

So, create board specific -u-boot.dtsi files and move these sdram dtsi
files accordingly. This would help of maintain u-boot specific changes
separately without touching Linux dts(i) files which indeed easy for
syncing from Linux between releases.

These board specific -u-boot.dtsi can be extendible to add more u-boot
specific nodes or properties in future.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:13 +08:00
Jagan Teki
82d08de9c5 dts: Makefile: Build rockchip dtbs based on SoC types
- Sometimes u-boot specific dtsi files are included
  automatically which would build for entire rockchip SoC,
  even-though the respective dtsi should used it for specific
  family of rockchip SoC.
- Sometimes u-boot specific dts nodes or properties can use
  config macros from respective rockchip family include/configs
  files, example CONFIG_SPL_PAD_TO.

So, it's better to compile the dtbs based on the respective
rockchip family types rather than rockchip itself to avoid
compilation issues.

This patch organize the existing dtb's based on the rockchip
family types.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:13 +08:00
David Wu
79d16e4540 pinctrl: rockchip: Also move common set_schmitter func into per Soc file
Only some Soc need Schmitter feature, so move the
implementation into their own files.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
David Wu
623aca8830 pinctrl: rockchip: Clean the unused type and label
As the mux/pull/drive feature implement at own file,
the type and label are not necessary.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
David Wu
69a38f81bb pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' pull
RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding
bits, need to read before write the register.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
David Wu
743a77373b pinctrl: rockchip: Split the common set_pull() func into per Soc
As the common set_mux func(), implement the feature at the own file
for each Soc.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
David Wu
956362c84b pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' drive strength
RK3288 pmu_gpio0 drive strength setting have no higher 16 writing
corresponding bits, need to read before write the register.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
David Wu
625ab11fda pinctrl: rockchip: Split the common set_drive() func into per Soc
As the common set_mux func(), implement the feature at the own file
for each Soc.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
David Wu
cd8f00ce08 pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' iomux
RK3288 pmu_gpio0 iomux setting have no higher 16 writing corresponding
bits, need to read before write the register.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
David Wu
54e75702c4 pinctrl: rockchip: Split the common set_mux() into per Soc
Such as rk3288's pins of pmu_gpio0 are a special feature, which have no
higher 16 writing corresponding bits, use common set_mux() func would
introduce more code, so implement their set_mux() in each Soc's own
file to reduce the size of code.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
David Wu
8541beb86d pinctrl: rockchip: Remove redundant spaces
Some files have the redundant spaces, remove them.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
David Wu
0a5cc3cac9 pinctrl: rockchip: Add pull-pin-default param and remove unused param
Some Socs use the pull-pin-default config param, need to add it.
And input-enable/disable config params are not necessary, remove it.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
cc325e4bb6 Revert "pinctrl: rockchip: Add 32bit writing function for rk3288 gpio0 pinctrl"
This reverts commit 502980914b.
This is a superseded version, revert this to apply new patch set.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Simon Glass
ec107f04b6 rockchip: chromebook_minnie: Enable sound
Enable sound for this board, which has the same codec as jerry.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
bdc0008011 rockchip: rk3399: update defconfig for TPL
The SPL is now running at SDRAM, and 0x10000 is used by BL31,
and the ARM SPL do not support relocate now, we need reserved
0x50000 so that it won't overwrite the code when we load the
bl31 to target space.
We should remove this after we enable the relocate feature.

The SPL need malloc 0x9000 for MMC as buffer used for transfer
data to IRAM(The EMMC DMA can not transfer data to IRAM directly).

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
82763349a2 rockchip: ram: rk3399: update for TPL
Init the ddr sdram in TPL instead of SPL, update the code.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
6bbf5e1a94 rockchip: rk3399: add tpl support
Rockchip platform suppose to use TPL(run in SRAM) as dram init and
SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be
limited by SRAM size.
This patch add rk3399-board-tpl.c and its common configs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
3cbec0ad09 rockchip: add u-boot-tpl-v8.lds
We don't have both sram and sdram in TPL, so update from:
arch/arm/cpu/armv8/u-boot-spl.lds

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-08 17:34:12 +08:00
Kever Yang
615e9b3cce rockchip: px5: add timer0 dts node as tick timer
Let's use rockchip timer before stimer patches can be merged.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
6459e7f588 rockchip: rk3368: remove uart iomux init in SPL
The iomux should have been set in board_debug_uart_init(),
do not set in board_init_f(), remove it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
99a1a5b195 rockchip: dmc: rk3368: update rank number for evb-px5
evb-px5 has only 1 CS, update for it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
6b780e441b rockchip: boot0: update CONFIG_ROCKCHIP_SPL_RESERVE_IRAM for SPL only
The CONFIG_ROCKCHIP_SPL_RESERVE_IRAM is for SPL only, add
condition to limit it not affect TPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
259afb1692 rockchip: px5: update defconfig for TPL/SPL
Add options to support TPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
cd193462ee rockchip: px5: update SPL size for spl/tpl
Use larger space for load bl31 in SPL

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
4d9dd40d68 rockchip: px5 update dts for spl/tpl
TPL need dmc to init ddr sdram, and emmc, boot-order.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
579a168466 rockchip: rk3368: support UART2/4 in board_debug_uart_init()
evb-rk3368 is using UART2 and PX5 evb is using UART4

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
a5fd9a7e1e rockchip: evb-rk322x: update defconfig with tpl and optee support
Enable all the options for TPL/SPL and OPTEE.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
7c2a754235 rockchip: evb-rk3229: add README file for OP-TEE support
Detail of step by step to bring up the board with OP-TEE support.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
26f3814e02 rockchip: evb-rk3229: remove unnecessary defines
Prefer to use default setting like other SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
d55dbfed16 rockchip: rk322x: dts: enable uart2 for SPL/TPL
When we use DM_SERIAL for serial driver, we need enable the
dts node for the debug console.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
09259fce1e sysreset: enable driver support in SPL/TPL
SPL/TPL also need use sysreset for some feature like panic callback.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
c34643e0db rockchip: rk322x: add tpl support
Move original spl to tpl, and add spl to load next stage firmware,
adapt all the address and option for them.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
5793e8c271 rockchip: clk: rk322x: fix assert clock value
BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
e4d0d61275 rockchip: rk322x: add CLK_EMMC_SAMPLE clock support
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
a0a0d04f32 arm: add a separate stack for TPL
TPL stack may different from SPL and sys stack, add support for
separate one when the board defines it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00