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https://github.com/brain-hackers/u-boot-brain
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rockchip: rk3399: add tpl support
Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang
parent
3cbec0ad09
commit
6bbf5e1a94
@ -154,12 +154,28 @@ config ROCKCHIP_RK3399
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bool "Support Rockchip RK3399"
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select ARM64
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select SUPPORT_SPL
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select SUPPORT_TPL
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select SPL
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select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
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select TPL_NEEDS_SEPARATE_STACK if TPL
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select SPL_SEPARATE_BSS
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select SPL_SERIAL_SUPPORT
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select SPL_DRIVERS_MISC_SUPPORT
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select BOARD_LATE_INIT
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select ROCKCHIP_BROM_HELPER
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imply TPL_SERIAL_SUPPORT
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imply TPL_LIBCOMMON_SUPPORT
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imply TPL_LIBGENERIC_SUPPORT
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imply TPL_SYS_MALLOC_SIMPLE
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imply TPL_BOOTROM_SUPPORT
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imply TPL_DRIVERS_MISC_SUPPORT
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imply TPL_OF_CONTROL
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imply TPL_DM
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imply TPL_REGMAP
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imply TPL_SYSCON
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imply TPL_RAM
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imply TPL_CLK
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imply TPL_TINY_MEMSET
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help
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The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
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and quad-core Cortex-A53.
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@ -168,6 +184,22 @@ config ROCKCHIP_RK3399
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and video codec support. Peripherals include Gigabit Ethernet,
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USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
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if ROCKCHIP_RK3399
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config TPL_LDSCRIPT
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default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
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config TPL_TEXT_BASE
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default 0xff8c2000
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config TPL_MAX_SIZE
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default 188416
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config TPL_STACK
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default 0xff8effff
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endif
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config ROCKCHIP_RV1108
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bool "Support Rockchip RV1108"
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select CPU_V7A
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@ -195,7 +227,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM
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config TPL_ROCKCHIP_BACK_TO_BROM
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bool "TPL returns to bootrom"
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default y if ROCKCHIP_RK3368
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default y
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select ROCKCHIP_BROM_HELPER
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depends on TPL
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help
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@ -12,6 +12,7 @@ obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
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obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o
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obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
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obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o
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obj-tpl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-tpl.o
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obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
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obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
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84
arch/arm/mach-rockchip/rk3399-board-tpl.c
Normal file
84
arch/arm/mach-rockchip/rk3399-board-tpl.c
Normal file
@ -0,0 +1,84 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <ram.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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#define TIMER_CHN10_BASE 0xff8680a0
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#define TIMER_END_COUNT_L 0x00
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#define TIMER_END_COUNT_H 0x04
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#define TIMER_INIT_COUNT_L 0x10
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#define TIMER_INIT_COUNT_H 0x14
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#define TIMER_CONTROL_REG 0x1c
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#define TIMER_EN 0x1
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#define TIMER_FMODE (0 << 1)
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#define TIMER_RMODE (1 << 1)
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void secure_timer_init(void)
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{
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writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
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writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
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writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
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writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
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writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
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}
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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int ret;
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#ifdef CONFIG_DEBUG_UART
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debug_uart_init();
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/*
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* Debug UART can be used from here if required:
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*
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* debug_uart_init();
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* printch('a');
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* printhex8(0x1234);
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* printascii("string");
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*/
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printascii("U-Boot TPL board init\n");
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#endif
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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secure_timer_init();
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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pr_err("DRAM init failed: %d\n", ret);
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return;
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}
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}
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void board_return_to_bootrom(void)
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{
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back_to_bootrom(BROM_BOOT_NEXTSTAGE);
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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@ -18,11 +18,19 @@
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#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
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#define CONFIG_SYS_LOAD_ADDR 0x00800800
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT)
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#define CONFIG_SPL_STACK 0x00400000
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#define CONFIG_SPL_MAX_SIZE 0x100000
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#define CONFIG_SPL_BSS_START_ADDR 0x00400000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
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#else
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#define CONFIG_SPL_STACK 0xff8effff
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#define CONFIG_SPL_MAX_SIZE 0x30000 - 0x2000
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/* BSS setup */
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#define CONFIG_SPL_BSS_START_ADDR 0xff8e0000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
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#endif
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
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