Add support of loading image, binary for MMC and SPI during SPL boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
SPI driver perform its operation(read/write) on 64KB buffer chunk for data
greater than 64KB. This buffer chunk is allocated from system heap.
During SPL boot, 768KB of data is read from SPI flash.
Here, heap size may not be sufficient enough to full-fill 64KB buffer
requirement of SPI driver. So break down u-boot read operation at 8KB of chunk.
Also, fix a warning i.e. "unused variable buf" during CONFIG_FSL_CORENET
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The commit 6af8dc3ebc broke support for
S25FL032P and S25FL064P by carelessly removing the code handling special
page size for these two SPI NOR flashes and unifying the code under the
assumption that Extended JEDEC ID of 0x4d00 always implies 512b page size.
Add special case handling for these two SPI NOR flashes.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Squash the malloc()+memset() combo in favor of calloc().
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Marek Vasut <marex@denx.de>
Squash the malloc()+memset() combo in favor of calloc().
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Both of these chips have 256kB big sectors, thus the _256K suffix,
compared to their _64K counterparts, which have 64kB sectors. Also,
they have four times less sectors than their _64K counterparts.
Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Remove the flag SECT_4K for device N25Q128 as the 4K-byte
sub sector erase granularity is available only for top/bottom
8 sectors in some of the N25Q128 chips.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This config will use for defining greater than single flash support.
currently - DUAL_STACKED and DUAL_PARALLEL.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch added support for accessing dual memories in
parallel connection with single chipselect line from controller.
For more info - see doc/SPI/README.dual-flash
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch added support for accessing dual memories in
stacked connection with single chipselect line from controller.
For more info - see doc/SPI/README.dual-flash
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
QEB code comprises of couple of flash register read/write operations,
this patch moved flash register operations on to sf_op
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added macronix flash quad read/write commands support and
it's up to the respective controller driver usecase to
configure the respective commands by defining SPI RX/TX
operation modes from include/spi.h on the driver.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch adds set QEB support for macronix flash devices
which are trying to program/read quad operations.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Moved the flash params table from sf_probe.c and
placed on to sf_params.c, hence flash params file will
alter based on new addons.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch enabled RD_FULL and WR_QPP for supported flashes
in micron, winbond and spansion.
Remaining parts will be add in future patches.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch provides support to set the quad enable bit on flash.
quad enable bit needs to set before performing any quad IO
operations on respective SPI flashes.
Currently added set quad enable bit for winbond and spansion flash
devices. stmicro flash doesn't require to set as qeb is volatile.
remaining flash devices support will add in future patches.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch provides support to program a flash config register.
Configuration register contains the control bits used to configure
the different configurations and security features of a device.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch add quad commands support like
- QUAD_PAGE_PROGRAM => for write program
- QUAD_OUTPUT_FAST ->> for read program
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Current sf uses FAST_READ command, this patch adds support to
use the different/extended read command.
This implementation will determine the fastest command by taking
the supported commands from the flash and the controller, controller
is always been a priority.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
claim spi bus while doing memory copy, this will set up
the spi controller device control register before doing
a memory read.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Yebio Mesfin <ymesfin@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Add support for Macronix MX25L2006E SPI flash.
Signed-off-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
All other hex values in sf_probe.c are in lower case so we should
fix this one too.
Signed-off-by: Luka Perkov <luka@openwrt.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
This adds a SPI flash driver which simulates SPI flash clients.
Currently supports the bare min that U-Boot requires: you can
probe, read, erase, and write. Should be easy to extend to make
it behave more exactly like a real SPI flash, but this is good
enough to merge now.
sjg@chromium.org added a README and tidied up code a little.
Added a required map_sysmem() for sandbox.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This allows us to put the SPI flash chip inside the SPI interface node,
with U-Boot finding the correct bus and chip select automatically.
Signed-off-by: Simon Glass <sjg@chromium.org>
Existing eSPI SPL framework assumes booting from spi-image
with boot_format header which contains final u-boot Image
offset and size. No such header is present in case of
corenet devices like T1040 as corenet deivces use PBI-RCW
based intialization.
So, for corenet deives, SPL bootloader use values provided
at compilation time. These values can be defined in board
specific config file.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
As the spi flash transfer to multiple parts, it is forgot to add
Atmel AT25DF321 spi flash support, which broken several Atmel EK
boards which this chip. So, add it
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Added GPL-2.0+ SPDX-License-Identifier for missed sf
source files.
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Bo Shen <voice.shen@atmel.com>
There is no page_size for ramtron flashes,
so just print the detected flash and it's size.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Qspi controller can have a memory mapped port which can be used for
data read. Added support to enable memory mapped port read.
This patch enables the following:
- It enables exchange of memory map address between mtd and qspi
through the introduction of "memory_map" flag.
- Add support to communicate to the driver that memory mapped
transfer is to be started through introduction of new flags like
"SPI_XFER_MEM_MAP" and "SPI_XFER_MEM_MAP_END".
This will enable the spi controller to do memory mapped configurations
if required.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Use flash->page_size arg in print_size() instead of
flash->sector_size while printing detected flas part details.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Now the common probing is handled in spi_flash_probe.c
hence removed the unneeded flash drivers.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Compared to other spi flashes, ramtron has a different
probing and implementation on flash ops, hence moved
ramtron probe code into ramtron driver.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
From Micron, 512MB onwards, flash requires to poll flag status
instead of read status- hence added E_FSR flag on spectific
flash parts.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
SECT_4K, SECT_32K and SECT_64K opeartions are performed to
to specific flash by adding a SECT* flag on respective
spi_flash_params.flag param.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Few of the flashes(Atmel, Macronix and SST) require to
clear BP# bits in flash power ups.
So clear these BP# bits at probe time, so-that the flash
is ready for user operations.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Most of the SST flashes needs to write up using SST_WP, AAI
Word Program, so added a flag param on spi_flash_params table.
SST flashes, which supports SST_WP need to use a WP write
sst_write_wp instead of common flash write.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added AT45DB* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added SST25* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
Added S25FL* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added W25* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added MX25L* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added GD25* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added EN25Q* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added M25P* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Added new spi_flash_probe support, currently added N25Q*
flash part attributes support.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Divided the spi_flash framework into mutiple parts for
- spi_flash.c:
spi flash core file, interaction for spi/qspi driver to
spi_flash framework.
- spi_flash_ops.c
spi flash preffered operations, erase,write and read.
- spi_flash_probe.c
spi flash probing, easy to extend probing functionality.
This change will support to extend the functionality in a
proper manner.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch cleans up license header in these files:
board/freescale/p1022ds/spl.c
drivers/mmc/fsl_esdhc_spl.c
drivers/mtd/spi/fsl_espi_spl.c
Signed-off-by: York Sun <yorksun@freescale.com>
This patch introduces SPL to enable a loader stub that being loaded by
the code from the internal on-chip ROM. It loads the final uboot image
into DDR, then jump to it to begin execution.
The SPL's size is sizeable, the maximum size must not exceed the size of L2
SRAM. It initializes the DDR through SPD code, and copys final uboot image
to DDR. So there are two stage uboot images:
* spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that
ddr spd code can get the interleaving mode setting in env. It loads
final uboot image from offset 96KB.
* final uboot image, size is variable depends on the functions enabled.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Add support for SST25WF080 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
- line over 80 characters
- foo * bar -> foo *bar
- removed unnecessary for single statement blocks.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Move common flash write code into spi_flash_write_common().
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>
Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.
Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and use the poll status code
spi_flash_cmd_wait_ready() itself.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use the existing spi_flash_addr() for 3-byte addressing
cmd filling in write call.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has < 16Mbytes SPI flashes.
It's upto user which has provision to use the bank addr code for
flashes which has > 16Mbytes.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch updated the spi_flash read func to support all
sizes of flashes using bank reg addr facility.
The same support has been added in below patch for erase/write
spi_flash functions:
"sf: Support all sizes of flashes using bank addr reg facility"
(sha1: c956f600cbb0943d0afe1004cdb503f4fcd8f415)
With these new updates on sf framework, the flashes which has < 16MB
are not effected as per as performance is concern and but the
u-boot.bin size incrased ~460 bytes.
sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s
- W25Q128BV
16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s
- S25FL256S_64K
16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s
sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s
- W25Q128BV
16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s
- S25FL256S_64K
16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Updated the spi_flash framework to handle all sizes of flashes
using bank/extd addr reg facility
The current implementation in spi_flash supports 3-byte address mode
due to this up to 16Mbytes amount of flash is able to access for those
flashes which has an actual size of > 16MB.
As most of the flashes introduces a bank/extd address registers
for accessing the flashes in 16Mbytes of banks if the flash size
is > 16Mbytes, this new scheme will add the bank selection feature
for performing write/erase operations on all flashes.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.
bank read only valid for flashes which has > 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.
Suppose if the flash has 64Mbytes size consists of 4 banks like
bank0, bank1, bank2 and bank3.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bank/Extended addr commands are specific to particular
flash vendor so discover them based on the idocode0.
Assign the discovered bank commands to spi_flash members
so-that the bank read/write will use their specific operations.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This patch provides support to program a flash bank address
register.
extended/bank address register contains an information to access
the 4th byte addressing in 3-byte address mode.
reff' the spec for more details about bank addr register
in Page-63, Table 8.16
http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
