sf: Add bank addr code in CONFIG_SPI_FLASH_BAR
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the size for existing boards which has < 16Mbytes SPI flashes. It's upto user which has provision to use the bank addr code for flashes which has > 16Mbytes. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Jagannadha Sutradharudu Teki
parent
fc207ee4db
commit
1dcd6d0381
5
README
5
README
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@ -2509,6 +2509,11 @@ CBFS (Coreboot Filesystem) support
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Define this option to include a destructive SPI flash
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test ('sf test').
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CONFIG_SPI_FLASH_BAR Ban/Extended Addr Reg
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Define this option to use the Bank addr/Extended addr
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support on SPI flashes which has size > 16Mbytes.
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- SystemACE Support:
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CONFIG_SYSTEMACE
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@ -74,7 +74,7 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
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unsigned long page_addr, byte_addr, page_size;
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size_t chunk_len, actual;
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int ret;
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u8 cmd[4], bank_sel;
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u8 cmd[4];
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page_size = flash->page_size;
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@ -86,6 +86,9 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
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cmd[0] = CMD_PAGE_PROGRAM;
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for (actual = 0; actual < len; actual += chunk_len) {
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#ifdef CONFIG_SPI_FLASH_BAR
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u8 bank_sel;
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bank_sel = offset / SPI_FLASH_16MB_BOUN;
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ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
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@ -93,7 +96,7 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
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debug("SF: fail to set bank%d\n", bank_sel);
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return ret;
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}
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#endif
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page_addr = offset / page_size;
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byte_addr = offset % page_size;
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chunk_len = min(len - actual, page_size - byte_addr);
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@ -148,7 +151,7 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
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int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
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size_t len, void *data)
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{
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u8 cmd[5], bank_sel;
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u8 cmd[5], bank_sel = 0;
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u32 remain_len, read_len;
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int ret = -1;
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@ -162,6 +165,7 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
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cmd[4] = 0x00;
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while (len) {
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#ifdef CONFIG_SPI_FLASH_BAR
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bank_sel = offset / SPI_FLASH_16MB_BOUN;
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ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
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@ -169,7 +173,7 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
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debug("SF: fail to set bank%d\n", bank_sel);
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return ret;
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}
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#endif
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remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset);
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if (len < remain_len)
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read_len = len;
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@ -240,7 +244,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
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{
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u32 erase_size;
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int ret;
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u8 cmd[4], bank_sel;
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u8 cmd[4];
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erase_size = flash->sector_size;
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if (offset % erase_size || len % erase_size) {
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@ -260,6 +264,9 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
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cmd[0] = CMD_ERASE_64K;
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while (len) {
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#ifdef CONFIG_SPI_FLASH_BAR
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u8 bank_sel;
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bank_sel = offset / SPI_FLASH_16MB_BOUN;
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ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
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@ -267,7 +274,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
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debug("SF: fail to set bank%d\n", bank_sel);
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return ret;
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}
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#endif
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spi_flash_addr(offset, cmd);
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debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
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@ -321,6 +328,7 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
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return 0;
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}
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#ifdef CONFIG_SPI_FLASH_BAR
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int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
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{
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u8 cmd;
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@ -389,6 +397,7 @@ int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0)
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return 0;
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}
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#endif
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#ifdef CONFIG_OF_CONTROL
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int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
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@ -534,10 +543,12 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
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goto err_manufacturer_probe;
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}
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#ifdef CONFIG_SPI_FLASH_BAR
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/* Configure the BAR - disover bank cmds and read current bank */
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ret = spi_flash_bank_config(flash, *idp);
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if (ret < 0)
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goto err_manufacturer_probe;
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#endif
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#ifdef CONFIG_OF_CONTROL
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if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
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@ -35,11 +35,13 @@
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#define SPI_FLASH_STMICRO_IDCODE0 0x20
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#define SPI_FLASH_WINBOND_IDCODE0 0xef
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#ifdef CONFIG_SPI_FLASH_BAR
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/* Bank addr access commands */
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#define CMD_BANKADDR_BRWR 0x17
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#define CMD_BANKADDR_BRRD 0x16
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#define CMD_EXTNADDR_WREAR 0xC5
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#define CMD_EXTNADDR_RDEAR 0xC8
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# define CMD_BANKADDR_BRWR 0x17
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# define CMD_BANKADDR_BRRD 0x16
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# define CMD_EXTNADDR_WREAR 0xC5
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# define CMD_EXTNADDR_RDEAR 0xC8
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#endif
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/* Common status */
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#define STATUS_WIP 0x01
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@ -90,11 +92,13 @@ static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
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/* Program the status register. */
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int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
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#ifdef CONFIG_SPI_FLASH_BAR
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/* Program the bank address register */
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int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel);
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/* Configure the BAR - discover the bank cmds */
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int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0);
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#endif
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/*
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* Same as spi_flash_cmd_read() except it also claims/releases the SPI
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@ -38,13 +38,14 @@ struct spi_flash {
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u32 page_size;
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/* Erase (sector) size */
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u32 sector_size;
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#ifdef CONFIG_SPI_FLASH_BAR
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/* Bank read cmd */
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u8 bank_read_cmd;
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/* Bank write cmd */
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u8 bank_write_cmd;
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/* Current flash bank */
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u8 bank_curr;
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#endif
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void *memory_map; /* Address of read-only SPI flash access */
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int (*read)(struct spi_flash *flash, u32 offset,
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size_t len, void *buf);
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