U-Boot widely uses error() as a bit noisier variant of printf().
This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:
# define __compiletime_error(message) __attribute__((error(message)))
This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux. (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)
Let's convert error() into now treewide-available pr_err().
Done with the help of Coccinelle, excluing tools/ directory.
The semantic patch I used is as follows:
// <smpl>
@@@@
-error
+pr_err
(...)
// </smpl>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com>
When we import code from Linux, with regular re-sync planned, we want
to use printk() and pr_*(). U-Boot does not support them in a clean
way. So, people end up with local macros, or compat headers here and
there, then we occasionally see build errors of definition conflicts.
We have include/linux/compat.h, but putting all sorts of unrelated
things into a single header is just a temporal workaround. Hence this
patch, to find the best home for all printk variants. If you want to
use printk() and friends, please include <linux/printk.h>. This header
is self-contained, and pulls in only a few headers.
When I was testing this clean-up, I noticed the image size exceeded
its platform limit on some boards. This is because all pr_*() that
were previously defined as no-op in include/linux/mtd/mtd.h (unless
CONFIG_MTD_DEBUG is set), are now enabled.
To make such boards happy, this commit also implements CONFIG_LOGLEVEL.
The concept is similar to the kernel parameter "loglevel". (Actually,
the Kconfig help message was taken from kernel-paremeter.txt of Linux)
Messages with a loglevel smaller than console loglevel will be printed.
The difference is the loglevel is build-time determined. To save the
image size, lower priority pr_*() are compiled out. I set the default
of CONFIG_LOGLEVEL to 6, i.e. pr_notice and higher priority messages
are compiled in.
I adjusted CONFIG_LOGLEVEL to avoid build error for some boards.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Add in SPL_LOGLEVEL that is the same as LOGLEVEL]
Signed-off-by: Tom Rini <trini@konsulko.com>
All the new SoCs from Allwinner since the A33 have had the phy_ctl offset
at 0x410 instead of 0x404 that was used on the previous SoCs.
Instead of adding more and more special cases as the number of SoCs grow,
let's invert the test to have 0x410 by default, and the (hopefully) fixed
number of old SoCs being the exception.
Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Suggested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Banana Pi M1 Plus is an open-source single-board computer
that adds more connectivity to the classic board using
Allwinner A20 SOC.
Bananapi M1-Plus features:
- A20 Dual-core 1.0GHz
- 1 GB DDR3 SDRAM
- MicroSD
- 10/100/1000 Ethernet RJ45
- WiFi b/g/n
- 5V DC Micro USB power-supply
For dts file,
Sync with Linux commit f92ca09("Merge branch 'akpm/master'").
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The upstream (Linux) device tree file for the Bananapi M3 follows the
convention of using the well known brand name, instead of the vendor
name, for naming. The file was recently added to upstream in commit
359b5a1e1c2d ("ARM: sun8i: a83t: Add device tree for Sinovoip Bananapi
BPI-M3")
Rename the device tree file in U-boot to match.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
USB_GADGET will fail to compile if USB_MUSB_GADGET is not defined. Make
sure we have that condition right.
Fixes: e0ea88042d51 ("sunxi: Imply USB_ETHER")
Suggested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
U-Boot itself might need to identify the boot device, for example to be
able to tell where to load the kernel from when several options are
possible.
Move the logic of spl_boot_device to a function that is compiled both for
the SPL and the main binary.
Tested-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
From rev.J A20-OLinuXino-MICRO has eMMC option. For now this is
only 4GB, but in the future size may increase.
The dts file is the same from mainline kernel.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
GPT is pretty common these days and can be useful for things like fastboot.
Add a platform imply, so that users can still opt out if they wish so.
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The kernel DT of the SinA33 has evolved quite a bit. Make sure we sync it
and its upstream DTSI to be able to use the OTG. The DTs were taken from
the 4.13 kernel release.
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that we can enable the usb_ether gadget, do it. This will be especially
useful for boards that don't have any ethernet controller, such as the ones
based on the A13 or A33.
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The device model was implemented so far using a hook that needed to be
called from the board support, without DT support and only for the host.
Switch to probing both in peripheral and host mode through the DT.
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Fastboot need a bunch of options to be operating properly, such as the
g_dnl gadget, the fastboot command, and some options that make sense. Since
fastboot is now part of Kconfig, make sure we have them right.
That will also reduce the boilerplate in the defconfigs.
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
A good number of our boards have USB_GADGET enabled. Imply it so that all
the boards can benefit from it, and remove some boilerplate from our
defconfigs.
Reviewed-by: Łukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The g_dnl USB settings for the vendor ID, product ID and manufacturer are
actually common settings that can and should be shared by all the gadgets.
Make them common by renaming them, and convert all the users.
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The setbits/clrbits/clrsetbits macros are used widely across the tree,
let's provide implementation for them in the sandbox.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Convert the sandbox architecture to make use of the new asm-generic/io.h
to provide address mapping functions. As sandbox actually performs
non-identity mapping between physical & virtual addresses we can't
simply make use of the generic mapping functions, but are able to
implement phys_to_virt() & make use of it from map_physmem().
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Convert the powerpc architecture to make use of the new asm-generic/io.h
to provide address mapping functions. As powerpc can actually perform
non-identity mapping between physical & virtual addresses we can't
simply make use of the generic phys_to_virt() & virt_to_phys()
functions. However since map_physmem() already effectively implemented
the same thing as virt_to_phys() we can simply implement virt_to_phys()
instead of map_physmem() & use the generic map_physmem(). We also drop
the no-op unmap_physmem().
This has only been build-tested, feedback from architecture maintainers
is welcome.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Wolfgang Denk <wd@denx.de>
Convert the nios2 architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As nios2 actually performs
non-identity mapping between physical & virtual addresses we can't
simply make use of the generic functions, with the exception of being
able to drop our no-op unmap_physmem() and definitions of unused map
flags.
Feedback from architecture maintainers is welcome.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Thomas Chou <thomas@wytron.com.tw>
Convert the mips architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As mips actually performs
non-identity mapping between physical & virtual addresses we can't
simply make use of the generic functions, with the exception of being
able to drop our no-op unmap_physmem() and definitions of unused map
flags.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Convert the xtensa architecture to make use of the new asm-generic/io.h
to provide address mapping functions. As the generic implementations are
suitable for xtensa this is primarily a matter of moving code.
This has only been build-tested, feedback from architecture maintainers
is welcome.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Convert the x86 architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for x86 this is primarily a matter of moving code.
This has only been build-tested, feedback from architecture maintainers
is welcome.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert the sh architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for sh this is primarily a matter of moving code.
Feedback from architecture maintainers is welcome.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Convert the nds32 architecture to make use of the new asm-generic/io.h
to provide address mapping functions. As the generic implementations are
suitable for nds32 this is primarily a matter of removing code.
Feedback from architecture maintainers is welcome.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Macpaul Lin <macpaul@andestech.com>
Convert the microblaze architecture to make use of the new
asm-generic/io.h to provide address mapping functions. As the generic
implementations are suitable for microblaze this is primarily a matter
of removing code.
Feedback from architecture maintainers is welcome.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Michal Simek <monstr@monstr.eu>
Convert the m68k architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for m68k this is primarily a matter of emoving code.
Feedback from architecture maintainers is welcome.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Huan Wang <alison.wang@freescale.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Acked-by: Angelo Dureghello <angelo@sysam.it>
Tested-by: Angelo Dureghello <angelo@sysam.it>
Convert the arm architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for arm this is primarily a matter of removing code.
This has only been build-tested, feedback from architecture maintainers
is welcome.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert the arc architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for arc this is primarily a matter of removing code.
Feedback from architecture maintainers is welcome.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
With Makefiles testing for $(SPL_TPL_)SYSRESET, we need TPL_SYSRESET
for do_reset() in TPL for Rockchip SoCs.
References: 87c16d4 "drivers: spl: consistently use the $(SPL_TPL_)
macro"
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Falcon mode, is updating DDR dt node configuration through
spl_fixup_fdt() so add appropriate DDR base and size through
dram_init_banksize.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The (Qseven) BIOS_DISABLE signal on the RK3399-Q7 (Puma) keeps the
eMMC and SPI in reset initially and we need to write a GPIO to turn
them on before continuing the boot-up.
This adds the DTS entries for the additional regulator and makes
pinctrl and gpio3 available during SPL. It also adds a hook to the
spl_board_init() to ensure that the regulator gets probed and enabled.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In the general case, we want to continue booting the full U-Boot
(contained in a discoverable FIT image) from the same device the SPL
stage was loaded from. This prepends the 'same-as-spl' specifier to
our configurable boot-order to make this the default behaviour.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To support the new "same-as-spl" specifier in the boot-order on the
RK3399, this implements the chip-specific mapping from the information
obtainable from the BROM to a OF path name.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It is often desirable to configure the spl-boot-order (i.e. the order
that SPL probes devices to find the FIT image containing a full U-Boot)
such that it contains 'the same device the SPL stage was booted from'
early on. To support this, we introduce the 'same-as-spl' specifier
for the spl-boot-order property.
This commit adds:
- documentation for the new board_spl_was_booted_from() function that
individual SoCs/boards should provide, if they can determine where
the SPL was booted from
- implements the new board_spl_was_booted_from() stub function
- adds support for handling the 'same-as-spl' specifier and calling
into the per-SoC/per-board support code.
This also updates the documentation for the 'u-boot,spl-boot-order'
property.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In the expectation that the spl-boot-order code will eventually
gain use outside of mach-rockchip: let's add documentation on the
spl_node_to_boot_device() function, which is likely to become a
publicly exported function.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The Rockchip BROM allows reading where it booted from from SRAM.
This adds the necessary definitions (as received from Kever) for
the location of this information in the RK3399's SRAM and naming
for the constants used.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The later-stage spl_board_init (as opposed to board_init_f) should set
up board-specific details: these differ between the EVB-RK3399 and the
RK3399-Q7 (Puma).
This moves spl_board_init back into the individual boards and removes
the unneeded functionality from Puma.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The boot mode for rk322x is stored in sysreg 0, update it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
add i2c1 and rk805 nodes to support rk805 init setting.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Since the size of SPL can't be exceeded 0x8000 bytes in RK3288,
it is not possible add new SPL features like Falcon mode or etc.
So add TPL stage so-that adding new features to SPL is possible.
- TPL: DRAM init, clocks
- SPL: MMC, falcon, etc
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
configure_l2ctlr will be shared between SPL and TPL so
move them into asm/arch/sys_proto.h
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
L2CTLR read/write functions are common to armv7 so, move
them in to include/asm/armv7.h and use them where ever it need.
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Backed out the change to arch/arm/mach-tegra/cache.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Some of macros definition are not correct, fix them according to TRM.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Instead of directly calling into the back-to-bootrom code, the RK3399
common SPL implementation now uses BOOT_DEVICE_BOOTROM to trigger a
transfer back into the bootrom.
With this factored out, the spl_board_init function can not be
customised for each RK3399 board.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add driver for rk322x to support sdram initialize in SPL.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Enable the Rockchip SARADC driver for all Rockchip SoCs.
Note that the SARADC peripheral is available on all SoCs except the
RK3036 and RK3228. However, as this is a DM-driver, enabling by
default will not cause any function problems (and can always be
changed from defconfig, if size is a concern).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: David Wu <david.wu@rock-chips.com>
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Enable the SARADC for download key pressed detect.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This re-syncs omap3 DTS file with current file from
Linux v4.14-rc1 to ensure a consistent configuration. Upstream
Linux removed the redundant Interrupt-parent property from usbhsohci,
usbhsehci, ssi_port1 and ssi_port2 sub nodes.
Signed-off-by: Karthik Tummala <karthik@techveda.org>
With DM enabled, gpio numbering is assigned based on the
probed order of gpios, irrespective of the gpio base. So enable
all necessary gpios in SPL.
Fixes: edf25d94d55c (“ARM: dts: OMAP5+: Enable gpio in SPL”)
Reported-by: Gou, Hongmei <h-gou@ti.com>
Tested-by: Aparna Balasubramanian <aparnab@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This patch adds support for authentication of both plain
text and encrypted binaries. A new SECDEV package is needed
to enable encryption of binaries by default for AM3x.
The ROM authentication API detects encrypted images at
runtime and automatically decrypts the image if the
signature verification passes.
Addition of encryption on AM3x results in a change in the
image format. On AM4x, AM5x and, on AM3x devices signing
clear test images, the signature is appended to the end of the
binary.
On AM3x, when the SECDEV package is used to create signed
and encrypted images, the signature is added as a header
to the start of the binary. So the binary size calculation
has been updated to reflect this change.
The signing tools and encrypted image format for AM3x
cannot be changed to behave like AM4x and AM5x to
maintain backward compatibility with older Sitara
M-Shield releases.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
With the device tree ported from Linux 4.13, this enables
Driver Model and Device Tree support for the am3517-evm
Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
To keep the DTS and DTSI files clean and in sync with Linux, new
u-boot.dtsi files are added.
There are some spacing issues in the patch, but they appear to be
present in the Linux source files. I'll try to get to fixing them there,
and do a future re-sync at a later date.
Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
On ARCH_OMAP2PLUS platforms we know what the DDR layout is going to be,
and that it is safe to use SPL_STACK_R and provide a default value for
it. select this and re-sync the defconfigs.
Signed-off-by: Tom Rini <trini@konsulko.com>
With DM now enabled with the device tree pulled from Linux, we can
enable DM_I2C in U-Boot.
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Add DM_I2C_COMPAT to da850_am18xxevm to fix warning]
Signed-off-by: Tom Rini <trini@konsulko.com>
Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert the board to support the video driver model, add the device
tree node, and remove the unnecessary code.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
A few small additional items are needed to support DM_SPI and
DM_SERIAL, so those were added to da850-evm-u-boot.dtsi
Signed-off-by: Adam Ford <aford173@gmail.com>
The ClearFog Base boot from UART when setting the DIP switches to 01001.
Unfortunately, the SPL code sometimes fails to detect the UART boot
method at run-time. Add an alternative SAR UART boot value to fix this.
Note that this alternative value is not documented (Armada 38x Hardware
Specifications, Table 48). But experimentations showed it on the
ClearFog Base.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
dram_ecc_scrubbing() had code to skip unused DRAM banks but it would not
work because mvebu_sdram_bs() returns 0 and the code was subtracting 1
before checking the size. Remove the -1 from the bank size and the +1
from the total which will skip unused banks and still calculate the
correct size. Put the -1 where it is needed for scrubbing via the xor
engine.
Reported-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The Armada-38x has 1.8GHz and 2.0GHz variants. Add entries for these
variants to the sar_freq_tab.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Display more information about the current RAM configuration. With these
changes the output on a 88F6820 board is
SoC: MV88F6820-A0 at 1600 MHz
DRAM: 2 GiB (800 MHz, 32-bit, ECC not enabled)
Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
These SoCs are network packet processors (switch chips) with integrated
ARMv7 cores. They share a great deal of commonality with the Armada-XP
CPUs.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This converts the following to Kconfig:
CONFIG_MVNETA
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
The PHY reset GPIOs were missing from the DT, add them.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
As per updated board design, different QSPI flash
is connected on boards, hence change QSPI flash type
from Micron n25q512a device to spansion s25fs512s
device in dts and config.
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
It is not necessary for every SoC to have 2 SATA controller.
So put SATA1, SATA2 code under respective defines.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch provides default implementations of the two functions
set_uart_mux_conf and set_mux_conf_regs. Hence boards not using
them do not need to provide their distinct empty definitions.
Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>
This patch adds support for stm32h7 soc family, stm32h743
discovery and evaluation boards.
For more information about STM32H7 series, please visit:
http://www.st.com/en/microcontrollers/stm32h7-series.html
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adapts stm32h743 disco and eval dts files to match
with U-boot requirements or add features wich are not yet
upstreamed on kernel side :
_ Add RCC clock driver node and update all clocks phandle
accordingly.
By default, on kernel side, all clocks was temporarly
configured as a phandle to timer_clk waiting for a RCC
clock driver to be available.
On U-boot side, we now have a dedicated RCC clock driver, we
can configured all clocks as phandle to this driver.
All this binding update will be available soon in a kernel tag,
as all the bindings have been acked by Rob Herring [1].
[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html
_ Align STM32H7 serial compatible string with the one which will be
available in next kernel tag. The bindings has been acked by
Rob Herring [2].
This compatible string will be usefull to add stm32h7 specific
feature for this serial driver.
[2] https://lkml.org/lkml/2017/7/17/739
_ Add gpio compatible and aliases for stm32h743
_ Add FMC sdram node with associated new bindings value to
manage second bank (ie bank 1).
_ Add missing HSI and CSI oscillators nodes needed
by STM32H7 RCC clock driver.
Clock sources could be:
_ HSE (High Speed External)
_ HSI (High Speed Internal)
_ CSI (Low Power Internal)
These clocks can be used as clocksource in some configuration.
By default, HSE is selected as clock source.
_ Set HSE to 25Mhz for stm32h743i-disco and eval board
By default, the external oscillator frequency is defined at
25 Mhz in SoC stm32h743.dtsi file.
It has been set at 125 Mhz in kernel DT temporarly waiting for
RCC clock driver becomes available.
As in U-boot we got a RCC clock driver, the real value of HSE
clock can be used.
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This file is imported from linux kernel v4.13
Add device tree support for STM32H743 evaluation board.
This board offers :
_ STM32H743XIH6 microcontroller with 2 Mbytes of
Flash memory and 1 Mbyte of RAM in TFBGA240+25 package
_ 5.7” 640x480 TFT color LCD with touch screen
_ Ethernet compliant with IEEE-802.3-2002
_ USB OTG HS and FS
_ I2 C compatible serial interface
_ RTC with rechargeable backup battery
_ SAI Audio DAC
_ ST-MEMS digital microphones
_ 8-Gbyte (or more) SDIO3.0 interface microSD™ card
_ 8Mx32bit SDRAM, 1Mx16bit SRAM and 8Mx16bit NOR Flash
_ 1-Gbit Twin Quad-SPI NOR Flash
_ Potentiometer
_ 4 colored user LEDs
_ Reset, wakeup, tamper or key buttons
_ Joystick with 4-direction control and selector
_ Board connectors :
Power jack
3 USB with Micro-AB
RS-232 communications
Ethernet RJ45
FD-CAN compliant connection
Stereo headset jack including analog microphone input
2 audio jacks for external speakers
microSD™ card
JTAG/SWD and ETM trace
_ Expansion connectors:
Extension connectors and memory connectors for daughterboard
or wire-wrap board
_ Flexible power-supply options: ST-LINK USB VBUS or external
sources
_ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
capability: mass storage, virtual COM port and debug port
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
All these files are imported from linux kernel v4.13
Add device tree support for STM32H743 SoC and discovery
board. This board offers :
_ STM32H743XIH6 microcontroller with 2 Mbytes of
Flash memory and 1 Mbyte of RAM in TFBGA240+25 package
_ 5.7” 640x480 TFT color LCD with touch screen
_ Ethernet compliant with IEEE-802.3-2002
_ USB OTG HS
_ I2 C compatible serial interface
_ ST-MEMS digital microphones
_ 8-Gbyte (or more) SDIO3.0 interface microSD™ card
_ 8Mx32bit SDRAM
_ 1-Gbit Twin Quad-SPI NOR Flash
_ Reset, wakeup, or key buttons
_ Joystick with 4-direction control and selector
_ Board connectors :
1 USB with Micro-AB
Ethernet RJ45
Stereo headset jack including analog microphone input
microSD™ card
RCA connector
JTAG/SWD and ETM trace
_ Expansion connectors:
Arduino Uno compatible Connectors
2 x PIO connectors (PMOD and PMOD+)
_ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
capability: mass storage, virtual COM port and debug port
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Update ehci and ohci node's compatible string in order to
use ehci-generic and ohci-generic drivers.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
On STi 96boards, configure by default the micro USB connector
(managed by DWC3 hardware block) in peripheral mode.
This will allow to use fastboot feature.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds the ST glue logic to manage the DWC3 HC
on STiH407 SoC family. It configures the internal glue
logic and syscfg registers.
Part of this code been extracted from kernel.org driver
(drivers/usb/dwc3/dwc3-st.c)
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
reset-names property is needed to use the reset
API for STi sdhci driver.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Instead of having every board file to add its own g_dnl_bind_fixup()
implementation, move it to the common imx6 SPL code.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Łukasz Majewski <lukma@denx.de>
After Simon's patch, the dtoc can work with 64bit address,
so we need to fix reg number for it.
Depend on Simon's patch set:
https://patchwork.ozlabs.org/cover/807266/
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The RK3368 TPL stage always returns to the BootROM, so it has no need
for the eMMC, SD and SPI nodes. This marks those nodes (that should
be included in SPL, but not TPL) as 'u-boot,dm-spl'.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
On the RK3399-Q7, we need to turn on the on-module USB hub before using the
USB host interfaces (only the OTG interface is directly connected to the edge
connector). This drops the deprecated 'rockchip,vbus-gpio' property and uses
a fixed regulator to turn on the USB hub.
References: 26a8b80 "usb: host: xhci-rockchip: use fixed regulator to control vbus"
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds support for Vyasa RK3288 initial board
from Amarula Solutions.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
On the RK3399, we will have either OF_PLATDATA or full OF_CONTROL
enabled: this allows the use of syscon to retrieve the addresses of
GRF and SGRF (except for the early debug UART setup, which runs so
early that the device-model is not initialised).
This removes the hard-coded addresses and goes through syscon to
retrieve the base-addresses of GRF and SGRF. After that, we use
the structure definitions to locate the respective registers.
In addition to this, the inclusion of header files is also cleaned up:
- all headers are included at the beginning (there was a spurious
inclusion of the grf header from within a function)
- all #include statements for unused headers are removed
- the remaining #include statements are sorted (while keeping common.h
included in front)
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
To support bootstage recording, we want to mark our DM timer as the
tick-timer; this triggers the support for 'trying harder' to read the
timer in the Rockchip DM timer driver, even if the device model isn't
ready yet.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Unfortunately, the integrated macphy default is enabled, which will
increase power consuming, if we do not use this PHY. So let's disable
it at first, which will save power consuming. If we really use it, then
enable it in driver level.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
To support fastboot "fastboot reboot-bootloader" cmd.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This patch adds USB OTG/EHCI/OHCI nodes for evb-rv1108 USB ports.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Update these macros to use all upper-case to avoid checkpatch
warnings:
ENET_25MHz,
ENET_50MHz,
ENET_125MHz,
Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
The current mechanism using SCR/GPR registers work well when
the serial downloader boot mode has been selected explicitly
(either via boot mode pins or using bmode command). However,
in case the system entered boot ROM due to unbootable primary
boot devices (e.g. empty eMMC), the SPL fails to detect that
it has been downloaded through serial loader and tries to
continue booting from eMMC:
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
The only known way to reliably detect USB serial downloader
is by checking the USB PHY receiver block power state...
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
This macro allows to detect whether the USB PHY is active. This
is helpful to detect if the boot ROM has previously started the
USB serial downloader.
The idea is taken from the mfgtool support in the NXP U-Boot:
http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/?h=imx_v2016.03_4.1.15_2.0.0_ga&id=a352ed3c5184b95c4c9f7468f5fbb5f43de5e412
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Starting from PXs3, the bit fields of RSTCTRL, CLKCTRL registers
will change every SoC. There is no more point to define bitfields
in the common header file.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The main difference between Pro4 and PXs2/LD6b is the Denali NAND
IP version. This is now distinguished by DT. Merge the two defconfig
files into uniphier_v7_defconfig.
Update the README.uniphier too.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
legacy_hole_base_k and legacy_hole_size_k are defined but
not used.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With bootstage we need access to the timer before driver model is set up.
To handle this, put the required state in global_data and provide a new
function to set up the device, separate from the driver's probe() method.
This will be used by the 'early' timer also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This adds support to Intel Cherry Hill board, a board based on
Intel Braswell SoC. The following devices are validated:
- serial port as the serial console
- on-board Realtek 8169 ethernet controller
- SATA AHCI controller
- EMMC/SDHC controller
- USB 3.0 xHCI controller
- PCIe x1 slot with a graphics card
- ICH SPI controller with an 8MB Macronix SPI flash
- Integrated graphics device as the video console
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
FSP's built-in UPD configuration enables PUNIT power configuration,
but on B0 stepping, this causes CPU hangs in fsp_init(). Disable it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds microcode device tree fragment for Braswell B0 (406C2),
C0 (406C3) and D0 (406C4) stepping SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.
Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
FSP spec 1.1 adds 3 new APIs and their offsets are in the header.
Update the 'fsp hdr' command to show these new entries.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When a VBT is given to an FSP that supports graphics initialization,
the FSP will produce a graphics info HOB that contains all necessary
information for the linear frame buffer of the integrated graphics
device. This adds a DM video driver for it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Now that binman is able to recognize the Video BIOS Table entry,
add such one in the u-boot.dtsi.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds Kconfig options for Video BIOS Table which is normally
required if you are using an Intel FSP firmware that is complaint
with spec 1.1 or later to initialize the integrated graphics device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds a new HOB type for graphics information introduced in FSP
spec 1.1. When graphics capability is included in FSP and enabled,
FSP produces an FSP_GRAPHICS_INFO_HOB as described in the EFI PI
specification which provides information about the graphics mode and
framebuffer.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
FSP spec 1.1 adds one more member to the struct common_buf to
determine the memory size that can be reserved by FSP below "top
of low usable memory" for bootloader usage. This new member uses
the reserved space so that it is still compatible with previous
FSP spec 1.0.
A new HOB (FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID) is also
published when common_buf.tolum_size is valid and non zero.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Nothing CONFIG_SOC_DA830 anymore, so let's remove it and
the one remaining source file for it. It appears to have been
abandoned a while ago.
Signed-off-by: Adam Ford <aford173@gmail.com>
commit b63b995 (arm: dts: Add u-boot specific compatibles) separated out
u-boot specific compatibles from dts files.
The u-boot specifics were moved in *-u-boot.dtsi files for all dra7
platforms except dra7-evm.
Without it the SD card is broken on DRA7-evm because the regulator cannot
be enabled.
Fix it by adding the missing dra7-evm-u-boot.dtsi with the needed
properties.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
When the OP-TEE image is built for secure paging the load address may be
in SRAM, remove checks that prevent this.
Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
All these places seem to inherit the codes from the MMC driver where
a FIXME was put in the comment. However the correct operation after
read should be cache invalidate, not flush.
The underlying drivers should be responsible for the cache operation.
Remove these codes completely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: York Sun <york.sun@nxp.com>
Commit 6ae4c3efbd ("ARM: DRA7: Add pinctrl register definitions")
has added new macros for pinmux configuration in line with the kernel
definitions. Cleanup the old pinctrl macros from the common header
file so that they are not used by any new boards.
Signed-off-by: Suman Anna <s-anna@ti.com>
Use the CONFIG_XXXX_BOOT to indicate the boot media, instead of
the CONFIG_SYS_USE_XXXX option, which is declared by
CONFIG_SYS_EXTRA_OPTIONS option.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
As said in READRE.kconfig, include/configs/*.h will be removed
after all options are switched to Kconfig. As the first step,
remove the follow line from include/configs/*.h.
#include <asm/hardware.h>
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
To prepare to remove the SoCs options such as SAMA5D2, SAMA5D3
and SAMA5D4 from the CONFIG_SYS_EXTRA_OPTIONS option which is
deprecated, add the SoC options to Kconfig.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
The SAMA5D27-SiP (System in Package) integrates the SAMA5D2
with 1Gbit DDR2-SDRAM in a single package.
The SAMA5D27 SOM1 embeds a 64Mbit QSPI flash, KSZ8081 Phy and
Mac-address EEPROM.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The SAMA5D2 SiP(System in Package) has different Chip IDs in the
CHIPID and CHIP_EXID registers.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add the boot device for booting from the QSPI flash.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Refer to the commit 70f8c8316ad(PMC: add new mck function to lower
rate while switching) from AT91Bootstrap.
While switching to a lower clock source, we must switch the clock
source first instead of last. Otherwise, we could end up with
too high frequency on internal bus and peripherals.
This happens on SAMA5D2 as exitting from the ROM code.
Add a function pmc_mck_init_down() to allow this sequence.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As said in 29.5.7 section of SAMA5D2 datasheet, before switching to
the crystal oscillator, a check must be carried out to ensure that
the oscillator is present and that its freqency is valid.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a function to display the company's logo and board information
via the API from DM_VIDEO. This function can be shared by other
atmel boards, so locate it in board/atmel/common folder.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
For sama5d2, add the sfr node with syscon support.
In order to access the SFR_UTMICKTRIM register for the utmi clock
driver, add the phandle property for the utmi node to point to the
sfr node.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
By default, it is assumed that the UTMI clock is generated from
a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ
field of the SFR_UTMICKTRIM has to be updated to generate the UTMI
clock in the proper way.
The UTMI clock has a fixed rate of 480 MHz. In fact, there is no
multiplier we can configure. The multiplier is managed internally,
depending on the reference clock frequency, to achieve the target
of 480 MHz.
The patch is cloned from the patch of mailing-list:
[PATCH v2] clk: at91: utmi: set the mainck rate
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
[trini: Depend on SPL_DM]
Signed-off-by: Tom Rini <trini@konsulko.com>
