Merge git://git.denx.de/u-boot-uniphier

2024-06-09 23:36:03 +09:00 · 2017-09-18 10:58:10 -04:00 · 2017-09-18 10:58:10 -04:00 · 45d19acb2f
commit 45d19acb2f
parent c07f38208a a184fb8e96
11 changed files with 106 additions and 109 deletions
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@ -12,18 +12,14 @@ config ARCH_UNIPHIER_32BIT

 choice
        prompt "UniPhier SoC select"
-        default ARCH_UNIPHIER_PRO4
+        default ARCH_UNIPHIER_V8_MULTI

 config ARCH_UNIPHIER_LD4_SLD8
 	bool "UniPhier LD4/sLD8 SoCs"
 	select ARCH_UNIPHIER_32BIT

-config ARCH_UNIPHIER_PRO4
-	bool "UniPhier Pro4 SoC"
-	select ARCH_UNIPHIER_32BIT
-
-config ARCH_UNIPHIER_PRO5_PXS2_LD6B
-	bool "UniPhier Pro5/PXs2/LD6b SoCs"
+config ARCH_UNIPHIER_V7_MULTI
+	bool "UniPhier Pro4/Pro5/PXs2/LD6b SoCs"
 	select ARCH_UNIPHIER_32BIT

 config ARCH_UNIPHIER_V8_MULTI
@ -44,19 +40,24 @@ config ARCH_UNIPHIER_SLD8
 	depends on ARCH_UNIPHIER_LD4_SLD8
 	default y

+config ARCH_UNIPHIER_PRO4
+	bool "Enable UniPhier Pro4 SoC support"
+	depends on ARCH_UNIPHIER_V7_MULTI
+	default y
+
 config ARCH_UNIPHIER_PRO5
 	bool "Enable UniPhier Pro5 SoC support"
-	depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
+	depends on ARCH_UNIPHIER_V7_MULTI
 	default y

 config ARCH_UNIPHIER_PXS2
 	bool "Enable UniPhier Pxs2 SoC support"
-	depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
+	depends on ARCH_UNIPHIER_V7_MULTI
 	default y

 config ARCH_UNIPHIER_LD6B
 	bool "Enable UniPhier LD6b SoC support"
-	depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
+	depends on ARCH_UNIPHIER_V7_MULTI
 	default y

 config ARCH_UNIPHIER_LD11
--- a/arch/arm/mach-uniphier/clk/clk-ld11.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld11.c
@ -40,7 +40,7 @@ void uniphier_ld11_clk_init(void)
 		int ch;

 		tmp = readl(SC_CLKCTRL4);
-		tmp |= SC_CLKCTRL4_MIO | SC_CLKCTRL4_STDMAC;
+		tmp |= BIT(10) | BIT(8);	/* MIO, STDMAC */
 		writel(tmp, SC_CLKCTRL4);

 		for (ch = 0; ch < 3; ch++) {
--- a/arch/arm/mach-uniphier/clk/clk-ld20.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld20.c
@ -4,14 +4,26 @@
 * SPDX-License-Identifier:	GPL-2.0+
 */

+#include <linux/bitops.h>
 #include <linux/io.h>

 #include "../init.h"
+#include "../sc64-regs.h"

 #define SDCTRL_EMMC_HW_RESET	0x59810280

 void uniphier_ld20_clk_init(void)
 {
+	u32 tmp;
+
+	tmp = readl(SC_RSTCTRL6);
+	tmp |= BIT(8);			/* Mali */
+	writel(tmp, SC_RSTCTRL6);
+
+	tmp = readl(SC_CLKCTRL6);
+	tmp |= BIT(8);			/* Mali */
+	writel(tmp, SC_CLKCTRL6);
+
 	/* TODO: use "mmc-pwrseq-emmc" */
 	writel(1, SDCTRL_EMMC_HW_RESET);
 }
--- a/arch/arm/mach-uniphier/clk/clk-pxs3.c
+++ b/arch/arm/mach-uniphier/clk/clk-pxs3.c
@ -4,14 +4,26 @@
 * SPDX-License-Identifier:	GPL-2.0+
 */

+#include <linux/bitops.h>
 #include <linux/io.h>

 #include "../init.h"
+#include "../sc64-regs.h"

 #define SDCTRL_EMMC_HW_RESET	0x59810280

 void uniphier_pxs3_clk_init(void)
 {
+	u32 tmp;
+
+	tmp = readl(SC_RSTCTRL6);
+	tmp |= BIT(8);			/* Mali */
+	writel(tmp, SC_RSTCTRL6);
+
+	tmp = readl(SC_CLKCTRL6);
+	tmp |= BIT(8);			/* Mali */
+	writel(tmp, SC_CLKCTRL6);
+
 	/* TODO: use "mmc-pwrseq-emmc" */
 	writel(1, SDCTRL_EMMC_HW_RESET);
 }
--- a/arch/arm/mach-uniphier/sc64-regs.h
+++ b/arch/arm/mach-uniphier/sc64-regs.h
@ -15,34 +15,16 @@
 #define SC_RSTCTRL		(SC_BASE_ADDR | 0x2000)
 #define SC_RSTCTRL3		(SC_BASE_ADDR | 0x2008)
 #define SC_RSTCTRL4		(SC_BASE_ADDR | 0x200c)
-#define   SC_RSTCTRL4_ETHER		(1 << 6)
-#define   SC_RSTCTRL4_NAND		(1 << 0)
 #define SC_RSTCTRL5		(SC_BASE_ADDR | 0x2010)
 #define SC_RSTCTRL6		(SC_BASE_ADDR | 0x2014)
 #define SC_RSTCTRL7		(SC_BASE_ADDR | 0x2018)
-#define   SC_RSTCTRL7_UMCSB		(1 << 16)
-#define   SC_RSTCTRL7_UMCA2		(1 << 10)
-#define   SC_RSTCTRL7_UMCA1		(1 << 9)
-#define   SC_RSTCTRL7_UMCA0		(1 << 8)
-#define   SC_RSTCTRL7_UMC32		(1 << 2)
-#define   SC_RSTCTRL7_UMC31		(1 << 1)
-#define   SC_RSTCTRL7_UMC30		(1 << 0)

 #define SC_CLKCTRL		(SC_BASE_ADDR | 0x2100)
 #define SC_CLKCTRL3		(SC_BASE_ADDR | 0x2108)
 #define SC_CLKCTRL4		(SC_BASE_ADDR | 0x210c)
-#define   SC_CLKCTRL4_MIO		(1 << 10)
-#define   SC_CLKCTRL4_STDMAC		(1 << 8)
-#define   SC_CLKCTRL4_PERI		(1 << 7)
-#define   SC_CLKCTRL4_ETHER		(1 << 6)
-#define   SC_CLKCTRL4_NAND		(1 << 0)
 #define SC_CLKCTRL5		(SC_BASE_ADDR | 0x2110)
 #define SC_CLKCTRL6		(SC_BASE_ADDR | 0x2114)
 #define SC_CLKCTRL7		(SC_BASE_ADDR | 0x2118)
-#define   SC_CLKCTRL7_UMCSB		(1 << 16)
-#define   SC_CLKCTRL7_UMC32		(1 << 2)
-#define   SC_CLKCTRL7_UMC31		(1 << 1)
-#define   SC_CLKCTRL7_UMC30		(1 << 0)

 #define SC_CA72_GEARST		(SC_BASE_ADDR | 0x8000)
 #define SC_CA72_GEARSET		(SC_BASE_ADDR | 0x8004)
--- a/configs/uniphier_pro4_defconfig
+++ b/configs/uniphier_pro4_defconfig
@ -1,49 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_UNIPHIER=y
-CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-pro4-ref"
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_SPL=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_CONFIG=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_GPIO_UNIPHIER=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10
-CONFIG_MMC_UNIPHIER=y
-CONFIG_NAND=y
-CONFIG_NAND_DENALI=y
-CONFIG_NAND_DENALI_DT=y
-CONFIG_SYS_NAND_DENALI_64BIT=y
-CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-CONFIG_SPL_NAND_DENALI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_STORAGE=y
--- a/configs/uniphier_pxs2_ld6b_defconfig
+++ b/configs/uniphier_pxs2_ld6b_defconfig
@ -5,7 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_ARCH_UNIPHIER_PRO5_PXS2_LD6B=y
+CONFIG_ARCH_UNIPHIER_V7_MULTI=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-pxs2-vodka"
 # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
@ -45,4 +45,6 @@ CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
 CONFIG_SPL_NAND_DENALI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
 CONFIG_USB_STORAGE=y
--- a/doc/README.uniphier
+++ b/doc/README.uniphier
@ -27,17 +27,17 @@ The following tables show <defconfig> and <device-tree> for each board.

 32bit SoC boards:

- Board         | <defconfig>                  | <device-tree>
---------------|------------------------------|------------------------------
-LD4 reference  | uniphier_ld4_sld8_defconfig  | uniphier-ld4-ref (default)
-sld8 reference | uniphier_ld4_sld8_defconfig  | uniphier-sld8-def
-Pro4 reference | uniphier_pro4_defconfig      | uniphier-pro4-ref (default)
-Pro4 Ace       | uniphier_pro4_defconfig      | uniphier-pro4-ace
-Pro4 Sanji     | uniphier_pro4_defconfig      | uniphier-pro4-sanji
-Pro5 4KBOX     | uniphier_pxs2_ld6b_defconfig | uniphier-pro5-4kbox
-PXs2 Gentil    | uniphier_pxs2_ld6b_defconfig | uniphier-pxs2-gentil
-PXs2 Vodka     | uniphier_pxs2_ld6b_defconfig | uniphier-pxs2-vodka (default)
-LD6b reference | uniphier_pxs2_ld6b_defconfig | uniphier-ld6b-ref
+ Board         | <defconfig>                 | <device-tree>
+---------------|-----------------------------|------------------------------
+LD4 reference  | uniphier_ld4_sld8_defconfig | uniphier-ld4-ref (default)
+sld8 reference | uniphier_ld4_sld8_defconfig | uniphier-sld8-def
+Pro4 reference | uniphier_v7_defconfig       | uniphier-pro4-ref
+Pro4 Ace       | uniphier_v7_defconfig       | uniphier-pro4-ace
+Pro4 Sanji     | uniphier_v7_defconfig       | uniphier-pro4-sanji
+Pro5 4KBOX     | uniphier_v7_defconfig       | uniphier-pro5-4kbox
+PXs2 Gentil    | uniphier_v7_defconfig       | uniphier-pxs2-gentil
+PXs2 Vodka     | uniphier_v7_defconfig       | uniphier-pxs2-vodka (default)
+LD6b reference | uniphier_v7_defconfig       | uniphier-ld6b-ref

 64bit SoC boards:

@ -47,17 +47,18 @@ LD11 reference | uniphier_v8_defconfig | uniphier-ld11-ref
 LD11 Global    | uniphier_v8_defconfig | uniphier-ld11-global
 LD20 reference | uniphier_v8_defconfig | uniphier-ld20-ref (default)
 LD20 Global    | uniphier_v8_defconfig | uniphier-ld20-global
+PXs3 reference | uniphier_v8_defconfig | uniphier-pxs3-ref

 For example, to compile the source for PXs2 Vodka board, run the following:

-    $ make uniphier_pxs2_ld6b_defconfig
+    $ make uniphier_v7_defconfig
    $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pxs2-vodka

 The device tree marked as (default) can be omitted.  `uniphier-pxs2-vodka` is
-the default device tree for the configuration `uniphier_pxs2_ld6b_defconfig`,
-so the following gives the same result.
+the default device tree for the configuration `uniphier_v7_defconfig`, so the
+following gives the same result.

-    $ make uniphier_pxs2_ld6b_defconfig
+    $ make uniphier_v7_defconfig
    $ make CROSS_COMPILE=arm-linux-gnueabihf-


@ -178,4 +179,4 @@ newer SoCs.  Even if it is, EA[25] is not connected on most of the boards.

 --
 Masahiro Yamada <yamada.masahiro@socionext.com>
-Jul. 2017
+Sep. 2017
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@ -10,7 +10,7 @@
 #include <malloc.h>
 #include <nand.h>
 #include <linux/errno.h>
-#include <asm/io.h>
+#include <linux/io.h>

 #include "denali.h"

@ -433,17 +433,13 @@ static void find_valid_banks(struct denali_nand_info *denali)
 */
 static void detect_max_banks(struct denali_nand_info *denali)
 {
-	uint32_t features = readl(denali->flash_reg + FEATURES);
-	/*
-	 * Read the revision register, so we can calculate the max_banks
-	 * properly: the encoding changed from rev 5.0 to 5.1
-	 */
-	u32 revision = MAKE_COMPARABLE_REVISION(
-				readl(denali->flash_reg + REVISION));
-	if (revision < REVISION_5_1)
-		denali->max_banks = 2 << (features & FEATURES__N_BANKS);
-	else
-		denali->max_banks = 1 << (features & FEATURES__N_BANKS);
+	uint32_t features = ioread32(denali->flash_reg + FEATURES);
+
+	denali->max_banks = 1 << (features & FEATURES__N_BANKS);
+
+	/* the encoding changed from rev 5.0 to 5.1 */
+	if (denali->revision < 0x0501)
+		denali->max_banks <<= 1;
 }

 static void detect_partition_feature(struct denali_nand_info *denali)
@ -1153,6 +1149,13 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
 /* Initialization code to bring the device up to a known good state */
 static void denali_hw_init(struct denali_nand_info *denali)
 {
+	/*
+	 * The REVISION register may not be reliable.  Platforms are allowed to
+	 * override it.
+	 */
+	if (!denali->revision)
+		denali->revision = swab16(ioread32(denali->flash_reg + REVISION));
+
 	/*
 	 * tell driver how many bit controller will skip before writing
 	 * ECC code in OOB. This is normally used for bad block marker
--- a/drivers/mtd/nand/denali.h
+++ b/drivers/mtd/nand/denali.h
@ -166,8 +166,6 @@

 #define REVISION				0x370
 #define     REVISION__VALUE				0xffff
-#define MAKE_COMPARABLE_REVISION(x)		swab16((x) & REVISION__VALUE)
-#define REVISION_5_1				0x00000501

 #define ONFI_DEVICE_FEATURES			0x380
 #define     ONFI_DEVICE_FEATURES__VALUE			0x003f
@ -462,8 +460,13 @@ struct denali_nand_info {
 	uint32_t blksperchip;
 	uint32_t bbtskipbytes;
 	uint32_t max_banks;
+	unsigned int revision;
+	unsigned int caps;
 };

+#define DENALI_CAP_HW_ECC_FIXUP			BIT(0)
+#define DENALI_CAP_DMA_64BIT			BIT(1)
+
 int denali_init(struct denali_nand_info *denali);

 #endif /* __DENALI_H__ */
--- a/drivers/mtd/nand/denali_dt.c
+++ b/drivers/mtd/nand/denali_dt.c
@ -12,15 +12,38 @@

 #include "denali.h"

+struct denali_dt_data {
+	unsigned int revision;
+	unsigned int caps;
+};
+
+static const struct denali_dt_data denali_socfpga_data = {
+	.caps = DENALI_CAP_HW_ECC_FIXUP,
+};
+
+static const struct denali_dt_data denali_uniphier_v5a_data = {
+	.caps = DENALI_CAP_HW_ECC_FIXUP |
+		DENALI_CAP_DMA_64BIT,
+};
+
+static const struct denali_dt_data denali_uniphier_v5b_data = {
+	.revision = 0x0501,
+	.caps = DENALI_CAP_HW_ECC_FIXUP |
+		DENALI_CAP_DMA_64BIT,
+};
+
 static const struct udevice_id denali_nand_dt_ids[] = {
 	{
 		.compatible = "altr,socfpga-denali-nand",
+		.data = (unsigned long)&denali_socfpga_data,
 	},
 	{
 		.compatible = "socionext,uniphier-denali-nand-v5a",
+		.data = (unsigned long)&denali_uniphier_v5a_data,
 	},
 	{
 		.compatible = "socionext,uniphier-denali-nand-v5b",
+		.data = (unsigned long)&denali_uniphier_v5b_data,
 	},
 	{ /* sentinel */ }
 };
@ -28,9 +51,16 @@ static const struct udevice_id denali_nand_dt_ids[] = {
 static int denali_dt_probe(struct udevice *dev)
 {
 	struct denali_nand_info *denali = dev_get_priv(dev);
+	const struct denali_dt_data *data;
 	struct resource res;
 	int ret;

+	data = (void *)dev_get_driver_data(dev);
+	if (data) {
+		denali->revision = data->revision;
+		denali->caps = data->caps;
+	}
+
 	ret = dev_read_resource_byname(dev, "denali_reg", &res);
 	if (ret)
 		return ret;