Merge git://git.denx.de/u-boot-x86

2024-06-09 23:36:03 +09:00 · 2017-09-17 11:46:51 -04:00 · 2017-09-17 11:46:51 -04:00 · c07f38208a
commit c07f38208a
parent 08cebeeaad 8a1c44271c
51 changed files with 15254 additions and 49 deletions
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@ -108,6 +108,7 @@ source "board/intel/Kconfig"

 # platform-specific options below
 source "arch/x86/cpu/baytrail/Kconfig"
+source "arch/x86/cpu/braswell/Kconfig"
 source "arch/x86/cpu/broadwell/Kconfig"
 source "arch/x86/cpu/coreboot/Kconfig"
 source "arch/x86/cpu/ivybridge/Kconfig"
@ -558,6 +559,48 @@ config VGA_BIOS_ADDR
 	  address of 0xfff90000 indicates that the image will be put at offset
 	  0x90000 from the beginning of a 1MB flash device.

+config HAVE_VBT
+	bool "Add a Video BIOS Table (VBT) image"
+	depends on HAVE_FSP
+	help
+	  Select this option if you have a Video BIOS Table (VBT) image that
+	  you would like to add to your ROM. This is normally required if you
+	  are using an Intel FSP firmware that is complaint with spec 1.1 or
+	  later to initialize the integrated graphics device (IGD).
+
+	  Video BIOS Table, or VBT, provides platform and board specific
+	  configuration information to the driver that is not discoverable
+	  or available through other means. By other means the most used
+	  method here is to read EDID table from the attached monitor, over
+	  Display Data Channel (DDC) using two pin I2C serial interface. VBT
+	  configuration is related to display hardware and is available via
+	  the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
+
+config VBT_FILE
+	string "Video BIOS Table (VBT) image filename"
+	depends on HAVE_VBT
+	default "vbt.bin"
+	help
+	  The filename of the file to use as Video BIOS Table (VBT) image
+	  in the board directory.
+
+config VBT_ADDR
+	hex "Video BIOS Table (VBT) image location"
+	depends on HAVE_VBT
+	default 0xfff90000
+	help
+	  The location of Video BIOS Table (VBT) image in the SPI flash. For
+	  example, base address of 0xfff90000 indicates that the image will
+	  be put at offset 0x90000 from the beginning of a 1MB flash device.
+
+config VIDEO_FSP
+	bool "Enable FSP framebuffer driver support"
+	depends on HAVE_VBT && DM_VIDEO
+	help
+	  Turn on this option to enable a framebuffer driver when U-Boot is
+	  using Video BIOS Table (VBT) image for FSP firmware to initialize
+	  the integrated graphics device.
+
 config ROM_TABLE_ADDR
 	hex
 	default 0xf0000
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@ -27,6 +27,7 @@ endif

 obj-y += intel_common/
 obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
+obj-$(CONFIG_INTEL_BRASWELL) += braswell/
 obj-$(CONFIG_INTEL_BROADWELL) += broadwell/
 obj-$(CONFIG_SYS_COREBOOT) += coreboot/
 obj-$(CONFIG_EFI_APP) += efi/
--- a/arch/x86/cpu/braswell/Kconfig
+++ b/arch/x86/cpu/braswell/Kconfig
@ -0,0 +1,39 @@
+#
+# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+config INTEL_BRASWELL
+	bool
+	select HAVE_FSP
+	select ARCH_MISC_INIT
+	select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+	imply HAVE_INTEL_ME
+	imply HAVE_VBT
+	imply ENABLE_MRC_CACHE
+	imply ENV_IS_IN_SPI_FLASH
+	imply AHCI_PCI
+	imply ICH_SPI
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply SCSI
+	imply SPI_FLASH
+	imply SYS_NS16550
+	imply USB
+	imply USB_XHCI_HCD
+	imply VIDEO_FSP
+
+if INTEL_BRASWELL
+
+config FSP_ADDR
+	hex
+	default 0xfff20000
+
+config FSP_LOCKDOWN_SPI
+	bool
+	default y
+
+endif
--- a/arch/x86/cpu/braswell/Makefile
+++ b/arch/x86/cpu/braswell/Makefile
@ -0,0 +1,7 @@
+#
+# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += braswell.o cpu.o early_uart.o fsp_configs.o
--- a/arch/x86/cpu/braswell/braswell.c
+++ b/arch/x86/cpu/braswell/braswell.c
@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mrccache.h>
+#include <asm/post.h>
+
+int arch_cpu_init(void)
+{
+	post_code(POST_CPU_INIT);
+
+	return x86_cpu_init_f();
+}
+
+int arch_misc_init(void)
+{
+#ifdef CONFIG_ENABLE_MRC_CACHE
+	/*
+	 * We intend not to check any return value here, as even MRC cache
+	 * is not saved successfully, it is not a severe error that will
+	 * prevent system from continuing to boot.
+	 */
+	mrccache_save();
+#endif
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	/* cold reset */
+	x86_full_reset();
+}
--- a/arch/x86/cpu/braswell/cpu.c
+++ b/arch/x86/cpu/braswell/cpu.c
@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Derived from arch/x86/cpu/baytrail/cpu.c
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <asm/cpu.h>
+#include <asm/cpu_x86.h>
+#include <asm/io.h>
+#include <asm/lapic.h>
+#include <asm/msr.h>
+#include <asm/turbo.h>
+
+static const unsigned int braswell_bus_freq_table[] = {
+	83333333,
+	100000000,
+	133333333,
+	116666666,
+	80000000,
+	93333333,
+	90000000,
+	88900000,
+	87500000
+};
+
+static unsigned int braswell_bus_freq(void)
+{
+	msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);
+
+	if ((clk_info.lo & 0xf) < (ARRAY_SIZE(braswell_bus_freq_table)))
+		return braswell_bus_freq_table[clk_info.lo & 0xf];
+
+	return 0;
+}
+
+static unsigned long braswell_tsc_freq(void)
+{
+	msr_t platform_info;
+	ulong bclk = braswell_bus_freq();
+
+	if (!bclk)
+		return 0;
+
+	platform_info = msr_read(MSR_PLATFORM_INFO);
+
+	return bclk * ((platform_info.lo >> 8) & 0xff);
+}
+
+static int braswell_get_info(struct udevice *dev, struct cpu_info *info)
+{
+	info->cpu_freq = braswell_tsc_freq();
+	info->features = (1 << CPU_FEAT_L1_CACHE) | (1 << CPU_FEAT_MMU);
+
+	return 0;
+}
+
+static int braswell_get_count(struct udevice *dev)
+{
+	int ecx = 0;
+
+	/*
+	 * Use the algorithm described in Intel 64 and IA-32 Architectures
+	 * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
+	 * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
+	 * of CPUID Extended Topology Leaf.
+	 */
+	while (1) {
+		struct cpuid_result leaf_b;
+
+		leaf_b = cpuid_ext(0xb, ecx);
+
+		/*
+		 * Braswell doesn't have hyperthreading so just determine the
+		 * number of cores by from level type (ecx[15:8] == * 2)
+		 */
+		if ((leaf_b.ecx & 0xff00) == 0x0200)
+			return leaf_b.ebx & 0xffff;
+
+		ecx++;
+	}
+
+	return 0;
+}
+
+static void braswell_set_max_freq(void)
+{
+	msr_t perf_ctl;
+	msr_t msr;
+
+	/* Enable speed step */
+	msr = msr_read(MSR_IA32_MISC_ENABLES);
+	msr.lo |= (1 << 16);
+	msr_write(MSR_IA32_MISC_ENABLES, msr);
+
+	/* Enable Burst Mode */
+	msr = msr_read(MSR_IA32_MISC_ENABLES);
+	msr.hi = 0;
+	msr_write(MSR_IA32_MISC_ENABLES, msr);
+
+	/*
+	 * Set guaranteed ratio [21:16] from IACORE_TURBO_RATIOS to
+	 * bits [15:8] of the PERF_CTL
+	 */
+	msr = msr_read(MSR_IACORE_TURBO_RATIOS);
+	perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
+
+	/*
+	 * Set guaranteed vid [22:16] from IACORE_TURBO_VIDS to
+	 * bits [7:0] of the PERF_CTL
+	 */
+	msr = msr_read(MSR_IACORE_TURBO_VIDS);
+	perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
+
+	perf_ctl.hi = 0;
+	msr_write(MSR_IA32_PERF_CTL, perf_ctl);
+}
+
+static int braswell_probe(struct udevice *dev)
+{
+	debug("Init Braswell core\n");
+
+	/*
+	 * On Braswell the turbo disable bit is actually scoped at the
+	 * building-block level, not package. For non-BSP cores that are
+	 * within a building block, enable turbo. The cores within the BSP's
+	 * building block will just see it already enabled and move on.
+	 */
+	if (lapicid())
+		turbo_enable();
+
+	/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
+	msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f080f, 0xe0008),
+	msr_clrsetbits_64(MSR_POWER_MISC,
+			  ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK, 0);
+
+	/* Disable C1E */
+	msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);
+	msr_setbits_64(MSR_POWER_MISC, 0x44);
+
+	/* Set this core to max frequency ratio */
+	braswell_set_max_freq();
+
+	return 0;
+}
+
+static const struct udevice_id braswell_ids[] = {
+	{ .compatible = "intel,braswell-cpu" },
+	{ }
+};
+
+static const struct cpu_ops braswell_ops = {
+	.get_desc	= cpu_x86_get_desc,
+	.get_info	= braswell_get_info,
+	.get_count	= braswell_get_count,
+	.get_vendor	= cpu_x86_get_vendor,
+};
+
+U_BOOT_DRIVER(cpu_x86_braswell_drv) = {
+	.name		= "cpu_x86_braswell",
+	.id		= UCLASS_CPU,
+	.of_match	= braswell_ids,
+	.bind		= cpu_x86_bind,
+	.probe		= braswell_probe,
+	.ops		= &braswell_ops,
+};
--- a/arch/x86/cpu/braswell/early_uart.c
+++ b/arch/x86/cpu/braswell/early_uart.c
@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define PCI_DEV_CONFIG(segbus, dev, fn) ( \
+		(((segbus) & 0xfff) << 20) | \
+		(((dev) & 0x1f) << 15) | \
+		(((fn)  & 0x07) << 12))
+
+/* Platform Controller Unit */
+#define LPC_DEV			0x1f
+#define LPC_FUNC		0
+
+/* Enable UART */
+#define UART_CONT		0x80
+
+/* UART PAD definitions */
+#define UART_RXD_COMMUITY	1
+#define UART_TXD_COMMUITY	1
+#define UART_RXD_FAMILY		4
+#define UART_TXD_FAMILY		4
+#define UART_RXD_PAD		2
+#define UART_TXD_PAD		7
+#define UART_RXD_FUNC		3
+#define UART_TXD_FUNC		3
+
+/* IO Memory */
+#define IO_BASE_ADDRESS		0xfed80000
+
+static inline uint32_t gpio_pconf0(int community, int family, int pad)
+{
+	return IO_BASE_ADDRESS + community * 0x8000 + 0x4400 +
+		family * 0x400 + pad * 8;
+}
+
+static void gpio_select_func(int community, int family, int pad, int func)
+{
+	uint32_t pconf0_addr = gpio_pconf0(community, family, pad);
+
+	clrsetbits_le32(pconf0_addr, 0xf << 16, func << 16);
+}
+
+static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
+{
+	unsigned long addr;
+
+	addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
+	writel(value, addr);
+}
+
+/* This can be called after memory-mapped PCI is working */
+int setup_internal_uart(int enable)
+{
+	/* Enable or disable the legacy UART hardware */
+	x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
+			       enable);
+
+	/* All done for the disable part, so just return */
+	if (!enable)
+		return 0;
+
+	/*
+	 * Set up the pads to the UART function. This allows the signals to
+	 * leave the chip
+	 */
+	gpio_select_func(UART_RXD_COMMUITY, UART_RXD_FAMILY,
+			 UART_RXD_PAD, UART_RXD_FUNC);
+	gpio_select_func(UART_TXD_COMMUITY, UART_TXD_FAMILY,
+			 UART_TXD_PAD, UART_TXD_FUNC);
+
+	return 0;
+}
+
+void board_debug_uart_init(void)
+{
+	setup_internal_uart(1);
+}
--- a/arch/x86/cpu/braswell/fsp_configs.c
+++ b/arch/x86/cpu/braswell/fsp_configs.c
@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * Override the FSP's Azalia configuration data
+ *
+ * @azalia:	pointer to be updated to point to a ROM address where Azalia
+ *		configuration data is stored
+ */
+__weak void update_fsp_azalia_configs(struct azalia_config **azalia)
+{
+	*azalia = NULL;
+}
+
+/**
+ * Override the FSP's GPIO configuration data
+ *
+ * @family:	pointer to be updated to point to a ROM address where GPIO
+ *		family configuration data is stored
+ * @pad:	pointer to be updated to point to a ROM address where GPIO
+ *		pad configuration data is stored
+ */
+__weak void update_fsp_gpio_configs(struct gpio_family **family,
+				    struct gpio_pad **pad)
+{
+	*family = NULL;
+	*pad = NULL;
+}
+
+/**
+ * Override the FSP's configuration data.
+ * If the device tree does not specify an integer setting, use the default
+ * provided in Intel's Braswell release FSP/BraswellFsp.bsf file.
+ */
+void update_fsp_configs(struct fsp_config_data *config,
+			struct fspinit_rtbuf *rt_buf)
+{
+	struct upd_region *fsp_upd = &config->fsp_upd;
+	struct memory_upd *memory_upd = &fsp_upd->memory_upd;
+	struct silicon_upd *silicon_upd = &fsp_upd->silicon_upd;
+	const void *blob = gd->fdt_blob;
+	int node;
+
+	/* Initialize runtime buffer for fsp_init() */
+	rt_buf->common.stack_top = config->common.stack_top - 32;
+	rt_buf->common.boot_mode = config->common.boot_mode;
+	rt_buf->common.upd_data = &config->fsp_upd;
+
+	node = fdt_node_offset_by_compatible(blob, 0, "intel,braswell-fsp");
+	if (node < 0) {
+		debug("%s: Cannot find FSP node\n", __func__);
+		return;
+	}
+
+	node = fdt_node_offset_by_compatible(blob, node,
+					     "intel,braswell-fsp-memory");
+	if (node < 0) {
+		debug("%s: Cannot find FSP memory node\n", __func__);
+		return;
+	}
+
+	/* Override memory UPD contents */
+	memory_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node,
+		"fsp,mrc-init-tseg-size", MRC_INIT_TSEG_SIZE_4MB);
+	memory_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node,
+		"fsp,mrc-init-mmio-size", MRC_INIT_MMIO_SIZE_2048MB);
+	memory_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node,
+		"fsp,mrc-init-spd-addr1", 0xa0);
+	memory_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node,
+		"fsp,mrc-init-spd-addr2", 0xa2);
+	memory_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node,
+		"fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_32MB);
+	memory_upd->aperture_size = fdtdec_get_int(blob, node,
+		"fsp,aperture-size", APERTURE_SIZE_256MB);
+	memory_upd->gtt_size = fdtdec_get_int(blob, node,
+		"fsp,gtt-size", GTT_SIZE_1MB);
+	memory_upd->legacy_seg_decode = fdtdec_get_bool(blob, node,
+		"fsp,legacy-seg-decode");
+	memory_upd->enable_dvfs = fdtdec_get_bool(blob, node,
+		"fsp,enable-dvfs");
+	memory_upd->memory_type = fdtdec_get_int(blob, node,
+		"fsp,memory-type", DRAM_TYPE_DDR3);
+	memory_upd->enable_ca_mirror = fdtdec_get_bool(blob, node,
+		"fsp,enable-ca-mirror");
+
+	node = fdt_node_offset_by_compatible(blob, node,
+					     "intel,braswell-fsp-silicon");
+	if (node < 0) {
+		debug("%s: Cannot find FSP silicon node\n", __func__);
+		return;
+	}
+
+	/* Override silicon UPD contents */
+	silicon_upd->sdcard_mode = fdtdec_get_int(blob, node,
+		"fsp,sdcard-mode", SDCARD_MODE_PCI);
+	silicon_upd->enable_hsuart0 = fdtdec_get_bool(blob, node,
+		"fsp,enable-hsuart0");
+	silicon_upd->enable_hsuart1 = fdtdec_get_bool(blob, node,
+		"fsp,enable-hsuart1");
+	silicon_upd->enable_azalia = fdtdec_get_bool(blob, node,
+		"fsp,enable-azalia");
+	if (silicon_upd->enable_azalia)
+		update_fsp_azalia_configs(&silicon_upd->azalia_cfg_ptr);
+	silicon_upd->enable_sata = fdtdec_get_bool(blob, node,
+		"fsp,enable-sata");
+	silicon_upd->enable_xhci = fdtdec_get_bool(blob, node,
+		"fsp,enable-xhci");
+	silicon_upd->lpe_mode = fdtdec_get_int(blob, node,
+		"fsp,lpe-mode", LPE_MODE_PCI);
+	silicon_upd->enable_dma0 = fdtdec_get_bool(blob, node,
+		"fsp,enable-dma0");
+	silicon_upd->enable_dma1 = fdtdec_get_bool(blob, node,
+		"fsp,enable-dma1");
+	silicon_upd->enable_i2c0 = fdtdec_get_bool(blob, node,
+		"fsp,enable-i2c0");
+	silicon_upd->enable_i2c1 = fdtdec_get_bool(blob, node,
+		"fsp,enable-i2c1");
+	silicon_upd->enable_i2c2 = fdtdec_get_bool(blob, node,
+		"fsp,enable-i2c2");
+	silicon_upd->enable_i2c3 = fdtdec_get_bool(blob, node,
+		"fsp,enable-i2c3");
+	silicon_upd->enable_i2c4 = fdtdec_get_bool(blob, node,
+		"fsp,enable-i2c4");
+	silicon_upd->enable_i2c5 = fdtdec_get_bool(blob, node,
+		"fsp,enable-i2c5");
+	silicon_upd->enable_i2c6 = fdtdec_get_bool(blob, node,
+		"fsp,enable-i2c6");
+#ifdef CONFIG_HAVE_VBT
+	silicon_upd->graphics_config_ptr = CONFIG_VBT_ADDR;
+#endif
+	update_fsp_gpio_configs(&silicon_upd->gpio_familiy_ptr,
+				&silicon_upd->gpio_pad_ptr);
+	/*
+	 * For Braswell B0 stepping, disable_punit_pwr_config must be set to 1
+	 * otherwise it just hangs in fsp_init().
+	 */
+	if (gd->arch.x86_mask == 2)
+		silicon_upd->disable_punit_pwr_config = 1;
+	silicon_upd->emmc_mode = fdtdec_get_int(blob, node,
+		"fsp,emmc-mode", EMMC_MODE_PCI);
+	silicon_upd->sata_speed = fdtdec_get_int(blob, node,
+		"fsp,sata-speed", SATA_SPEED_GEN3);
+	silicon_upd->pmic_i2c_bus = fdtdec_get_int(blob, node,
+		"fsp,pmic-i2c-bus", 0);
+	silicon_upd->enable_isp = fdtdec_get_bool(blob, node,
+		"fsp,enable-isp");
+	silicon_upd->isp_pci_dev_config = fdtdec_get_int(blob, node,
+		"fsp,isp-pci-dev-config", ISP_PCI_DEV_CONFIG_2);
+	silicon_upd->turbo_mode = fdtdec_get_bool(blob, node,
+		"fsp,turbo-mode");
+	silicon_upd->pnp_settings = fdtdec_get_int(blob, node,
+		"fsp,pnp-settings", PNP_SETTING_POWER_AND_PERF);
+	silicon_upd->sd_detect_chk = fdtdec_get_bool(blob, node,
+		"fsp,sd-detect-chk");
+}
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@ -34,16 +34,6 @@ int bridge_silicon_revision(struct udevice *dev)
 	return bridge_id | stepping;
 }

-/*
- * Reserve everything between A segment and 1MB:
- *
- * 0xa0000 - 0xbffff: legacy VGA
- * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
- * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
- */
-static const int legacy_hole_base_k = 0xa0000 / 1024;
-static const int legacy_hole_size_k = 384;
-
 static int get_pcie_bar(struct udevice *dev, u32 *base, u32 *len)
 {
 	u32 pciexbar_reg;
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@ -3,6 +3,7 @@
 #

 dtb-y += bayleybay.dtb \
+	cherryhill.dtb \
 	chromebook_link.dtb \
 	chromebox_panther.dtb \
 	chromebook_samus.dtb \
--- a/arch/x86/dts/cherryhill.dts
+++ b/arch/x86/dts/cherryhill.dts
@ -0,0 +1,215 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include <asm/arch-braswell/fsp/fsp_configs.h>
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+	model = "Intel Cherry Hill";
+	compatible = "intel,cherryhill", "intel,braswell";
+
+	aliases {
+		serial0 = &serial;
+		spi0 = &spi;
+	};
+
+	config {
+		silent_console = <0>;
+	};
+
+	chosen {
+		stdout-path = "/serial";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,braswell-cpu";
+			reg = <0>;
+			intel,apic-id = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "intel,braswell-cpu";
+			reg = <1>;
+			intel,apic-id = <2>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "intel,braswell-cpu";
+			reg = <2>;
+			intel,apic-id = <4>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "intel,braswell-cpu";
+			reg = <3>;
+			intel,apic-id = <6>;
+		};
+	};
+
+	pci {
+		compatible = "pci-x86";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
+			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
+			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+		pch@1f,0 {
+			reg = <0x0000f800 0 0 0 0>;
+			compatible = "intel,pch9";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			irq-router {
+				compatible = "intel,irq-router";
+				intel,pirq-config = "ibase";
+				intel,ibase-offset = <0x50>;
+				intel,pirq-link = <8 8>;
+				intel,pirq-mask = <0xdee0>;
+				intel,pirq-routing = <
+					/* Braswell PCI devices */
+					PCI_BDF(0, 2, 0) INTA PIRQA
+					PCI_BDF(0, 3, 0) INTA PIRQA
+					PCI_BDF(0, 11, 0) INTA PIRQA
+					PCI_BDF(0, 16, 0) INTA PIRQA
+					PCI_BDF(0, 17, 0) INTA PIRQA
+					PCI_BDF(0, 18, 0) INTA PIRQA
+					PCI_BDF(0, 19, 0) INTA PIRQA
+					PCI_BDF(0, 20, 0) INTA PIRQA
+					PCI_BDF(0, 21, 0) INTA PIRQA
+					PCI_BDF(0, 24, 0) INTA PIRQA
+					PCI_BDF(0, 24, 1) INTC PIRQC
+					PCI_BDF(0, 24, 2) INTD PIRQD
+					PCI_BDF(0, 24, 3) INTB PIRQB
+					PCI_BDF(0, 24, 4) INTA PIRQA
+					PCI_BDF(0, 24, 5) INTC PIRQC
+					PCI_BDF(0, 24, 6) INTD PIRQD
+					PCI_BDF(0, 24, 7) INTB PIRQB
+					PCI_BDF(0, 26, 0) INTA PIRQA
+					PCI_BDF(0, 27, 0) INTA PIRQA
+					PCI_BDF(0, 28, 0) INTA PIRQA
+					PCI_BDF(0, 28, 1) INTB PIRQB
+					PCI_BDF(0, 28, 2) INTC PIRQC
+					PCI_BDF(0, 28, 3) INTD PIRQD
+					PCI_BDF(0, 30, 0) INTA PIRQA
+					PCI_BDF(0, 30, 3) INTA PIRQA
+					PCI_BDF(0, 30, 4) INTA PIRQA
+					PCI_BDF(0, 31, 0) INTB PIRQB
+					PCI_BDF(0, 31, 3) INTB PIRQB
+
+					/*
+					 * PCIe root ports downstream
+					 * interrupts
+					 */
+					PCI_BDF(1, 0, 0) INTA PIRQA
+					PCI_BDF(1, 0, 0) INTB PIRQB
+					PCI_BDF(1, 0, 0) INTC PIRQC
+					PCI_BDF(1, 0, 0) INTD PIRQD
+					PCI_BDF(2, 0, 0) INTA PIRQB
+					PCI_BDF(2, 0, 0) INTB PIRQC
+					PCI_BDF(2, 0, 0) INTC PIRQD
+					PCI_BDF(2, 0, 0) INTD PIRQA
+					PCI_BDF(3, 0, 0) INTA PIRQC
+					PCI_BDF(3, 0, 0) INTB PIRQD
+					PCI_BDF(3, 0, 0) INTC PIRQA
+					PCI_BDF(3, 0, 0) INTD PIRQB
+					PCI_BDF(4, 0, 0) INTA PIRQD
+					PCI_BDF(4, 0, 0) INTB PIRQA
+					PCI_BDF(4, 0, 0) INTC PIRQB
+					PCI_BDF(4, 0, 0) INTD PIRQC
+				>;
+			};
+
+			spi: spi {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "intel,ich9-spi";
+
+				spi-flash@0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					reg = <0>;
+					compatible = "macronix,mx25u6435f", "spi-flash";
+					memory-map = <0xff800000 0x00800000>;
+					rw-mrc-cache {
+						label = "rw-mrc-cache";
+						reg = <0x005e0000 0x00010000>;
+					};
+				};
+			};
+		};
+	};
+
+	fsp {
+		compatible = "intel,braswell-fsp";
+		fsp,memory-upd {
+			compatible = "intel,braswell-fsp-memory";
+			fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_4MB>;
+			fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
+			fsp,mrc-init-spd-addr1 = <0xa0>;
+			fsp,mrc-init-spd-addr2 = <0xa2>;
+			fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_32MB>;
+			fsp,aperture-size = <APERTURE_SIZE_256MB>;
+			fsp,gtt-size = <GTT_SIZE_1MB>;
+			fsp,enable-dvfs;
+			fsp,memory-type = <DRAM_TYPE_DDR3>;
+		};
+		fsp,silicon-upd {
+			compatible = "intel,braswell-fsp-silicon";
+			fsp,sdcard-mode = <SDCARD_MODE_PCI>;
+			fsp,enable-hsuart1;
+			fsp,enable-sata;
+			fsp,enable-xhci;
+			fsp,lpe-mode = <LPE_MODE_PCI>;
+			fsp,enable-dma0;
+			fsp,enable-dma1;
+			fsp,enable-i2c0;
+			fsp,enable-i2c1;
+			fsp,enable-i2c2;
+			fsp,enable-i2c3;
+			fsp,enable-i2c4;
+			fsp,enable-i2c5;
+			fsp,enable-i2c6;
+			fsp,emmc-mode = <EMMC_MODE_PCI>;
+			fsp,sata-speed = <SATA_SPEED_GEN3>;
+			fsp,pmic-i2c-bus = <0>;
+			fsp,enable-isp;
+			fsp,isp-pci-dev-config = <ISP_PCI_DEV_CONFIG_2>;
+			fsp,turbo-mode;
+			fsp,pnp-settings = <PNP_SETTING_POWER_AND_PERF>;
+			fsp,sd-detect-chk;
+		};
+	};
+
+	microcode {
+		update@0 {
+#include "microcode/m01406c2220.dtsi"
+		};
+		update@1 {
+#include "microcode/m01406c3363.dtsi"
+		};
+		update@2 {
+#include "microcode/m01406c440a.dtsi"
+		};
+	};
+
+};
--- a/arch/x86/dts/microcode/m01406c2220.dtsi
+++ b/arch/x86/dts/microcode/m01406c2220.dtsi
--- a/arch/x86/dts/microcode/m01406c3363.dtsi
+++ b/arch/x86/dts/microcode/m01406c3363.dtsi
--- a/arch/x86/dts/microcode/m01406c440a.dtsi
+++ b/arch/x86/dts/microcode/m01406c440a.dtsi
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@ -67,6 +67,12 @@
 			pos = <CONFIG_VGA_BIOS_ADDR>;
 		};
 #endif
+#ifdef CONFIG_HAVE_VBT
+		intel-vbt {
+			filename = CONFIG_VBT_FILE;
+			pos = <CONFIG_VBT_ADDR>;
+		};
+#endif
 #ifdef CONFIG_HAVE_REFCODE
 		intel-refcode {
 			pos = <CONFIG_X86_REFCODE_ADDR>;
--- a/arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
+++ b/arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+#ifndef __ASSEMBLY__
+struct fsp_config_data {
+	struct fsp_cfg_common	common;
+	struct upd_region	fsp_upd;
+};
+
+struct fspinit_rtbuf {
+	struct common_buf	common;	/* FSP common runtime data structure */
+};
+#endif
+
+/* FSP user configuration settings */
+
+#define MRC_INIT_TSEG_SIZE_1MB		1
+#define MRC_INIT_TSEG_SIZE_2MB		2
+#define MRC_INIT_TSEG_SIZE_4MB		4
+#define MRC_INIT_TSEG_SIZE_8MB		8
+
+#define MRC_INIT_MMIO_SIZE_1024MB	0x400
+#define MRC_INIT_MMIO_SIZE_1536MB	0x600
+#define MRC_INIT_MMIO_SIZE_2048MB	0x800
+
+#define IGD_DVMT50_PRE_ALLOC_32MB	0x01
+#define IGD_DVMT50_PRE_ALLOC_64MB	0x02
+#define IGD_DVMT50_PRE_ALLOC_96MB	0x03
+#define IGD_DVMT50_PRE_ALLOC_128MB	0x04
+#define IGD_DVMT50_PRE_ALLOC_160MB	0x05
+#define IGD_DVMT50_PRE_ALLOC_192MB	0x06
+#define IGD_DVMT50_PRE_ALLOC_224MB	0x07
+#define IGD_DVMT50_PRE_ALLOC_256MB	0x08
+#define IGD_DVMT50_PRE_ALLOC_288MB	0x09
+#define IGD_DVMT50_PRE_ALLOC_320MB	0x0a
+#define IGD_DVMT50_PRE_ALLOC_352MB	0x0b
+#define IGD_DVMT50_PRE_ALLOC_384MB	0x0c
+#define IGD_DVMT50_PRE_ALLOC_416MB	0x0d
+#define IGD_DVMT50_PRE_ALLOC_448MB	0x0e
+#define IGD_DVMT50_PRE_ALLOC_480MB	0x0f
+#define IGD_DVMT50_PRE_ALLOC_512MB	0x10
+
+#define APERTURE_SIZE_128MB		1
+#define APERTURE_SIZE_256MB		2
+#define APERTURE_SIZE_512MB		3
+
+#define GTT_SIZE_1MB			1
+#define GTT_SIZE_2MB			2
+
+#define DRAM_TYPE_DDR3			0
+#define DRAM_TYPE_LPDDR3		1
+
+#define SDCARD_MODE_DISABLED		0
+#define SDCARD_MODE_PCI			1
+#define SDCARD_MODE_ACPI		2
+
+#define LPE_MODE_DISABLED		0
+#define LPE_MODE_PCI			1
+#define LPE_MODE_ACPI			2
+
+#define CHV_SVID_CONFIG_0		0
+#define CHV_SVID_CONFIG_1		1
+#define CHV_SVID_CONFIG_2		2
+#define CHV_SVID_CONFIG_3		3
+
+#define EMMC_MODE_DISABLED		0
+#define EMMC_MODE_PCI			1
+#define EMMC_MODE_ACPI			2
+
+#define SATA_SPEED_GEN1			1
+#define SATA_SPEED_GEN2			2
+#define SATA_SPEED_GEN3			3
+
+#define ISP_PCI_DEV_CONFIG_1		1
+#define ISP_PCI_DEV_CONFIG_2		2
+#define ISP_PCI_DEV_CONFIG_3		3
+
+#define PNP_SETTING_DISABLED		0
+#define PNP_SETTING_POWER		1
+#define PNP_SETTING_PERF		2
+#define PNP_SETTING_POWER_AND_PERF	3
+
+#endif /* __FSP_CONFIGS_H__ */
--- a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
+++ b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2015, Intel Corporation
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	Intel
+ */
+
+#ifndef __FSP_VPD_H__
+#define __FSP_VPD_H__
+
+struct __packed memory_upd {
+	u64 signature;				/* Offset 0x0020 */
+	u8 revision;				/* Offset 0x0028 */
+	u8 unused2[7];				/* Offset 0x0029 */
+	u16 mrc_init_tseg_size;			/* Offset 0x0030 */
+	u16 mrc_init_mmio_size;			/* Offset 0x0032 */
+	u8 mrc_init_spd_addr1;			/* Offset 0x0034 */
+	u8 mrc_init_spd_addr2;			/* Offset 0x0035 */
+	u8 mem_ch0_config;			/* Offset 0x0036 */
+	u8 mem_ch1_config;			/* Offset 0x0037 */
+	u32 memory_spd_ptr;			/* Offset 0x0038 */
+	u8 igd_dvmt50_pre_alloc;		/* Offset 0x003c */
+	u8 aperture_size;			/* Offset 0x003d */
+	u8 gtt_size;				/* Offset 0x003e */
+	u8 legacy_seg_decode;			/* Offset 0x003f */
+	u8 enable_dvfs;				/* Offset 0x0040 */
+	u8 memory_type;				/* Offset 0x0041 */
+	u8 enable_ca_mirror;			/* Offset 0x0042 */
+	u8 reserved[189];			/* Offset 0x0043 */
+};
+
+struct __packed azalia_verb_table_header {
+	u32 vendor_device_id;
+	u16 sub_system_id;
+	u8 revision_id;
+	u8 front_panel_support;
+	u16 number_of_rear_jacks;
+	u16 number_of_front_jacks;
+};
+
+struct __packed azalia_verb_table {
+	struct azalia_verb_table_header header;
+	u32 *data;
+};
+
+struct __packed azalia_config {
+	u8 pme_enable:1;
+	u8 docking_supported:1;
+	u8 docking_attached:1;
+	u8 hdmi_codec_enable:1;
+	u8 azalia_v_ci_enable:1;
+	u8 reserved:3;
+	u8 verb_table_num;
+	struct azalia_verb_table *verb_table;
+	u16 reset_wait_timer_ms;
+};
+
+struct gpio_family {
+	u32 confg;
+	u32 confg_changes;
+	u32 misc;
+	u32 mmio_addr;
+	wchar_t *name;
+};
+
+struct gpio_pad {
+	u32 confg0;
+	u32 confg0_changes;
+	u32 confg1;
+	u32 confg1_changes;
+	u32 community;
+	u32 mmio_addr;
+	wchar_t *name;
+	u32 misc;
+};
+
+struct __packed silicon_upd {
+	u64 signature;				/* Offset 0x0100 */
+	u8 revision;				/* Offset 0x0108 */
+	u8 unused3[7];				/* Offset 0x0109 */
+	u8 sdcard_mode;				/* Offset 0x0110 */
+	u8 enable_hsuart0;			/* Offset 0x0111 */
+	u8 enable_hsuart1;			/* Offset 0x0112 */
+	u8 enable_azalia;			/* Offset 0x0113 */
+	struct azalia_config *azalia_cfg_ptr;	/* Offset 0x0114 */
+	u8 enable_sata;				/* Offset 0x0118 */
+	u8 enable_xhci;				/* Offset 0x0119 */
+	u8 lpe_mode;				/* Offset 0x011a */
+	u8 enable_dma0;				/* Offset 0x011b */
+	u8 enable_dma1;				/* Offset 0x011c */
+	u8 enable_i2c0;				/* Offset 0x011d */
+	u8 enable_i2c1;				/* Offset 0x011e */
+	u8 enable_i2c2;				/* Offset 0x011f */
+	u8 enable_i2c3;				/* Offset 0x0120 */
+	u8 enable_i2c4;				/* Offset 0x0121 */
+	u8 enable_i2c5;				/* Offset 0x0122 */
+	u8 enable_i2c6;				/* Offset 0x0123 */
+	u32 graphics_config_ptr;		/* Offset 0x0124 */
+	struct gpio_family *gpio_familiy_ptr;	/* Offset 0x0128 */
+	struct gpio_pad *gpio_pad_ptr;		/* Offset 0x012c */
+	u8 disable_punit_pwr_config;		/* Offset 0x0130 */
+	u8 chv_svid_config;			/* Offset 0x0131 */
+	u8 disable_dptf;			/* Offset 0x0132 */
+	u8 emmc_mode;				/* Offset 0x0133 */
+	u8 usb3_clk_ssc;			/* Offset 0x0134 */
+	u8 disp_clk_ssc;			/* Offset 0x0135 */
+	u8 sata_clk_ssc;			/* Offset 0x0136 */
+	u8 usb2_port0_pe_txi_set;		/* Offset 0x0137 */
+	u8 usb2_port0_txi_set;			/* Offset 0x0138 */
+	u8 usb2_port0_tx_emphasis_en;		/* Offset 0x0139 */
+	u8 usb2_port0_tx_pe_half;		/* Offset 0x013a */
+	u8 usb2_port1_pe_txi_set;		/* Offset 0x013b */
+	u8 usb2_port1_txi_set;			/* Offset 0x013c */
+	u8 usb2_port1_tx_emphasis_en;		/* Offset 0x013d */
+	u8 usb2_port1_tx_pe_half;		/* Offset 0x013e */
+	u8 usb2_port2_pe_txi_set;		/* Offset 0x013f */
+	u8 usb2_port2_txi_set;			/* Offset 0x0140 */
+	u8 usb2_port2_tx_emphasis_en;		/* Offset 0x0141 */
+	u8 usb2_port2_tx_pe_half;		/* Offset 0x0142 */
+	u8 usb2_port3_pe_txi_set;		/* Offset 0x0143 */
+	u8 usb2_port3_txi_set;			/* Offset 0x0144 */
+	u8 usb2_port3_tx_emphasis_en;		/* Offset 0x0145 */
+	u8 usb2_port3_tx_pe_half;		/* Offset 0x0146 */
+	u8 usb2_port4_pe_txi_set;		/* Offset 0x0147 */
+	u8 usb2_port4_txi_set;			/* Offset 0x0148 */
+	u8 usb2_port4_tx_emphasis_en;		/* Offset 0x0149 */
+	u8 usb2_port4_tx_pe_half;		/* Offset 0x014a */
+	u8 usb3_lane0_ow2tap_gen2_deemph3p5;	/* Offset 0x014b */
+	u8 usb3_lane1_ow2tap_gen2_deemph3p5;	/* Offset 0x014c */
+	u8 usb3_lane2_ow2tap_gen2_deemph3p5;	/* Offset 0x014d */
+	u8 usb3_lane3_ow2tap_gen2_deemph3p5;	/* Offset 0x014e */
+	u8 sata_speed;				/* Offset 0x014f */
+	u8 usb_ssic_port;			/* Offset 0x0150 */
+	u8 usb_hsic_port;			/* Offset 0x0151 */
+	u8 pcie_rootport_speed;			/* Offset 0x0152 */
+	u8 enable_ssic;				/* Offset 0x0153 */
+	u32 logo_ptr;				/* Offset 0x0154 */
+	u32 logo_size;				/* Offset 0x0158 */
+	u8 rtc_lock;				/* Offset 0x015c */
+	u8 pmic_i2c_bus;			/* Offset 0x015d */
+	u8 enable_isp;				/* Offset 0x015e */
+	u8 isp_pci_dev_config;			/* Offset 0x015f */
+	u8 turbo_mode;				/* Offset 0x0160 */
+	u8 pnp_settings;			/* Offset 0x0161 */
+	u8 sd_detect_chk;			/* Offset 0x0162 */
+	u8 reserved[411];			/* Offset 0x0163 */
+};
+
+#define MEMORY_UPD_ID	0x244450554d454d24	/* '$MEMUPD$' */
+#define SILICON_UPD_ID	0x244450555f495324	/* '$SI_UPD$' */
+
+struct __packed upd_region {
+	u64 signature;				/* Offset 0x0000 */
+	u8 revision;				/* Offset 0x0008 */
+	u8 unused0[7];				/* Offset 0x0009 */
+	u32 memory_upd_offset;			/* Offset 0x0010 */
+	u32 silicon_upd_offset;			/* Offset 0x0014 */
+	u64 unused1;				/* Offset 0x0018 */
+	struct memory_upd memory_upd;		/* Offset 0x0020 */
+	struct silicon_upd silicon_upd;		/* Offset 0x0100 */
+	u16 terminator;				/* Offset 0x02fe */
+};
+
+#define VPD_IMAGE_ID	0x2450534657534224	/* '$BSWFSP$' */
+
+struct __packed vpd_region {
+	u64 sign;				/* Offset 0x0000 */
+	u32 img_rev;				/* Offset 0x0008 */
+	u32 upd_offset;				/* Offset 0x000c */
+};
+
+#endif /* __FSP_VPD_H__ */
--- a/arch/x86/include/asm/arch-braswell/gpio.h
+++ b/arch/x86/include/asm/arch-braswell/gpio.h
@ -0,0 +1,217 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * From coreboot src/soc/intel/braswell/include/soc/gpio.h
+ */
+
+#ifndef _BRASWELL_GPIO_H_
+#define _BRASWELL_GPIO_H_
+
+#include <asm/arch/iomap.h>
+
+enum mode_list {
+	M0,
+	M1,
+	M2,
+	M3,
+	M4,
+	M5,
+	M6,
+	M7,
+	M8,
+	M9,
+	M10,
+	M11,
+	M12,
+	M13,
+};
+
+enum int_select {
+	L0,
+	L1,
+	L2,
+	L3,
+	L4,
+	L5,
+	L6,
+	L7,
+	L8,
+	L9,
+	L10,
+	L11,
+	L12,
+	L13,
+	L14,
+	L15,
+};
+
+enum gpio_en {
+	NATIVE = 0xff,
+	GPIO = 0,	/* Native, no need to set PAD_VALUE */
+	GPO = 1,	/* GPO, output only in PAD_VALUE */
+	GPI = 2,	/* GPI, input only in PAD_VALUE */
+	HI_Z = 3,
+	NA_GPO = 0,
+};
+
+enum gpio_state {
+	LOW,
+	HIGH,
+};
+
+enum en_dis {
+	DISABLE,	/* Disable */
+	ENABLE,		/* Enable */
+};
+
+enum int_type {
+	INT_DIS,
+	TRIG_EDGE_LOW,
+	TRIG_EDGE_HIGH,
+	TRIG_EDGE_BOTH,
+	TRIG_LEVEL,
+};
+
+enum mask {
+	MASKABLE,
+	NON_MASKABLE,
+};
+
+enum glitch_cfg {
+	GLITCH_DISABLE,
+	EN_EDGE_DETECT,
+	EN_RX_DATA,
+	EN_EDGE_RX_DATA,
+};
+
+enum inv_rx_tx {
+	NO_INVERSION = 0,
+	INV_RX_ENABLE = 1,
+	INV_TX_ENABLE = 2,
+	INV_RX_TX_ENABLE = 3,
+	INV_RX_DATA = 4,
+	INV_TX_DATA = 8,
+};
+
+enum voltage {
+	VOLT_3_3,	/* Working on 3.3 Volts */
+	VOLT_1_8,	/* Working on 1.8 Volts */
+};
+
+enum hs_mode {
+	DISABLE_HS,	/* Disable high speed mode */
+	ENABLE_HS,	/* Enable high speed mode */
+};
+
+enum odt_up_dn {
+	PULL_UP,	/* On Die Termination Up */
+	PULL_DOWN,	/* On Die Termination Down */
+};
+
+enum odt_en {
+	DISABLE_OD,	/* On Die Termination Disable */
+	ENABLE_OD,	/* On Die Termination Enable */
+};
+
+enum pull_type {
+	P_NONE  = 0,	/* Pull None */
+	P_20K_L = 1,	/* Pull Down 20K */
+	P_5K_L  = 2,	/* Pull Down  5K */
+	P_1K_L  = 4,	/* Pull Down  1K */
+	P_20K_H = 9,	/* Pull Up 20K */
+	P_5K_H  = 10,	/* Pull Up  5K */
+	P_1K_H  = 12	/* Pull Up  1K */
+};
+
+enum bit {
+	ONE_BIT = 1,
+	TWO_BIT = 3,
+	THREE_BIT = 7,
+	FOUR_BIT = 15,
+	FIVE_BIT = 31,
+	SIX_BIT = 63,
+	SEVEN_BIT = 127,
+	EIGHT_BIT = 255
+};
+
+enum gpe_config {
+	GPE,
+	SMI,
+	SCI,
+};
+
+enum community {
+	SOUTHWEST = 0x0000,
+	NORTH = 0x8000,
+	EAST = 0x10000,
+	SOUTHEAST = 0x18000,
+	VIRTUAL = 0x20000,
+};
+
+#define NA		0xff
+#define TERMINATOR	0xffffffff
+
+#define GPIO_FAMILY_CONF(family_name, park_mode, hysctl, vp18_mode, hs_mode, \
+	odt_up_dn, odt_en, curr_src_str, rcomp, family_no, community_offset) { \
+	.confg = ((((park_mode) != NA) ? park_mode << 26 : 0) | \
+		  (((hysctl) != NA) ? hysctl << 24 : 0) | \
+		  (((vp18_mode) != NA) ? vp18_mode << 21 : 0) | \
+		  (((hs_mode) != NA) ? hs_mode << 19 : 0) | \
+		  (((odt_up_dn) != NA) ? odt_up_dn << 18 : 0) | \
+		  (((odt_en) != NA) ? odt_en << 17 : 0) | \
+		  (curr_src_str)), \
+	.confg_changes = ((((park_mode) != NA) ? ONE_BIT << 26 : 0) | \
+			  (((hysctl) != NA) ? TWO_BIT << 24 : 0) | \
+			  (((vp18_mode) != NA) ? ONE_BIT  << 21 : 0) | \
+			  (((hs_mode) != NA) ? ONE_BIT << 19 : 0) | \
+			  (((odt_up_dn) != NA) ? ONE_BIT << 18 : 0) | \
+			  (((odt_en) != NA) ? ONE_BIT << 17 : 0) | \
+			  (THREE_BIT)), \
+	.misc = ((rcomp == ENABLE) ? 1 : 0) , \
+	.mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
+		     ((family_no != NA) ? (IO_BASE_ADDRESS + community_offset +\
+		     (0x80 * family_no) + 0x1080) : 0) , \
+	.name = 0 \
+}
+
+#define GPIO_PAD_CONF(pad_name, mode_select, mode, gpio_config, gpio_state, \
+	gpio_light_mode, int_type, int_sel, term, open_drain, current_source,\
+	int_mask, glitch, inv_rx_tx, wake_mask, wake_mask_bit, gpe, \
+	mmio_offset, community_offset) { \
+	.confg0 = ((((int_sel) != NA) ? (int_sel << 28) : 0) | \
+		   (((glitch) != NA) ? (glitch << 26) : 0) | \
+		   (((term) != NA) ? (term << 20) : 0) | \
+		   (((mode_select) == GPIO) ? ((mode << 16) | (1 << 15)) : \
+		    ((mode << 16))) | \
+		   (((gpio_config) != NA) ? (gpio_config << 8) : 0) | \
+		   (((gpio_light_mode) != NA) ? (gpio_light_mode << 7) : 0) | \
+		   (((gpio_state) == HIGH) ? 2 : 0)), \
+	.confg0_changes = ((((int_sel) != NA) ? (FOUR_BIT << 28) : 0) | \
+			   (((glitch) != NA) ? (TWO_BIT << 26) : 0) | \
+			   (((term) != NA) ? (FOUR_BIT << 20) : 0) | \
+			   (FIVE_BIT << 15) | \
+			   (((gpio_config) != NA) ? (THREE_BIT << 8) : 0) | \
+			   (((gpio_light_mode) != NA) ? (ONE_BIT << 7) : 0) | \
+			   (((gpio_state) != NA) ? ONE_BIT << 1 : 0)), \
+	.confg1  = ((((current_source) != NA) ? (current_source << 27) : 0) | \
+		    (((inv_rx_tx) != NA) ? inv_rx_tx << 4 : 0) | \
+		    (((open_drain) != NA) ? open_drain << 3 : 0) | \
+		    (((int_type) != NA) ? int_type : 0)), \
+	.confg1_changes = ((((current_source) != NA) ? (ONE_BIT << 27) : 0) | \
+			   (((inv_rx_tx) != NA) ? FOUR_BIT << 4 : 0) | \
+			   (((open_drain) != NA) ? ONE_BIT << 3 : 0) | \
+			   (((int_type) != NA) ? THREE_BIT : 0)), \
+	.community = community_offset, \
+	.mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
+		     ((mmio_offset != NA) ? (IO_BASE_ADDRESS + \
+		      community_offset + mmio_offset) : 0), \
+	.name = 0, \
+	.misc = ((((gpe) != NA) ? (gpe << 0) : 0) | \
+		 (((wake_mask) != NA) ? (wake_mask << 2) : 0) | \
+		 (((int_mask) != NA) ? (int_mask << 3) : 0)) | \
+		 (((wake_mask_bit) != NA) ? (wake_mask_bit << 4) : (NA << 4)) \
+}
+
+#endif /* _BRASWELL_GPIO_H_ */
--- a/arch/x86/include/asm/arch-braswell/iomap.h
+++ b/arch/x86/include/asm/arch-braswell/iomap.h
@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BRASWELL_IOMAP_H_
+#define _BRASWELL_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* Power Management Controller */
+#define PMC_BASE_ADDRESS	0xfed03000
+#define PMC_BASE_SIZE		0x400
+
+/* Power Management Unit */
+#define PUNIT_BASE_ADDRESS	0xfed05000
+#define PUNIT_BASE_SIZE		0x800
+
+/* Intel Legacy Block */
+#define ILB_BASE_ADDRESS	0xfed08000
+#define ILB_BASE_SIZE		0x400
+
+/* SPI Bus */
+#define SPI_BASE_ADDRESS	0xfed01000
+#define SPI_BASE_SIZE		0x400
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS	0xfed1c000
+#define RCBA_BASE_SIZE		0x400
+
+/* IO Memory */
+#define IO_BASE_ADDRESS		0xfed80000
+#define IO_BASE_SIZE		0x4000
+
+/* MODPHY */
+#define MPHY_BASE_ADDRESS	0xfef00000
+#define MPHY_BASE_SIZE		0x100000
+
+/* IO Port bases */
+
+#define ACPI_BASE_ADDRESS	0x400
+#define ACPI_BASE_SIZE		0x80
+
+#define GPIO_BASE_ADDRESS	0x500
+#define GPIO_BASE_SIZE		0x100
+
+#define SMBUS_BASE_ADDRESS	0xefa0
+
+#endif /* _BRASWELL_IOMAP_H_ */
--- a/arch/x86/include/asm/fsp/fsp_api.h
+++ b/arch/x86/include/asm/fsp/fsp_api.h
@ -43,7 +43,8 @@ struct common_buf {
 	u32	stack_top;
 	u32	boot_mode;	/* Current system boot mode */
 	void	*upd_data;	/* User platform configuraiton data region */
-	u32	reserved[7];	/* Reserved */
+	u32	tolum_size;	/* Top of low usable memory size (FSP 1.1) */
+	u32	reserved[6];	/* Reserved */
 };

 enum fsp_phase {
--- a/arch/x86/include/asm/fsp/fsp_hob.h
+++ b/arch/x86/include/asm/fsp/fsp_hob.h
@ -127,6 +127,26 @@ struct hob_guid {
 	/* GUID specific data goes here */
 };

+enum pixel_format {
+	pixel_rgbx_8bpc,	/* RGB 8 bit per color */
+	pixel_bgrx_8bpc,	/* BGR 8 bit per color */
+	pixel_bitmask,
+};
+
+struct __packed hob_graphics_info {
+	phys_addr_t fb_base;	/* framebuffer base address */
+	u32 fb_size;		/* framebuffer size */
+	u32 version;
+	u32 width;
+	u32 height;
+	enum pixel_format pixel_format;
+	u32 red_mask;
+	u32 green_mask;
+	u32 blue_mask;
+	u32 reserved_mask;
+	u32 pixels_per_scanline;
+};
+
 /**
 * get_next_hob() - return a pointer to the next HOB in the HOB list
 *
@ -242,4 +262,18 @@ static inline u16 get_guid_hob_data_size(const struct hob_header *hdr)
 	{ 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \
 	}

+/* The following GUIDs are newly introduced in FSP spec 1.1 */
+
+#define FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID \
+	{ \
+	0x73ff4f56, 0xaa8e, 0x4451, \
+	{ 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } \
+	}
+
+#define FSP_GRAPHICS_INFO_HOB_GUID \
+	{ \
+	0x39f62cce, 0x6825, 0x4669, \
+	{ 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 } \
+	}
+
 #endif
--- a/arch/x86/include/asm/fsp/fsp_infoheader.h
+++ b/arch/x86/include/asm/fsp/fsp_infoheader.h
@ -26,7 +26,14 @@ struct __packed fsp_header {
 	u32	fsp_tempram_init;	/* tempram_init offset */
 	u32	fsp_init;		/* fsp_init offset */
 	u32	fsp_notify;		/* fsp_notify offset */
-	u32	reserved2;
+	u32	fsp_mem_init;		/* fsp_mem_init offset */
+	u32	fsp_tempram_exit;	/* fsp_tempram_exit offset */
+	u32	fsp_silicon_init;	/* fsp_silicon_init offset */
 };

+#define FSP_HEADER_REVISION_1		1
+#define FSP_HEADER_REVISION_2		2
+
+#define FSP_ATTR_GRAPHICS_SUPPORT	(1 << 0)
+
 #endif
--- a/arch/x86/include/asm/fsp/fsp_support.h
+++ b/arch/x86/include/asm/fsp/fsp_support.h
@ -190,6 +190,18 @@ void *fsp_get_nvs_data(const void *hob_list, u32 *len);
 */
 void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len);

+/**
+ * This function retrieves graphics information.
+ *
+ * @hob_list:      A HOB list pointer.
+ * @len:           A pointer to the graphics info HOB length.
+ *                 If the HOB is located, the length will be updated.
+ *
+ * @retval NULL:   Failed to find the graphics info HOB.
+ * @retval others: A pointer to struct hob_graphics_info.
+ */
+void *fsp_get_graphics_info(const void *hob_list, u32 *len);
+
 /**
 * This function overrides the default configurations of FSP.
 *
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@ -77,6 +77,7 @@ struct arch_global_data {
 	uint8_t x86_mask;
 	uint32_t x86_device;
 	uint64_t tsc_base;		/* Initial value returned by rdtsc() */
+	unsigned long clock_rate;	/* Clock rate of timer in Hz */
 	void *new_fdt;			/* Relocated FDT */
 	uint32_t bist;			/* Built-in self test value */
 	enum pei_boot_mode_t pei_boot_mode;
--- a/arch/x86/lib/fsp/Makefile
+++ b/arch/x86/lib/fsp/Makefile
@ -8,4 +8,5 @@ obj-y += cmd_fsp.o
 obj-y += fsp_car.o
 obj-y += fsp_common.o
 obj-y += fsp_dram.o
+obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o
 obj-y += fsp_support.o
--- a/arch/x86/lib/fsp/cmd_fsp.c
+++ b/arch/x86/lib/fsp/cmd_fsp.c
@ -38,17 +38,37 @@ static int do_hdr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	for (i = 0; i < sizeof(hdr->sign); i++)
 		printf("%c", *sign++);
 	printf(", size %d, rev %d\n", hdr->hdr_len, hdr->hdr_rev);
-	printf("Image  : rev %d.%d, id ",
-	       (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff);
+	printf("Image  : rev ");
+	if (hdr->hdr_rev == FSP_HEADER_REVISION_1) {
+		printf("%d.%d",
+		       (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff);
+	} else {
+		printf("%d.%d.%d.%d",
+		       (hdr->img_rev >> 24) & 0xff, (hdr->img_rev >> 16) & 0xff,
+		       (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff);
+	}
+	printf(", id ");
 	for (i = 0; i < ARRAY_SIZE(hdr->img_id); i++)
 		printf("%c", hdr->img_id[i]);
 	printf(", addr 0x%08x, size %d\n", img_addr, hdr->img_size);
+	if (hdr->hdr_rev == FSP_HEADER_REVISION_2) {
+		printf("GFX    :%ssupported\n",
+		       hdr->img_attr & FSP_ATTR_GRAPHICS_SUPPORT ? " " : " un");
+	}
 	printf("VPD    : addr 0x%08x, size %d\n",
 	       hdr->cfg_region_off + img_addr, hdr->cfg_region_size);
 	printf("\nNumber of APIs Supported : %d\n", hdr->api_num);
 	printf("\tTempRamInit : 0x%08x\n", hdr->fsp_tempram_init + img_addr);
 	printf("\tFspInit     : 0x%08x\n", hdr->fsp_init + img_addr);
 	printf("\tFspNotify   : 0x%08x\n", hdr->fsp_notify + img_addr);
+	if (hdr->hdr_rev == FSP_HEADER_REVISION_2) {
+		printf("\tMemoryInit  : 0x%08x\n",
+		       hdr->fsp_mem_init + img_addr);
+		printf("\tTempRamExit : 0x%08x\n",
+		       hdr->fsp_tempram_exit + img_addr);
+		printf("\tSiliconInit : 0x%08x\n",
+		       hdr->fsp_silicon_init + img_addr);
+	}

 	return 0;
 }
--- a/arch/x86/lib/fsp/fsp_graphics.c
+++ b/arch/x86/lib/fsp/fsp_graphics.c
@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <vbe.h>
+#include <video.h>
+#include <asm/fsp/fsp_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pixel {
+	u8 pos;
+	u8 size;
+};
+
+static const struct fsp_framebuffer {
+	struct pixel red;
+	struct pixel green;
+	struct pixel blue;
+	struct pixel rsvd;
+} fsp_framebuffer_format_map[] = {
+	[pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} },
+	[pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} },
+};
+
+static int save_vesa_mode(struct vesa_mode_info *vesa)
+{
+	const struct hob_graphics_info *ginfo;
+	const struct fsp_framebuffer *fbinfo;
+
+	ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL);
+
+	/*
+	 * If there is no graphics info structure, bail out and keep
+	 * running on the serial console.
+	 */
+	if (!ginfo) {
+		debug("FSP graphics hand-off block not found\n");
+		return -ENXIO;
+	}
+
+	vesa->x_resolution = ginfo->width;
+	vesa->y_resolution = ginfo->height;
+	vesa->bits_per_pixel = 32;
+	vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4;
+	vesa->phys_base_ptr = ginfo->fb_base;
+
+	if (ginfo->pixel_format >= pixel_bitmask) {
+		debug("FSP set unknown framebuffer format: %d\n",
+		      ginfo->pixel_format);
+		return -EINVAL;
+	}
+	fbinfo = &fsp_framebuffer_format_map[ginfo->pixel_format];
+	vesa->red_mask_size = fbinfo->red.size;
+	vesa->red_mask_pos = fbinfo->red.pos;
+	vesa->green_mask_size = fbinfo->green.size;
+	vesa->green_mask_pos = fbinfo->green.pos;
+	vesa->blue_mask_size = fbinfo->blue.size;
+	vesa->blue_mask_pos = fbinfo->blue.pos;
+	vesa->reserved_mask_size = fbinfo->rsvd.size;
+	vesa->reserved_mask_pos = fbinfo->rsvd.pos;
+
+	return 0;
+}
+
+static int fsp_video_probe(struct udevice *dev)
+{
+	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct vesa_mode_info *vesa = &mode_info.vesa;
+	int ret;
+
+	printf("Video: ");
+
+	/* Initialize vesa_mode_info structure */
+	ret = save_vesa_mode(vesa);
+	if (ret)
+		goto err;
+
+	/*
+	 * The framebuffer base address in the FSP graphics info HOB reflects
+	 * the value assigned by the FSP. After PCI enumeration the framebuffer
+	 * base address may be relocated. Let's get the updated one from device.
+	 *
+	 * For IGD, it seems to be always on BAR2.
+	 */
+	vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2);
+
+	ret = vbe_setup_video_priv(vesa, uc_priv, plat);
+	if (ret)
+		goto err;
+
+	printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
+	       vesa->bits_per_pixel);
+
+	return 0;
+
+err:
+	printf("No video mode configured in FSP!\n");
+	return ret;
+}
+
+static const struct udevice_id fsp_video_ids[] = {
+	{ .compatible = "fsp-fb" },
+	{ }
+};
+
+U_BOOT_DRIVER(fsp_video) = {
+	.name	= "fsp_video",
+	.id	= UCLASS_VIDEO,
+	.of_match = fsp_video_ids,
+	.probe	= fsp_video_probe,
+};
+
+static struct pci_device_id fsp_video_supported[] = {
+	{ PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, 0xffff00) },
+	{ },
+};
+
+U_BOOT_PCI_DEVICE(fsp_video, fsp_video_supported);
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@ -425,3 +425,10 @@ void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len)

 	return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
 }
+
+void *fsp_get_graphics_info(const void *hob_list, u32 *len)
+{
+	const struct efi_guid guid = FSP_GRAPHICS_INFO_HOB_GUID;
+
+	return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
+}
--- a/board/intel/Kconfig
+++ b/board/intel/Kconfig
@ -18,6 +18,15 @@ config TARGET_BAYLEYBAY
 	  4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC,
 	  PCIe and some other sensor interfaces.

+config TARGET_CHERRYHILL
+	bool "Cherry Hill"
+	help
+	  This is the Intel Cherry Hill Customer Reference Board. It is in a
+	  mini-ITX form factor containing the Intel Braswell SoC, which has
+	  a 64-bit quad-core, single-thread, Intel Atom processor, along with
+	  serial console, 10/100/1000 Ethernet, SD-Card, USB 2/3, SATA, PCIe,
+	  some GPIOs, one HDMI and two DP video out.
+
 config TARGET_COUGARCANYON2
 	bool "Cougar Canyon 2"
 	help
@ -69,6 +78,7 @@ config TARGET_MINNOWMAX
 endchoice

 source "board/intel/bayleybay/Kconfig"
+source "board/intel/cherryhill/Kconfig"
 source "board/intel/cougarcanyon2/Kconfig"
 source "board/intel/crownbay/Kconfig"
 source "board/intel/edison/Kconfig"
--- a/board/intel/cherryhill/Kconfig
+++ b/board/intel/cherryhill/Kconfig
@ -0,0 +1,25 @@
+if TARGET_CHERRYHILL
+
+config SYS_BOARD
+	default "cherryhill"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "braswell"
+
+config SYS_CONFIG_NAME
+	default "cherryhill"
+
+config SYS_TEXT_BASE
+	default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select INTEL_BRASWELL
+	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_MACRONIX
+
+endif
--- a/board/intel/cherryhill/MAINTAINERS
+++ b/board/intel/cherryhill/MAINTAINERS
@ -0,0 +1,6 @@
+INTEL CHERRYHILL BOARD
+M:	Bin Meng <bmeng.cn@gmail.com>
+S:	Maintained
+F:	board/intel/cherryhill/
+F:	include/configs/cherryhill.h
+F:	configs/cherryhill_defconfig
--- a/board/intel/cherryhill/Makefile
+++ b/board/intel/cherryhill/Makefile
@ -0,0 +1,7 @@
+#
+# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= cherryhill.o start.o
--- a/board/intel/cherryhill/cherryhill.c
+++ b/board/intel/cherryhill/cherryhill.c
@ -0,0 +1,596 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/fsp/fsp_support.h>
+
+static const struct gpio_family gpio_family[] = {
+	GPIO_FAMILY_CONF("SOUTHEAST_2_hshvfamily_2x3_rcomp_7_0", NA, 0,
+			 VOLT_1_8, NA, NA, NA, 0, ENABLE, 2, SOUTHEAST),
+
+	/* end of the table */
+	GPIO_FAMILY_CONF("GPIO FAMILY TABLE END", NA, 0,
+			 VOLT_1_8, NA, NA, NA, 0, DISABLE, 0, TERMINATOR),
+};
+
+static const struct gpio_pad gpio_pad[] = {
+	GPIO_PAD_CONF("N37: CX_PRDY_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 29, NA, 0x4c38, NORTH),
+	GPIO_PAD_CONF("N35: CX_PRDY_B_2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 27, NA, 0x4c28, NORTH),
+	GPIO_PAD_CONF("N39: CX_PREQ_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 20, NA, 0x4858, NORTH),
+	GPIO_PAD_CONF("N48: GP_CAMERASB00", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 37, NA, 0x5018, NORTH),
+	GPIO_PAD_CONF("N53: GP_CAMERASB01", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 42, NA, 0x5040, NORTH),
+	GPIO_PAD_CONF("N46: GP_CAMERASB02", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 35, NA, 0x5008, NORTH),
+	GPIO_PAD_CONF("N51: GP_CAMERASB03", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 40, NA, 0x5030, NORTH),
+	GPIO_PAD_CONF("N56: GP_CAMERASB04", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 45, NA, 0x5058, NORTH),
+	GPIO_PAD_CONF("N45: GP_CAMERASB05", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 34, NA, 0x5000, NORTH),
+	GPIO_PAD_CONF("N49: GP_CAMERASB06", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 38, NA, 0x5020, NORTH),
+	GPIO_PAD_CONF("N54: GP_CAMERASB07", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 43, NA, 0x5048, NORTH),
+	GPIO_PAD_CONF("N47: GP_CAMERASB08", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 36, NA, 0x5010, NORTH),
+	GPIO_PAD_CONF("N52: GP_CAMERASB09", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 41, NA, 0x5038, NORTH),
+	GPIO_PAD_CONF("N50: GP_CAMERASB10", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 39, NA, 0x5028, NORTH),
+	GPIO_PAD_CONF("N55: GP_CAMERASB11", GPIO, M1, GPO, LOW,
+		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 44, NA, 0x5050, NORTH),
+	GPIO_PAD_CONF("N00: GPIO_DFX0", NATIVE, M5, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 0, NA, 0x4400, NORTH),
+	GPIO_PAD_CONF("N03: GPIO_DFX1", NATIVE, M5, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 3, NA, 0x4418, NORTH),
+	GPIO_PAD_CONF("N07: GPIO_DFX2", NATIVE, M5, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 2, NA, 0x4438, NORTH),
+	GPIO_PAD_CONF("N01: GPIO_DFX3", NATIVE, M5, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 1, NA, 0x4408, NORTH),
+	GPIO_PAD_CONF("N05: GPIO_DFX4", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 5, NA, 0x4428, NORTH),
+	GPIO_PAD_CONF("N04: GPIO_DFX5", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 4, NA, 0x4420, NORTH),
+	GPIO_PAD_CONF("N08: GPIO_DFX6", NATIVE, M8, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 8, NA, 0x4440, NORTH),
+	GPIO_PAD_CONF("N02: GPIO_DFX7", GPIO, M1, GPO, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 2, NA, 0x4410, NORTH),
+	GPIO_PAD_CONF("N15: GPIO_SUS0", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 9 , NA, 0x4800, NORTH),
+	GPIO_PAD_CONF("N19: GPIO_SUS1", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 13, NA, 0x4820, NORTH),
+	GPIO_PAD_CONF("N24: GPIO_SUS2", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 18, NA, 0x4848, NORTH),
+	GPIO_PAD_CONF("N17: GPIO_SUS3", NATIVE, M6, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 11, NA, 0x4810, NORTH),
+	GPIO_PAD_CONF("N22: GPIO_SUS4", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 16, NA, 0x4838, NORTH),
+	GPIO_PAD_CONF("N20: GPIO_SUS5", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 14, NA, 0x4828, NORTH),
+	GPIO_PAD_CONF("N25: GPIO_SUS6", GPIO, M1, GPI, NA, NA,
+		      TRIG_EDGE_LOW, L9, NA, NA, NA, NON_MASKABLE,
+		      EN_EDGE_RX_DATA, NO_INVERSION,
+		      NA, 19, SCI, 0x4850, NORTH),
+	GPIO_PAD_CONF("N18: GPIO_SUS7", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 12, SMI, 0x4818, NORTH),
+	GPIO_PAD_CONF("N71: HV_DDI0_DDC_SCL", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 57, NA, 0x5458, NORTH),
+	GPIO_PAD_CONF("N66: HV_DDI0_DDC_SDA", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 52, NA, 0x5430, NORTH),
+	GPIO_PAD_CONF("N61: HV_DDI0_HPD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 47, NA, 0x5408, NORTH),
+	GPIO_PAD_CONF("N64: HV_DDI1_HPD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 50, NA, 0x5420, NORTH),
+	GPIO_PAD_CONF("N67: HV_DDI2_DDC_SCL", NATIVE, M3, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 53, NA, 0x5438, NORTH),
+	GPIO_PAD_CONF("N62: HV_DDI2_DDC_SDA", NATIVE, M3, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 48, NA, 0x5410, NORTH),
+	GPIO_PAD_CONF("N68: HV_DDI2_HPD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 54, NA, 0x5440, NORTH),
+	GPIO_PAD_CONF("N65: PANEL0_BKLTCTL", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 51, NA, 0x5428, NORTH),
+	GPIO_PAD_CONF("N60: PANEL0_BKLTEN", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 46, NA, 0x5400, NORTH),
+	GPIO_PAD_CONF("N72: PANEL0_VDDEN", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 58, NA, 0x5460, NORTH),
+	GPIO_PAD_CONF("N63: PANEL1_BKLTCTL", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 49, NA, 0x5418, NORTH),
+	GPIO_PAD_CONF("N70: PANEL1_BKLTEN", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 56, NA, 0x5450, NORTH),
+	GPIO_PAD_CONF("N69: PANEL1_VDDEN", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 55, NA, 0x5448, NORTH),
+	GPIO_PAD_CONF("N32: PROCHOT_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 24, NA, 0x4c10, NORTH),
+	GPIO_PAD_CONF("N16: SEC_GPIO_SUS10", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 10, NA, 0x4808, NORTH),
+	GPIO_PAD_CONF("N21: SEC_GPIO_SUS11", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 15, NA, 0x4830, NORTH),
+	GPIO_PAD_CONF("N23: SEC_GPIO_SUS8", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 17, NA, 0x4840, NORTH),
+	GPIO_PAD_CONF("N27: SEC_GPIO_SUS9", GPIO, M1, GPI, LOW, NA,
+		      TRIG_LEVEL, L15, NA, NA, NA, NON_MASKABLE,
+		      EN_RX_DATA, INV_RX_DATA,
+		      NA, 21, SCI, 0x4860, NORTH),
+	GPIO_PAD_CONF("N31: TCK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 23, NA, 0x4c08, NORTH),
+	GPIO_PAD_CONF("N41: TDI", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 33, NA, 0x4c58, NORTH),
+	GPIO_PAD_CONF("N39: TDO", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 31, NA, 0x4c48, NORTH),
+	GPIO_PAD_CONF("N36: TDO_2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 28, NA, 0x4c30, NORTH),
+	GPIO_PAD_CONF("N34: TMS", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 26, NA, 0x4c20, NORTH),
+	GPIO_PAD_CONF("N30: TRST_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 22, NA, 0x4c00, NORTH),
+
+	GPIO_PAD_CONF("E21: MF_ISH_GPIO_0", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 18, NA, 0x4830, EAST),
+	GPIO_PAD_CONF("E18: MF_ISH_GPIO_1", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 15, NA, 0x4818, EAST),
+	GPIO_PAD_CONF("E24: MF_ISH_GPIO_2", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 21, NA, 0x4848, EAST),
+	GPIO_PAD_CONF("E15: MF_ISH_GPIO_3", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 12, NA, 0x4800, EAST),
+	GPIO_PAD_CONF("E22: MF_ISH_GPIO_4", GPIO, M1, GPI, NA, NA,
+		      NA, L0, NA, NA, NA, NON_MASKABLE, NA, NO_INVERSION,
+		      NA, 19, NA, 0x4838, EAST),
+	GPIO_PAD_CONF("E19: MF_ISH_GPIO_5", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 16, NA, 0x4820, EAST),
+	GPIO_PAD_CONF("E25: MF_ISH_GPIO_6", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 22, NA, 0x4850, EAST),
+	GPIO_PAD_CONF("E16: MF_ISH_GPIO_7", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 13, NA, 0x4808, EAST),
+	GPIO_PAD_CONF("E23: MF_ISH_GPIO_8", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 20, NA, 0x4840, EAST),
+	GPIO_PAD_CONF("E20: MF_ISH_GPIO_9", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 17, NA, 0x4828, EAST),
+	GPIO_PAD_CONF("E26: MF_ISH_I2C1_SDA", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 23, NA, 0x4858, EAST),
+	GPIO_PAD_CONF("E17: MF_ISH_I2C1_SCL", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 14, NA, 0x4810, EAST),
+	GPIO_PAD_CONF("E04: PMU_AC_PRESENT", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 4, NA, 0x4420, EAST),
+	GPIO_PAD_CONF("E01: PMU_BATLOW_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 1, NA, 0x4408, EAST),
+	GPIO_PAD_CONF("E05: PMU_PLTRST_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 5, NA, 0x4428, EAST),
+	GPIO_PAD_CONF("E07: PMU_SLP_LAN_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 7, NA, 0x4438, EAST),
+	GPIO_PAD_CONF("E03: PMU_SLP_S0IX_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 3, NA, 0x4418, EAST),
+	GPIO_PAD_CONF("E00: PMU_SLP_S3_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 0, NA, 0x4400, EAST),
+	GPIO_PAD_CONF("E09: PMU_SLP_S4_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 9, NA, 0x4448, EAST),
+	GPIO_PAD_CONF("E06: PMU_SUSCLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 6, NA, 0x4430, EAST),
+	GPIO_PAD_CONF("E10: PMU_WAKE_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 10, NA, 0x4450, EAST),
+	GPIO_PAD_CONF("E11: PMU_WAKE_LAN_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 11, NA, 0x4458, EAST),
+	GPIO_PAD_CONF("E02: SUS_STAT_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 2, NA, 0x4410, EAST),
+
+	GPIO_PAD_CONF("SE16: SDMMC1_CLK", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 9, NA, 0x4808, SOUTHEAST),
+	GPIO_PAD_CONF("SE23: SDMMC1_CMD", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 16, NA, 0x4840, SOUTHEAST),
+	GPIO_PAD_CONF("SE17: SDMMC1_D0", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 10, NA, 0x4810, SOUTHEAST),
+	GPIO_PAD_CONF("SE24: SDMMC1_D1", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 17, NA, 0x4848, SOUTHEAST),
+	GPIO_PAD_CONF("SE20: SDMMC1_D2", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 13, NA, 0x4828, SOUTHEAST),
+	GPIO_PAD_CONF("SE26: SDMMC1_D3_CD_B", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 19, NA, 0x4858, SOUTHEAST),
+	GPIO_PAD_CONF("SE67: MMC1_D4_SD_WE", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 41, NA, 0x5438, SOUTHEAST),
+	GPIO_PAD_CONF("SE65: MMC1_D5", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 39, NA, 0x5428, SOUTHEAST),
+	GPIO_PAD_CONF("SE63: MMC1_D6", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 37, NA, 0x5418, SOUTHEAST),
+	GPIO_PAD_CONF("SE68: MMC1_D7", NATIVE, M1, NA, NA, HIGH,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 42, NA, 0x5440, SOUTHEAST),
+	GPIO_PAD_CONF("SE69: MMC1_RCLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 43, NA, 0x5448, SOUTHEAST),
+	GPIO_PAD_CONF("SE77: GPIO_ALERT", GPIO, M1, GPI, NA, NA,
+		      TRIG_LEVEL, L2, NA, NA, NA, NON_MASKABLE,
+		      EN_RX_DATA, INV_RX_DATA,
+		      NA, 46, NA, 0x5810, SOUTHEAST),
+	GPIO_PAD_CONF("SE79: ILB_SERIRQ", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 48, NA, 0x5820, SOUTHEAST),
+	GPIO_PAD_CONF("SE51: MF_LPC_CLKOUT0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 32, NA, 0x5030, SOUTHEAST),
+	GPIO_PAD_CONF("SE49: MF_LPC_CLKOUT1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 30, NA, 0x5020, SOUTHEAST),
+	GPIO_PAD_CONF("SE47: MF_LPC_AD0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 28, NA, 0x5010, SOUTHEAST),
+	GPIO_PAD_CONF("SE52: MF_LPC_AD1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 33, NA, 0x5038, SOUTHEAST),
+	GPIO_PAD_CONF("SE45: MF_LPC_AD2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 26, NA, 0x5000, SOUTHEAST),
+	GPIO_PAD_CONF("SE50: MF_LPC_AD3", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 31, NA, 0x5028, SOUTHEAST),
+	GPIO_PAD_CONF("SE46: LPC_CLKRUNB", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 27, NA, 0x5008, SOUTHEAST),
+	GPIO_PAD_CONF("SE48: LPC_FRAMEB", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 29, NA, 0x5018, SOUTHEAST),
+	GPIO_PAD_CONF("SE00: MF_PLT_CLK0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 0, NA, 0x4400, SOUTHEAST),
+	GPIO_PAD_CONF("SE02: MF_PLT_CLK1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 1, NA, 0x4410, SOUTHEAST),
+	GPIO_PAD_CONF("SE07: MF_PLT_CLK2", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 7, NA, 0x4438, SOUTHEAST),
+	GPIO_PAD_CONF("SE04: MF_PLT_CLK3", GPIO, M1, GPI, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 4, NA, 0x4420, SOUTHEAST),
+	GPIO_PAD_CONF("SE03: MF_PLT_CLK4", GPIO, M1, GPO, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 3, NA, 0x4418, SOUTHEAST),
+	GPIO_PAD_CONF("SE06: MF_PLT_CLK5", GPIO, M3, GPO, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 6, NA, 0x4430, SOUTHEAST),
+	GPIO_PAD_CONF("SE83: SUSPWRDNACK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 52, NA, 0x5840, SOUTHEAST),
+	GPIO_PAD_CONF("SE05: PWM0", GPIO, M1, GPO, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 5, NA, 0x4428, SOUTHEAST),
+	GPIO_PAD_CONF("SE01: PWM1", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 1, NA, 0x4408, SOUTHEAST),
+	GPIO_PAD_CONF("SE85: SDMMC3_1P8_EN", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 54, NA, 0x5850, SOUTHEAST),
+	GPIO_PAD_CONF("SE81: SDMMC3_CD_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 50, NA, 0x5830, SOUTHEAST),
+	GPIO_PAD_CONF("SE31: SDMMC3_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 21, NA, 0x4c08, SOUTHEAST),
+	GPIO_PAD_CONF("SE34: SDMMC3_CMD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 24, NA, 0x4c20, SOUTHEAST),
+	GPIO_PAD_CONF("SE35: SDMMC3_D0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 25, NA, 0x4c28, SOUTHEAST),
+	GPIO_PAD_CONF("SE30: SDMMC3_D1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 20, NA, 0x4c00, SOUTHEAST),
+	GPIO_PAD_CONF("SE33: SDMMC3_D2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 23, NA, 0x4c18, SOUTHEAST),
+	GPIO_PAD_CONF("SE32: SDMMC3_D3", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 22, NA, 0x4c10, SOUTHEAST),
+	GPIO_PAD_CONF("SE78: SDMMC3_PWR_EN_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 47, NA, 0x5818, SOUTHEAST),
+	GPIO_PAD_CONF("SE19: SDMMC2_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 12, NA, 0x4820, SOUTHEAST),
+	GPIO_PAD_CONF("SE22: SDMMC2_CMD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 15, NA, 0x4838, SOUTHEAST),
+	GPIO_PAD_CONF("SE25: SDMMC2_D0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 18, NA, 0x4850, SOUTHEAST),
+	GPIO_PAD_CONF("SE18: SDMMC2_D1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 11, NA, 0x4818, SOUTHEAST),
+	GPIO_PAD_CONF("SE21: SDMMC2_D2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 14, NA, 0x4830, SOUTHEAST),
+	GPIO_PAD_CONF("SE15: SDMMC2_D3_CD_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 8, NA, 0x4800, SOUTHEAST),
+	GPIO_PAD_CONF("SE62: SPI1_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 36, NA, 0x5410, SOUTHEAST),
+	GPIO_PAD_CONF("SE61: SPI1_CS0_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 35, NA, 0x5408, SOUTHEAST),
+	GPIO_PAD_CONF("SE66: SPI1_CS1_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 40, NA, 0x5430, SOUTHEAST),
+	GPIO_PAD_CONF("SE60: SPI1_MISO", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 34, NA, 0x5400, SOUTHEAST),
+	GPIO_PAD_CONF("SE64: SPI1_MOSI", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 38, NA, 0x5420, SOUTHEAST),
+	GPIO_PAD_CONF("SE80: USB_OC0_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 49, NA, 0x5828, SOUTHEAST),
+	GPIO_PAD_CONF("SE75: USB_OC1_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 44, NA, 0x5800, SOUTHEAST),
+	GPIO_PAD_CONF("SW02: FST_SPI_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 2, NA, 0x4410, SOUTHWEST),
+	GPIO_PAD_CONF("SW06: FST_SPI_CS0_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 6, NA, 0x4430, SOUTHWEST),
+	GPIO_PAD_CONF("SW04: FST_SPI_CS1_B", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 4, NA, 0x4420, SOUTHWEST),
+	GPIO_PAD_CONF("SW07: FST_SPI_CS2_B", GPIO, M1, GPO, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 7, NA, 0x4438, SOUTHWEST),
+	GPIO_PAD_CONF("SW01: FST_SPI_D0", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 1, NA, 0x4408, SOUTHWEST),
+	GPIO_PAD_CONF("SW05: FST_SPI_D1", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 5, NA, 0x4428, SOUTHWEST),
+	GPIO_PAD_CONF("SW00: FST_SPI_D2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 0, NA, 0x4400, SOUTHWEST),
+	GPIO_PAD_CONF("SW03: FST_SPI_D3", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 3, NA, 0x4418, SOUTHWEST),
+	GPIO_PAD_CONF("SW30: MF_HDA_CLK", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 16, NA, 0x4c00, SOUTHWEST),
+	GPIO_PAD_CONF("SW37: MF_HDA_DOCKENB", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 23, NA, 0x4c38, SOUTHWEST),
+	GPIO_PAD_CONF("SW34: MF_HDA_DOCKRSTB", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 20, NA, 0x4c20, SOUTHWEST),
+	GPIO_PAD_CONF("SW31: MF_HDA_RSTB", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 17, NA, 0x4c08, SOUTHWEST),
+	GPIO_PAD_CONF("SW32: MF_HDA_SDI0", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 18, NA, 0x4c10, SOUTHWEST),
+	GPIO_PAD_CONF("SW36: MF_HDA_SDI1", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 22, NA, 0x4c30, SOUTHWEST),
+	GPIO_PAD_CONF("SW33: MF_HDA_SDO", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 19, NA, 0x4c18, SOUTHWEST),
+	GPIO_PAD_CONF("SW35: MF_HDA_SYNC", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 21, NA, 0x4c28, SOUTHWEST),
+	GPIO_PAD_CONF("SW18: UART1_CTS_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 11, NA, 0x4818, SOUTHWEST),
+	GPIO_PAD_CONF("SW15: UART1_RTS_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 8, NA, 0x4800, SOUTHWEST),
+	GPIO_PAD_CONF("SW16: UART1_RXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 9, NA, 0x4808, SOUTHWEST),
+	GPIO_PAD_CONF("SW20: UART1_TXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 13, NA, 0x4828, SOUTHWEST),
+	GPIO_PAD_CONF("SW22: UART2_CTS_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 15, NA, 0x4838, SOUTHWEST),
+	GPIO_PAD_CONF("SW19: UART2_RTS_B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 12, NA, 0x4820, SOUTHWEST),
+	GPIO_PAD_CONF("SW17: UART2_RXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 10, NA, 0x4810, SOUTHWEST),
+	GPIO_PAD_CONF("SW21: UART2_TXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 14, NA, 0x4830, SOUTHWEST),
+	GPIO_PAD_CONF("SW50: I2C4_SCL", NATIVE, M3, NA, NA, NA,
+		      NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 29, NA, 0x5028, SOUTHWEST),
+	GPIO_PAD_CONF("SW46: I2C4_SDA", NATIVE, M3, NA, NA, NA,
+		      NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 25, NA, 0x5008, SOUTHWEST),
+	GPIO_PAD_CONF("SW49: I2C_NFC_SDA", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 28, NA, 0x5020, SOUTHWEST),
+	GPIO_PAD_CONF("SW52: I2C_NFC_SCL", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 31, NA, 0x5038, SOUTHWEST),
+	GPIO_PAD_CONF("SW77: GP_SSP_2_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 50, NA, 0x5c10, SOUTHWEST),
+	GPIO_PAD_CONF("SW81: GP_SSP_2_FS", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 54, NA, 0x5c30, SOUTHWEST),
+	GPIO_PAD_CONF("SW79: GP_SSP_2_RXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 52, NA, 0x5c20, SOUTHWEST),
+	GPIO_PAD_CONF("SW82: GP_SSP_2_TXD", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
+		      NA, 55, NA, 0x5C38, SOUTHWEST),
+	GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 48, NA, 0x5c00, SOUTHWEST),
+	GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 49, NA, 0x5c08, SOUTHWEST),
+	GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 51, NA, 0x5c18, SOUTHWEST),
+	GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 53, NA, 0x5c28, SOUTHWEST),
+	GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 40, NA, 0x5800, SOUTHWEST),
+	GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 41, NA, 0x5808, SOUTHWEST),
+	GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION,
+		      NA, 43, NA, 0x5818, SOUTHWEST),
+	GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 45, NA, 0x5828, SOUTHWEST),
+	GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION,
+		      NA, 42, NA, 0x5810, SOUTHWEST),
+	GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA,
+		      NA, NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 44, NA, 0x5820, SOUTHWEST),
+	GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 46, NA, 0x5830, SOUTHWEST),
+	GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 47, NA, 0x5838, SOUTHWEST),
+	GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NA,
+		      NA, 48, NA, 0x5c00, SOUTHWEST),
+	GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NA,
+		      NA, 49, NA, 0x5c08, SOUTHWEST),
+	GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NA,
+		      NA, 51, NA, 0x5c18, SOUTHWEST),
+	GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NA,
+		      NA, 53, NA, 0x5c28, SOUTHWEST),
+	GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA,
+		      NA, 40, NA, 0x5800, SOUTHWEST),
+	GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA,
+		      NA, 41, NA, 0x5808, SOUTHWEST),
+	GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, ENABLE, NA, NA, NA, NA,
+		      NA, 43, NA, 0x5818, SOUTHWEST),
+	GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NA,
+		      NA, 45, NA, 0x5828, SOUTHWEST),
+	GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, ENABLE, NA, NA, NA, NA,
+		      NA, 42, NA, 0x5810, SOUTHWEST),
+	GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA,
+		      NA, NA, NA, P_20K_H, NA, NA, NA, NA, NA,
+		      NA, 44, NA, 0x5820, SOUTHWEST),
+	GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NA,
+		      NA, 46, NA, 0x5830, SOUTHWEST),
+	GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA,
+		      NA, NA, P_20K_H, NA, NA, NA, NA, NA,
+		      NA, 47, NA, 0x5838, SOUTHWEST),
+
+	/* end of the table */
+	GPIO_PAD_CONF("GPIO PAD TABLE END", NATIVE, M1, NA, NA, NA,
+		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
+		      NA, 0, NA, 0, TERMINATOR),
+};
+
+void update_fsp_gpio_configs(const struct gpio_family **family,
+			     const struct gpio_pad **pad)
+{
+	*family = gpio_family;
+	*pad = gpio_pad;
+}
--- a/board/intel/cherryhill/start.S
+++ b/board/intel/cherryhill/start.S
@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+	jmp	early_board_init_ret
--- a/common/Kconfig
+++ b/common/Kconfig
@ -46,15 +46,6 @@ config BOOTSTAGE_REPORT
 		 29,916,167 26,005,792  bootm_start
 		 30,361,327    445,160  start_kernel

-config BOOTSTAGE_USER_COUNT
-	int "Number of boot ID numbers available for user use"
-	default 20
-	help
-	  This is the number of available user bootstage records.
-	  Each time you call bootstage_mark(BOOTSTAGE_ID_ALLOC, ...)
-	  a new ID will be allocated from this stash. If you exceed
-	  the limit, recording will stop.
-
 config BOOTSTAGE_RECORD_COUNT
 	int "Number of boot stage records to store"
 	default 30
@ -62,6 +53,13 @@ config BOOTSTAGE_RECORD_COUNT
 	  This is the size of the bootstage record list and is the maximum
 	  number of bootstage records that can be recorded.

+config SPL_BOOTSTAGE_RECORD_COUNT
+	int "Number of boot stage records to store for SPL"
+	default 5
+	help
+	  This is the size of the bootstage record list and is the maximum
+	  number of bootstage records that can be recorded.
+
 config BOOTSTAGE_FDT
 	bool "Store boot timing information in the OS device tree"
 	depends on BOOTSTAGE
--- a/common/board_f.c
+++ b/common/board_f.c
@ -952,6 +952,9 @@ void board_init_f_r(void)
 	 * UART if available.
 	 */
 	gd->flags &= ~GD_FLG_SERIAL_READY;
+#ifdef CONFIG_TIMER
+	gd->timer = NULL;
+#endif

 	/*
 	 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
--- a/common/bootstage.c
+++ b/common/bootstage.c
@ -18,7 +18,7 @@
 DECLARE_GLOBAL_DATA_PTR;

 enum {
-	RECORD_COUNT = CONFIG_BOOTSTAGE_RECORD_COUNT,
+	RECORD_COUNT = CONFIG_VAL(BOOTSTAGE_RECORD_COUNT),
 };

 struct bootstage_record {
@ -327,7 +327,7 @@ void bootstage_report(void)
 	}
 	if (data->rec_count > RECORD_COUNT)
 		printf("Overflowed internal boot id table by %d entries\n"
-		       "- please increase CONFIG_BOOTSTAGE_RECORD_COUNT\n",
+		       "Please increase CONFIG_(SPL_)BOOTSTAGE_RECORD_COUNT\n",
 		       data->rec_count - RECORD_COUNT);

 	puts("\nAccumulated time:\n");
@ -456,7 +456,7 @@ int bootstage_unstash(const void *base, int size)

 	if (data->rec_count + hdr->count > RECORD_COUNT) {
 		debug("%s: Bootstage has %d records, we have space for %d\n"
-			"- please increase CONFIG_BOOTSTAGE_USER_COUNT\n",
+			"Please increase CONFIG_(SPL_)BOOTSTAGE_RECORD_COUNT\n",
 		      __func__, hdr->count, RECORD_COUNT - data->rec_count);
 		return -ENOSPC;
 	}
--- a/configs/cherryhill_defconfig
+++ b/configs/cherryhill_defconfig
@ -0,0 +1,36 @@
+CONFIG_X86=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_DEFAULT_DEVICE_TREE="cherryhill"
+CONFIG_TARGET_CHERRYHILL=y
+CONFIG_DEBUG_UART=y
+CONFIG_SMP=y
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_RTL8169=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@ -67,6 +67,7 @@ CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPL_TIMER=y
+CONFIG_TIMER_EARLY=y
 CONFIG_TPM_TIS_LPC=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@ -49,6 +49,7 @@ CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_SYS_NS16550=y
+CONFIG_TIMER_EARLY=y
 CONFIG_TPM_TIS_LPC=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@ -7,7 +7,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_BOOTSTAGE_USER_COUNT=32
 CONFIG_BOOTSTAGE_FDT=y
 CONFIG_BOOTSTAGE_STASH=y
 CONFIG_BOOTSTAGE_STASH_ADDR=0x0
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@ -7,7 +7,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_BOOTSTAGE_USER_COUNT=32
 CONFIG_BOOTSTAGE_FDT=y
 CONFIG_BOOTSTAGE_STASH=y
 CONFIG_BOOTSTAGE_STASH_ADDR=0x0
--- a/configs/sandbox_noblk_defconfig
+++ b/configs/sandbox_noblk_defconfig
@ -6,7 +6,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_BOOTSTAGE_USER_COUNT=32
 CONFIG_BOOTSTAGE_FDT=y
 CONFIG_BOOTSTAGE_STASH=y
 CONFIG_BOOTSTAGE_STASH_ADDR=0x0
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@ -13,7 +13,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_BOOTSTAGE_USER_COUNT=32
 CONFIG_BOOTSTAGE_FDT=y
 CONFIG_BOOTSTAGE_STASH=y
 CONFIG_BOOTSTAGE_STASH_ADDR=0x0
--- a/doc/README.x86
+++ b/doc/README.x86
@ -26,6 +26,7 @@ In this case, known as bare mode, from the fact that it runs on the
 are supported:

   - Bayley Bay CRB
+   - Cherry Hill CRB
   - Congatec QEVAL 2.0 & conga-QA3/E3845
   - Cougar Canyon 2 CRB
   - Crown Bay CRB
@ -332,6 +333,35 @@ the default value 0xfffc0000.

 ---

+Intel Cherry Hill specific instructions for bare mode:
+
+This uses Intel FSP for Braswell platform. Download it from Intel FSP website,
+put the .fd file to the board directory and rename it to fsp.bin.
+
+Extract descriptor.bin and me.bin from the original BIOS on the board using
+ifdtool and put them to the board directory as well.
+
+Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS
+image for the integrated graphics device. Instead a new binary called Video
+BIOS Table (VBT) is shipped. Put it to the board directory and rename it to
+vbt.bin if you want graphics support in U-Boot.
+
+Now you can build U-Boot and obtain u-boot.rom
+
+$ make cherryhill_defconfig
+$ make all
+
+An important note for programming u-boot.rom to the on-board SPI flash is that
+you need make sure the SPI flash's 'quad enable' bit in its status register
+matches the settings in the descriptor.bin, otherwise the board won't boot.
+
+For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the
+status register by DediProg in: Config > Modify Status Register > Write Status
+Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it
+persists in SPI flash part regardless of the u-boot.rom image burned.
+
+---
+
 Intel Galileo instructions for bare mode:

 Only one binary blob is needed for Remote Management Unit (RMU) within Intel
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@ -18,7 +18,7 @@
 #include <asm/msr.h>
 #include <asm/u-boot-x86.h>

-#define MAX_NUM_FREQS	8
+#define MAX_NUM_FREQS	9

 DECLARE_GLOBAL_DATA_PTR;

@ -40,17 +40,20 @@ struct freq_desc {

 static struct freq_desc freq_desc_tables[] = {
 	/* PNW */
-	{ 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 } },
+	{ 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
 	/* CLV+ */
-	{ 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },
+	{ 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
 	/* TNG - Intel Atom processor Z3400 series */
-	{ 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } },
+	{ 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
 	/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
-	{ 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },
+	{ 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
 	/* ANN - Intel Atom processor Z3500 series */
-	{ 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } },
+	{ 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
+	/* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
+	{ 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
+			80000, 93300, 90000, 88900, 87500 } },
 	/* Ivybridge */
-	{ 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
+	{ 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
 };

 static int match_cpu(u8 family, u8 model)
@ -328,17 +331,17 @@ static int tsc_timer_get_count(struct udevice *dev, u64 *count)
 	return 0;
 }

-static int tsc_timer_probe(struct udevice *dev)
+static void tsc_timer_ensure_setup(void)
 {
-	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-
+	if (gd->arch.tsc_base)
+		return;
 	gd->arch.tsc_base = rdtsc();

 	/*
 	 * If there is no clock frequency specified in the device tree,
 	 * calibrate it by ourselves.
 	 */
-	if (!uc_priv->clock_rate) {
+	if (!gd->arch.clock_rate) {
 		unsigned long fast_calibrate;

 		fast_calibrate = cpu_mhz_from_msr();
@ -348,12 +351,32 @@ static int tsc_timer_probe(struct udevice *dev)
 				panic("TSC frequency is ZERO");
 		}

-		uc_priv->clock_rate = fast_calibrate * 1000000;
+		gd->arch.clock_rate = fast_calibrate * 1000000;
 	}
+}
+
+static int tsc_timer_probe(struct udevice *dev)
+{
+	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	tsc_timer_ensure_setup();
+	uc_priv->clock_rate = gd->arch.clock_rate;

 	return 0;
 }

+unsigned long notrace timer_early_get_rate(void)
+{
+	tsc_timer_ensure_setup();
+
+	return gd->arch.clock_rate;
+}
+
+u64 notrace timer_early_get_count(void)
+{
+	return rdtsc() - gd->arch.tsc_base;
+}
+
 static const struct timer_ops tsc_timer_ops = {
 	.get_count = tsc_timer_get_count,
 };
--- a/include/bootstage.h
+++ b/include/bootstage.h
@ -12,11 +12,6 @@
 #ifndef _BOOTSTAGE_H
 #define _BOOTSTAGE_H

-/* Define this for host tools */
-#ifndef CONFIG_BOOTSTAGE_USER_COUNT
-#define CONFIG_BOOTSTAGE_USER_COUNT	20
-#endif
-
 /* Flags for each bootstage record */
 enum bootstage_flags {
 	BOOTSTAGEF_ERROR	= 1 << 0,	/* Error record */
@ -208,7 +203,6 @@ enum bootstage_id {

 	/* a few spare for the user, from here */
 	BOOTSTAGE_ID_USER,
-	BOOTSTAGE_ID_COUNT = BOOTSTAGE_ID_USER + CONFIG_BOOTSTAGE_USER_COUNT,
 	BOOTSTAGE_ID_ALLOC,
 };

--- a/include/configs/cherryhill.h
+++ b/include/configs/cherryhill.h
@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(2 << 20)
+
+#define CONFIG_STD_DEVICES_SETTINGS	"stdin=usbkbd,serial\0" \
+					"stdout=vidconsole,serial\0" \
+					"stderr=vidconsole,serial\0"
+
+/* Environment configuration */
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#define CONFIG_ENV_OFFSET		0x005f0000
+
+#endif	/* __CONFIG_H */
--- a/tools/binman/etype/intel_vbt.py
+++ b/tools/binman/etype/intel_vbt.py
@ -0,0 +1,14 @@
+#
+# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Entry-type module for Intel Video BIOS Table binary blob
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_intel_vbt(Entry_blob):
+    def __init__(self, image, etype, node):
+        Entry_blob.__init__(self, image, etype, node)
--- a/tools/binman/func_test.py
+++ b/tools/binman/func_test.py
@ -38,6 +38,7 @@ X86_START16_DATA    = 'start16'
 U_BOOT_NODTB_DATA   = 'nodtb with microcode pointer somewhere in here'
 FSP_DATA            = 'fsp'
 CMC_DATA            = 'cmc'
+VBT_DATA            = 'vbt'

 class TestFunctional(unittest.TestCase):
    """Functional tests for binman
@ -74,6 +75,7 @@ class TestFunctional(unittest.TestCase):
        TestFunctional._MakeInputFile('u-boot-nodtb.bin', U_BOOT_NODTB_DATA)
        TestFunctional._MakeInputFile('fsp.bin', FSP_DATA)
        TestFunctional._MakeInputFile('cmc.bin', CMC_DATA)
+        TestFunctional._MakeInputFile('vbt.bin', VBT_DATA)
        self._output_setup = False

        # ELF file with a '_dt_ucode_base_size' symbol
@ -801,6 +803,11 @@ class TestFunctional(unittest.TestCase):
        self.assertEqual(FSP_DATA, data[:len(FSP_DATA)])

    def testPackCmc(self):
-        """Test that an image with a FSP binary can be created"""
+        """Test that an image with a CMC binary can be created"""
        data = self._DoReadFile('43_intel-cmc.dts')
        self.assertEqual(CMC_DATA, data[:len(CMC_DATA)])
+
+    def testPackVbt(self):
+        """Test that an image with a VBT binary can be created"""
+        data = self._DoReadFile('46_intel-vbt.dts')
+        self.assertEqual(VBT_DATA, data[:len(VBT_DATA)])
--- a/tools/binman/test/46_intel-vbt.dts
+++ b/tools/binman/test/46_intel-vbt.dts
@ -0,0 +1,14 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	binman {
+		size = <16>;
+
+		intel-vbt {
+			filename = "vbt.bin";
+		};
+	};
+};