Synchronize the Linux Device Tree for Amlogic Meson GX boards from Linux 4.17.0
This will enable USB on Amlogic Meson GXL Boards like Khadas VIM, P212 or
LibreTech-CC.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
After the commit 265edc03d5 ("fs/fat: Clean up open-coded sector
<-> cluster conversions"), it is hung up writing new file to FAT16
disk with more than 19 files in armv7. It is because result value
of sect_to_cluster() is not proper by casting from signed value to
unsigned value. Fix the wrong casting of sect_to_cluster().
Reported-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0
clock when OHCI1 is in use.
Fixes commit dd3228170a ("usb: sunxi: Switch to use generic-phy")
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Add Panther Point chipset interrupt pin/PIRQ information, and
enable the generation of PIRQ routing table and MP table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently both pirq_reg_to_linkno() and pirq_linkno_to_reg() assume
consecutive PIRQ routing control registers. But this is not always
the case on some platforms. Introduce a new device tree property
intel,pirq-regmap to describe how the PIRQ routing register offset
is mapped to the link number and adjust the irq router driver to
utilize the mapping.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The "intel,pirq-link" property in Intel IRQ router's dt bindings
has two cells, where the second one represents the number of PIRQ
links on the platform. However current driver does not parse this
information from device tree. This adds the codes to do the parse
and save it for future use.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If GetMemoryMap() fails, we really want to know EFI_BITS_PER_LONG
instead of BITS_PER_LONG. A space and LF are added in places where
error message is output to improve readability.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If U-Boot gets used as coreboot payload all pci resources got
assigned by coreboot. If a dts without any pci ranges gets used
the dm is not able to access pci device memory. To get things
working make use of a 1:1 mapping for bus <-> phy addresses.
This change makes it possible to get the e1000 U-Boot driver
working on a sandybridge device where U-Boot is used as coreboot
payload.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed 'u-boot' in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If we use U-Boot as coreboot payload with a generic dts without
any ranges specified we fail in pci pre_probe and our pci bus
is not usable.
So convert decode_regions(..) into a void function and do the simple
error handling there.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed 'u-boot' in the commit message and checkpatch warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Attempting to use a toolchain that is preconfigured to generate code
for the 32-bit architecture (i386), for example, the i386-linux-gcc
toolchain on kernel.org, to compile the 64-bit EFI payload does not
build. This updates the makefile fragments to ensure '-m64' is passed
to toolchain when building the 64-bit EFI payload stub codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The EFI application does not boot currently. It's due to the call
to syscon_get_by_driver_data() in cpu_init_r() maps to nowhere as
CONFIG_SYSCON is not included in the configuration.
EFI application is built as a shared library, so GCC won't complain
during the build process if some symbols are not found. GCC will
simply put these symbols into the .plt section and expect dynamic
loader to fix these up.
While we are here, remove some commands and drivers that are not
needed at present.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The pinctrl_ich6 driver is currently unconditionally built for all
x86 boards. Let's use a Kconfig option to control the build.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
LINK_V2N and LINK_N2V are currently defines, so they cannot handle
complex logics. Change to inline functions for future extension.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present there are 3 irq router drivers. One is the common one
and the other two are chipset specific for queensbay and quark.
However these are really the same drivers as the core logic is
the same. The two chipset specific drivers configure some registers
that are outside the irq router block which should really be part
of the chipset initialization.
Now we remove these specific drivers and make all x86 boards use
the common one.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This enables the 206ax cpu driver on Intel Cougar Canyon 2 board,
so that SMP can be supported too.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The 206ax cpu driver does not require pre-relocation flag to work.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present this 206ax cpu driver is only built when FSP is not used.
This updates the Makefile to enable the build for both cases.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As README.x86 already mentions, there are two SPI flashes mounted
on Intel Cougar Canyon 2 board, called SPI-0 and SPI-1 respectively.
SPI-0 stores the flash descriptor and the ME firmware. SPI-1 stores
the actual BIOS image which is U-Boot. Building a single image with
both ME firmware and U-Boot does not make sense.
This also describes the exact flash location where the u-boot.rom
should be programmed in the documentation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It turns out that like Braswell, Intel FSP for IvyBridge requires
SPI controller settings to be locked down, as the U-Boot ICH SPI
driver fails with the following message on Cougar Canyon 2 board:
"ICH SPI: Opcode 9f not found"
Update the SPI node property to indicate this fact.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The Panther Point chipset connected to Ivybridge has xHC integrated,
imply it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This fixes the following compiler warning:
"warning: cast from pointer to integer of different size
[-Wpointer-to-int-cast]"
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The guaranteed vid bit ranges in IACORE_VIDS MSR is actually
[22:16]. This corrects the comment for it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The commit
f9a88a4c1cd0 ("iASL: Enhance the -tc option (create AML hex file in C)")
in ACPICA project changed a template of the variable that is used
in the generated C-file. Now, instead of hard coded "AmlCode" the
"%s_aml_code" is in use, where the prefix is a lowered case base
name of the output file. In our case it will be "dsdt" producing
a name as "dsdt_aml_code".
The quick solution is to call sed which replaces new name by the
old one to keep compatibility with old version of iASL.
The long term solution would be to modify code to use the new name
because it is more scalable.
Cc: Robert Moore <robert.moore@intel.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Evan Lloyd <evan.lloyd@arm.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed two sentences in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Starting with cpuid level 0x16 (Skylake-based processors)
it is possible to get CPU base freq via cpuid.
This fixes booting on a skylake based system.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed wrong indention of labels]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
generic.h has changed in Linux and new addtionals functions were
added.
This commit takes the latest and greatest from Linux (v4.17-rc5)
to aid with porting drivers that utilize these functions.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
This commit removes text that is exact duplicated of the text above.
Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
In upstream Linux kernel, the fdtfile
for this specific board is called am335x-wega-rdk.dtb
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
The helios4 is built on the SolidRun Armada 38x SOM.
The port os based on the ClearFog board, using information from
https://github.com/helios-4/u-boot-marvell as well as dtb input
from https://github.com/helios-4/linux-marvell
Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Signed-off-by: Dennis Gilmore <dgilmore@redhat.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Added the following:
1. defconfig for LS1012AFRWY Secure boot
2. PfE Validation support
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
FRWY-LS1012A belongs to LS1012A family with features 2 1G SGMII PFE
MAC, Micro SD, USB 3.0, DDR, QuadSPI, Audio, UART.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
[yorks: rebase and fix SPDX tag]
[yorks: fix board/freescale/ls1012afrdm/Kconfig]
Reviewed-by: York Sun <york.sun@nxp.com>
PPA firmware and header address may vary depending upon different
boards, configure ppa firmware and header address in board specific
Kconfig.
Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As per updated hardware documentation for
lsch3 based chips like LS2088A, 0.9v support
has been added in possible supported SoC volatges
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
After the commit 9b643e312d ("treewide: replace with error() with
pr_err()"), there are some pr_err() with no line break. Add missing
line breaks.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
After the commit 9b643e312d ("treewide: replace with error() with
pr_err()"), there are some pr_err() with no line break. Add missing
line breaks.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
If building envtools, there is env directory in tools directory.
Mafe the get_default_envs.sh script exclude tools/env directory.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Add timestamp to each iotrace record to aid in debugging
of IO timing access bugs.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
