Some rams (Micron for example) return duplicate mr data on all byte lanes.
Users of the get_mr function currently don't deal with this duplicated
data gracefully. This patch detects the duplicated data and returns only
the expected 8 bit mr data.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Errata ID:i727
Description: The refresh rate is programmed in the EMIF_SDRAM_REF_CTRL[15:0]
REG_REFRESH_RATE parameter taking into account frequency of the device.
When a warm reset is applied on the system, the OMAP processor restarts
with another OPP and so frequency is not the same. Due to this frequency
change, the refresh rate will be too low and could result in an unexpected
behavior on the memory side.
Workaround:
The workaround is to force self-refresh when coming back from the warm reset
with the following sequence:
• Set EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
• Set EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM to 0x0
• Do a dummy read (loads automatically new value of sr_tim)
This will reduce the risk of memory content corruption, but memory content
can't be guaranteed after a warm reset.
This errata is impacted on
OMAP4430: 1.0, 2.0, 2.1, 2.2, 2.3
OMAP4460: 1.0, 1.1
OMAP4470: 1.0
OMAP5430: 1.0
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
EMIF and DDR device state are preserved in warmreset. Redoing the full
initialisation would cause unexpected behaviour. Do only partial
initialisation to account for frequency change.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
Certain modules are not affected by means of
a warm reset and need not be configured again.
Adding an API to detect the reset reason warm/cold.
This will be used to skip the module configurations
that are retained across a warm reset.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Interrupts and exceptions doesn't work in relocated code.
It badly use IRQ_STACK_START_IN in rom area as interrupt stack.
It is because the vecotr table is not moved to ram area.
This patch moves vector table before jumping relocated code.
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Tested-by: Tom Rini <trini@ti.com>
So that they can be redefined by some boards specific values.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
These two function nows ensure that the MPP is configured correctly for
the SPI controller before any SPI access, and restore the initial
configuration when the access is over.
Since the used pins for the SPI controller can differ (2 possibilities
for each signal), the used pins are configured with CONFIG_SYS_KW_SPI_MPP.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
If a second non NULL argument is given to the kirkwood_mpp_conf
function, it will be used to store the current configuration of the MPP
registers. mpp_save must be a preallocated table of the same size as
mpp_list and it must be zero terminated as well.
A later call to kirkwood_mpp_conf function with this saved list as first
(mpp_conf) argment will set the configuration back.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Enable new PIO feature supported by Atmel SoC.
Using CPU_HAS_PIO3 micro to enable PIO new feature.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The commit "i.mx: fsl_esdhc: add the i.mx6q support" (4692708d) introduces
support for the i.MX6Q MMC host controller USDHC.
MXC_IPG_PERCLK sets the clock to 66MHz. This seems to be the default clock
of the ESDHC IP found in < i.MX6 silicon. However, the default clock for the USDHC
IP found in i.MX6 is 200MHz (MXC_ESDHC_CLK). This difference will cause a 3 times
higher clock on SD_CLK than expected (see fsl_esdh.c -> set_sysctl()).
Signed-off-by: Michael Langer <michael.langer@de.bosch.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <r64343@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This function can be overridden at run-time and allows implementors
of new boards based on the i.MX28 chip to fine-tune the memory params.
It is possible to write into the dram_vals array because when the SPL
runs, it is located SRAM. Therefore the location is writable. There is
no possibility of these data to be read-only.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
The macro mistakenly referred to 32bit struct instead of 8bit one.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
SATA_ALT_REF_CLK field corresponds to bits 1 and 2 of offset 0x180c.
Fix the mask for these bits.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
If one PAD does not have mux or pad config register, we need
set the NO_MUX_I/NO_PAD_I to 0, the old value is not correct
Signed-off-by: Jason Liu <jason.hui@linaro.org>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
This patch performs the pinmux configuration in a common file.
As of now only EXYNOS5 pinmux for SDMMC, UART and Ethernet is
supported.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Since Exynos architecture have new SoCs,
need to fix cpuinfo correctly.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Chander Kashyap <chander.kashyap@linaro.org>
To meet certain timing requirements on the lpddr2 cmd and data phy
interfaces ,lpddr iopads have to be configured as differential buffers
and a Vref has to be internally generated and provided to these buffers.
Correcting the above settings here.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
In OMAP5432 EMIF controlller supports DDR3 device.
This patch adds support for ddr3 device intialization and configuration.
Initialization sequence is done as specified in JEDEC specs.
This also adds support for ddr3 leveling.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Previously, only the low 5 bits (NCH) were being transfered
from DDRVTPR to DDRVTPIOCR, the bits 5-9 where zeroed.
VTP_RECAL should be bit 15, not 18.
The only mainline board affected by this change is davinci_sonata.
The other Davinci boards define CONFIG_SKIP_LOWLEVEL_INIT.
However, if the program that loads u-boot on these boards
copied the code from u-boot, they will need fixed as well.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Please get tested by acks before applying, where tested by
means an overnight memory test.
Thanks
Troy
get_ram_size checks the given memory range for valid ram,
but expects the size of memory to be aligned to the power
of 2. In case of OMAP5 evm board the memory available is
2GB - 16MB(used for TRAP section) = 2032MB.
So always ensure that the size of memory used for testing is
aligned to the power of 2.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The unmapped entries in tiler space are set with
values 0xFF. So creating a DMM section of
size 16MB at 0xFF000000 with ADDRSPACE set to 0x2.
This way all the unmapped entry accesses to tiler
will be trapped by the EMIF and a error response
is sent to the L3 interconnect. L3 errors are
inturn reported to MPU.
Note that here the tiler trap section is overlapping
with the actual ddr physical space and we lose 16MB
out of the total 2GB.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
The DMM sections can be overlapping with each other, with
sections 3 to 0 having the highest to lowest priority in that
order. There could also be a section that is used trap the
unmapped Tiler entries and this trap section could be
overlapping with the actual sdram area.
So take care of the above scenarios while calculating the
size of the actual ram.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Walk the BIT and BCT to find the ODMDATA word in the
CustomerData field and put it into Scratch20 reg for
use by kernel, etc.
Built all Tegra builds OK; Booted on Seaboard and saw
ODMDATA in PMC scratch20 was the same as the value in my
burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities
will have to specify the odmdata (nvflash --odmdata n) on
the command line or via a cfg file, or built in to their
BCT.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
In anticipation of Tegra3 support, continue removing/renaming
Tegra2-specific files. No functional changes (yet).
Updated copyrights to 2012.
Signed-off-by: Tom Warren <twarren@nvidia.com>
In anticipation of Tegra3 support, start removing/renaming
Tegra2-specific files. No functional changes (yet).
Also updated copyright to 2012.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Override -march setting for tegra to -march=armv4t for files that are
necessary for low level init on tegra.
The recent change to use -march=armv7-a for armv7 caused a regression
on tegra because tegra starts boot on a arm7tdmi processor before
transferring control to the cortex-a9. While still executing on the
arm7tdmi there are calls to getenv_ulong() and memset() that cause an
illegal instruction exception if compiled for armv7.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Correct this warning seen by Albert:
ap20.c:44:18: warning: array subscript is above array bounds
There is a subtle bug here which currently causes no errors, but might
in future if people use PCI or the 32KHz clock. So take the opportunity
to correct the logic now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This is based on top of:
tegra: add alternate UART1 funcmux entry
tegra: add UART1 on GPU funcmux entry
v2: remove enum change
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Tom Warren <twarren@nvidia.com>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
(In at least some configurations) Whistler uses UART1 on pingroups
UAA, UAB.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass's proposal to fix this on Seaboard was NAK'd, so I
removed his NS16550 references and added a small delay before
SPI/UART muxing. Tested on my Seaboard with large SPI reads/writes
and saw no corruption (crc's matched) and no spurious comm chars.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
We provide a default table of { 9600, 19200, 38400, 57600, 115200 }
in <config_fallbacks.h> which mkconfig places after <configs/...h> in
the generated config file. This is used when a board has not set its
own table.
Signed-off-by: Tom Rini <trini@ti.com>
* 'master' of git://git.denx.de/u-boot-video:
video: atmel/lcd: add LCD driver for new Atmel SoC
video: cfb_console: flush dcache for frame buffer in DRAM
cfb_console: Ignore bell character
cfb_console: Add console_clear_line function
cfb_console: Fix function console_back
omap3_dss: cosmetic changes
omap3_dss: add optional framebuffer
mx53loco: Add LCD support
mx5: Rename mx51_fb_init()
mx53: Allow IPUv3 driver to also work on mx53
mx51evk: Add LCD support
EXYNOS: display 32bpp bitmap TIZEN logo
create lib/tizen directory
LCD: display 32bpp decompressed bitmap image
common/lcd.c: reduce one CONFIG_LCD_LOGO ifdef
common/lcd.c: reduce some CONFIG_LCD_*_LOGO ifdefs
common/lcd.c: use ARRAY_SIZE
cmd_bmp.c: make bmp_display() usable by drivers or board code
LCD: support another s6e8ax0 panel type
LCD: change s6e8ax0 panel gamma value
include/video.h: drop unused video_printf()
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'master' of git://git.denx.de/u-boot-mips:
MIPS: board.c: move extern declarations to u-boot-mips.h
MIPS: bootm_qemu_mips.c: make checkpatch.pl clean
MIPS: bootm.c: make checkpatch.pl clean
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'master' of git://git.denx.de/u-boot-sh:
sh/ap_sh4a_4a: Fix typo of operator in ET0_ETXD4
sh: Add SH7269 device and RSK2+SH7269 board
sh: Set CONFIG_SH_ETHER_PHY_MODE and CONFIG_SH_ETHER_SH7734_MII to boards with sh_eth
sh: Add support for AP-SH4A-4A board
sh: Add register definition of PFC for SH7734
sh: r0p7734: Add support I2C controller
sh: Add bit control functions
sh: Add support for r0p7734 board
sh: Add support Renesas SH7734
Signed-off-by: Wolfgang Denk <wd@denx.de>
This patch conditionally defines flush_dcache_range() and
invalidate_dcache_range() on MPC8xxx, to avoid EHCI complaining,
resulting in the following output:
$ ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- ./MAKEALL MPC8572DS
Configuring for MPC8572DS board...
make: *** [u-boot] Error 1
powerpc-linux-gnu-size: './u-boot': No such file
e1000.c: In function ‘e1000_initialize’:
e1000.c:5264:13: warning: assignment from incompatible pointer type [enabled by default]
tsec.c: In function ‘tsec_initialize’:
tsec.c:638:12: warning: assignment from incompatible pointer type [enabled by default]
drivers/usb/host/libusb_host.o: In function `ehci_td_buffer':
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:186: undefined reference to `flush_dcache_range'
drivers/usb/host/libusb_host.o: In function `ehci_submit_async':
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:346: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:348: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:349: undefined reference to `flush_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:372: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:374: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:376: undefined reference to `invalidate_dcache_range'
/home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:386: undefined reference to `invalidate_dcache_range'
make: *** [u-boot] Error 1
--------------------- SUMMARY ----------------------------
Boards compiled: 1
Boards with errors: 1 ( MPC8572DS )
----------------------------------------------------------
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
