With DDR4, Intel SOCs take quite a long time to init their memory. During
this time, if the user is watching, it looks like SPL has hung. Add a
message in this case.
This works by adding a return code to fspm_update_config() that indicates
whether MRC data was found and a new property to the device tree.
Also add one more debug message while starting.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Some settings were modified slightly in the device-tree conversion. Return
these to their original values. This includes some audio settings and a
few others that have changed.
Note that we still rely on the FSP defaults for most values, so there is
no need to specify a value if the FSP default is suitable.
This makes WiFi work again.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Some settings were modified slightly in the device-tree conversion. Return
these to their original values.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
A the moment the FSP-S configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-S full configurable from devicetree by
adding binding properties for all FSP-S parameters.
Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
A the moment the FSP-M configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-M full configurable from devicetree by adding
binding properties for all FSP-M parameters.
Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral)
[sjg: Fix a build error for coral]
Signed-off-by: Simon Glass <sjg@chromium.org>
[bmeng: Add __maybe_unused to fsp_update_config_from_dtb()]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This device should use ready-gpios rather than ready-gpio. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Drop the Apollo Lake prefix 'apl' from the functions, types and
variables in the P2SB driver.
The P2SB is not Apollo Lake specific, and as such it was moved in
commit 2999846c11 ("x86: Move P2SB from Apollo Lake to a more generic
location") from the Apollo Lake folder to the intel_common folder.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add nodes to the device tree for Cr50 and other available I2C ports. Also
enable the ACPI interrupt driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Enable the Intel clock driver and modify coral's device tree to use it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The Interrupt Timer Subsystem (ITSS) is not specific to Apollo Lake, so
remove the apl-prefix of the implemented functions/structures/...
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for coral which is a range of Apollo Lake-based Chromebook
released in 2017. This also includes reef released in 2016, since it is
based on the same SoC.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
