x86: apl: Use devicetree for FSP-S configuration

A the moment the FSP-S configuration is a mix of hard coded values and
devicetree properties.

This patch makes FSP-S full configurable from devicetree by
adding binding properties for all FSP-S parameters.

Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Bernhard Messerklinger 2020-05-18 12:33:35 +02:00 committed by Bin Meng
parent 1fa6305fd6
commit d9e7efe10a
6 changed files with 1922 additions and 387 deletions

File diff suppressed because it is too large Load Diff

View File

@ -24,313 +24,16 @@
#include <asm/arch/fsp/fsp_configs.h>
#include <asm/arch/fsp/fsp_s_upd.h>
#include <linux/bitops.h>
#include <asm/arch/fsp_bindings.h>
#define PCH_P2SB_E0 0xe0
#define HIDE_BIT BIT(0)
#define INTEL_GSPI_MAX 3
#define MAX_USB2_PORTS 8
enum {
CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
};
/* Serial IRQ control. SERIRQ_QUIET is the default (0) */
enum serirq_mode {
SERIRQ_QUIET,
SERIRQ_CONTINUOUS,
SERIRQ_OFF,
};
struct gspi_cfg {
/* Bus speed in MHz */
u32 speed_mhz;
/* Bus should be enabled prior to ramstage with temporary base */
u8 early_init;
};
/*
* This structure will hold data required by common blocks.
* These are soc specific configurations which will be filled by soc.
* We'll fill this structure once during init and use the data in common block.
*/
struct soc_intel_common_config {
int chipset_lockdown;
struct gspi_cfg gspi[INTEL_GSPI_MAX];
};
enum pnp_settings {
PNP_PERF,
PNP_POWER,
PNP_PERF_POWER,
};
struct usb2_eye_per_port {
u8 per_port_tx_pe_half;
u8 per_port_pe_txi_set;
u8 per_port_txi_set;
u8 hs_skew_sel;
u8 usb_tx_emphasis_en;
u8 per_port_rxi_set;
u8 hs_npre_drv_sel;
u8 override_en;
};
struct apl_config {
/* Common structure containing soc config data required by common code*/
struct soc_intel_common_config common_soc_config;
/*
* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
* four CLKREQ inputs, but six root ports. Root ports without an
* associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
*/
u8 pcie_rp_clkreq_pin[MAX_PCIE_PORTS];
/* Enable/disable hot-plug for root ports (0 = disable, 1 = enable) */
u8 pcie_rp_hotplug_enable[MAX_PCIE_PORTS];
/* De-emphasis enable configuration for each PCIe root port */
u8 pcie_rp_deemphasis_enable[MAX_PCIE_PORTS];
/*
* [14:8] DDR mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR mode Number of dealy elements.Each = 125pSec.
*/
u32 emmc_tx_cmd_cntl;
/*
* [14:8] HS400 mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec.
*/
u32 emmc_tx_data_cntl1;
/*
* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR12/Compatibility mode Number of dealy elements.
* Each = 125pSec.
*/
u32 emmc_tx_data_cntl2;
/*
* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR12/Compatibility mode Number of dealy elements.
* Each = 125pSec.
*/
u32 emmc_rx_cmd_data_cntl1;
/*
* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec.
* [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec.
*/
u32 emmc_rx_strobe_cntl;
/*
* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec.
*/
u32 emmc_rx_cmd_data_cntl2;
/* Select the eMMC max speed allowed */
u32 emmc_host_max_speed;
/* Specifies on which IRQ the SCI will internally appear */
u32 sci_irq;
/* Configure serial IRQ (SERIRQ) line */
enum serirq_mode serirq_mode;
/* Configure LPSS S0ix Enable */
bool lpss_s0ix_enable;
/* Enable DPTF support */
bool dptf_enable;
/* TCC activation offset value in degrees Celsius */
int tcc_offset;
/*
* Configure Audio clk gate and power gate
* IOSF-SB port ID 92 offset 0x530 [5] and [3]
*/
bool hdaudio_clk_gate_enable;
bool hdaudio_pwr_gate_enable;
bool hdaudio_bios_config_lockdown;
/* SLP S3 minimum assertion width */
int slp_s3_assertion_width_usecs;
/* GPIO pin for PERST_0 */
u32 prt0_gpio;
/* USB2 eye diagram settings per port */
struct usb2_eye_per_port usb2eye[MAX_USB2_PORTS];
/* GPIO SD card detect pin */
unsigned int sdcard_cd_gpio;
/*
* PRMRR size setting with three options
* 0x02000000 - 32MiB
* 0x04000000 - 64MiB
* 0x08000000 - 128MiB
*/
u32 PrmrrSize;
/*
* Enable SGX feature.
* Enabling SGX feature is 2 step process,
* (1) set sgx_enable = 1
* (2) set PrmrrSize to supported size
*/
bool sgx_enable;
/*
* Select PNP Settings.
* (0) Performance,
* (1) Power
* (2) Power & Performance
*/
enum pnp_settings pnp_settings;
/*
* PMIC PCH_PWROK delay configuration - IPC Configuration
* Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address
* (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0)
*/
u32 pmic_pmc_ipc_ctrl;
/*
* Options to disable XHCI Link Compliance Mode. Default is FALSE to not
* disable Compliance Mode. Set TRUE to disable Compliance Mode.
* 0:FALSE(Default), 1:True.
*/
bool disable_compliance_mode;
/*
* Options to change USB3 ModPhy setting for the Integrated Filter (IF)
* value. Default is 0 to not changing default IF value (0x12). Set
* value with the range from 0x01 to 0xff to change IF value.
*/
u32 mod_phy_if_value;
/*
* Options to bump USB3 LDO voltage. Default is FALSE to not increasing
* LDO voltage. Set TRUE to increase LDO voltage with 40mV.
* 0:FALSE (default), 1:True.
*/
bool mod_phy_voltage_bump;
/*
* Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting
* the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage
* configuration: I2C_Slave_Address (31:23) + Register_Offset (23:16)
* + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]:
* 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default).
*/
u32 pmic_vdd2_voltage;
/* Option to enable VTD feature */
bool enable_vtd;
};
static int get_config(struct udevice *dev, struct apl_config *apl)
{
const u8 *ptr;
ofnode node;
u32 emmc[4];
int ret;
memset(apl, '\0', sizeof(*apl));
node = dev_read_subnode(dev, "fsp-s");
if (!ofnode_valid(node))
return log_msg_ret("fsp-s settings", -ENOENT);
ptr = ofnode_read_u8_array_ptr(node, "pcie-rp-clkreq-pin",
MAX_PCIE_PORTS);
if (!ptr)
return log_msg_ret("pcie-rp-clkreq-pin", -EINVAL);
memcpy(apl->pcie_rp_clkreq_pin, ptr, MAX_PCIE_PORTS);
ret = ofnode_read_u32(node, "prt0-gpio", &apl->prt0_gpio);
if (ret)
return log_msg_ret("prt0-gpio", ret);
ret = ofnode_read_u32(node, "sdcard-cd-gpio", &apl->sdcard_cd_gpio);
if (ret)
return log_msg_ret("sdcard-cd-gpio", ret);
ret = ofnode_read_u32_array(node, "emmc", emmc, ARRAY_SIZE(emmc));
if (ret)
return log_msg_ret("emmc", ret);
apl->emmc_tx_data_cntl1 = emmc[0];
apl->emmc_tx_data_cntl2 = emmc[1];
apl->emmc_rx_cmd_data_cntl1 = emmc[2];
apl->emmc_rx_cmd_data_cntl2 = emmc[3];
apl->dptf_enable = ofnode_read_bool(node, "dptf-enable");
apl->hdaudio_clk_gate_enable = ofnode_read_bool(node,
"hdaudio-clk-gate-enable");
apl->hdaudio_pwr_gate_enable = ofnode_read_bool(node,
"hdaudio-pwr-gate-enable");
apl->hdaudio_bios_config_lockdown = ofnode_read_bool(node,
"hdaudio-bios-config-lockdown");
apl->lpss_s0ix_enable = ofnode_read_bool(node, "lpss-s0ix-enable");
/* Santa */
apl->usb2eye[1].per_port_pe_txi_set = 7;
apl->usb2eye[1].per_port_txi_set = 2;
return 0;
}
static void apl_fsp_silicon_init_params_cb(struct apl_config *apl,
struct fsp_s_config *cfg)
{
u8 port;
for (port = 0; port < MAX_USB2_PORTS; port++) {
if (apl->usb2eye[port].per_port_tx_pe_half)
cfg->port_usb20_per_port_tx_pe_half[port] =
apl->usb2eye[port].per_port_tx_pe_half;
if (apl->usb2eye[port].per_port_pe_txi_set)
cfg->port_usb20_per_port_pe_txi_set[port] =
apl->usb2eye[port].per_port_pe_txi_set;
if (apl->usb2eye[port].per_port_txi_set)
cfg->port_usb20_per_port_txi_set[port] =
apl->usb2eye[port].per_port_txi_set;
if (apl->usb2eye[port].hs_skew_sel)
cfg->port_usb20_hs_skew_sel[port] =
apl->usb2eye[port].hs_skew_sel;
if (apl->usb2eye[port].usb_tx_emphasis_en)
cfg->port_usb20_i_usb_tx_emphasis_en[port] =
apl->usb2eye[port].usb_tx_emphasis_en;
if (apl->usb2eye[port].per_port_rxi_set)
cfg->port_usb20_per_port_rxi_set[port] =
apl->usb2eye[port].per_port_rxi_set;
if (apl->usb2eye[port].hs_npre_drv_sel)
cfg->port_usb20_hs_npre_drv_sel[port] =
apl->usb2eye[port].hs_npre_drv_sel;
}
}
int fsps_update_config(struct udevice *dev, ulong rom_offset,
struct fsps_upd *upd)
{
struct fsp_s_config *cfg = &upd->config;
struct apl_config *apl;
ofnode node;
if (IS_ENABLED(CONFIG_HAVE_VBT)) {
struct binman_entry vbt;
@ -358,88 +61,11 @@ int fsps_update_config(struct udevice *dev, ulong rom_offset,
cfg->graphics_config_ptr = (ulong)vbt_buf;
}
apl = malloc(sizeof(*apl));
if (!apl)
return log_msg_ret("config", -ENOMEM);
get_config(dev, apl);
node = dev_read_subnode(dev, "fsp-s");
if (!ofnode_valid(node))
return log_msg_ret("fsp-s settings", -ENOENT);
cfg->ish_enable = 0;
cfg->enable_sata = 0;
cfg->pcie_root_port_en[2] = 0;
cfg->pcie_rp_hot_plug[2] = 0;
cfg->pcie_root_port_en[3] = 0;
cfg->pcie_rp_hot_plug[3] = 0;
cfg->pcie_root_port_en[4] = 0;
cfg->pcie_rp_hot_plug[4] = 0;
cfg->pcie_root_port_en[5] = 0;
cfg->pcie_rp_hot_plug[5] = 0;
cfg->pcie_root_port_en[1] = 0;
cfg->pcie_rp_hot_plug[1] = 0;
cfg->usb_otg = 0;
cfg->i2c6_enable = 0;
cfg->i2c7_enable = 0;
cfg->hsuart3_enable = 0;
cfg->spi1_enable = 0;
cfg->spi2_enable = 0;
cfg->sdio_enabled = 0;
memcpy(cfg->pcie_rp_clk_req_number, apl->pcie_rp_clkreq_pin,
sizeof(cfg->pcie_rp_clk_req_number));
memcpy(cfg->pcie_rp_hot_plug, apl->pcie_rp_hotplug_enable,
sizeof(cfg->pcie_rp_hot_plug));
switch (apl->serirq_mode) {
case SERIRQ_QUIET:
cfg->sirq_enable = 1;
cfg->sirq_mode = 0;
break;
case SERIRQ_CONTINUOUS:
cfg->sirq_enable = 1;
cfg->sirq_mode = 1;
break;
case SERIRQ_OFF:
default:
cfg->sirq_enable = 0;
break;
}
if (apl->emmc_tx_cmd_cntl)
cfg->emmc_tx_cmd_cntl = apl->emmc_tx_cmd_cntl;
if (apl->emmc_tx_data_cntl1)
cfg->emmc_tx_data_cntl1 = apl->emmc_tx_data_cntl1;
if (apl->emmc_tx_data_cntl2)
cfg->emmc_tx_data_cntl2 = apl->emmc_tx_data_cntl2;
if (apl->emmc_rx_cmd_data_cntl1)
cfg->emmc_rx_cmd_data_cntl1 = apl->emmc_rx_cmd_data_cntl1;
if (apl->emmc_rx_strobe_cntl)
cfg->emmc_rx_strobe_cntl = apl->emmc_rx_strobe_cntl;
if (apl->emmc_rx_cmd_data_cntl2)
cfg->emmc_rx_cmd_data_cntl2 = apl->emmc_rx_cmd_data_cntl2;
if (apl->emmc_host_max_speed)
cfg->e_mmc_host_max_speed = apl->emmc_host_max_speed;
cfg->lpss_s0ix_enable = apl->lpss_s0ix_enable;
cfg->skip_mp_init = true;
/* Disable setting of EISS bit in FSP */
cfg->spi_eiss = 0;
/* Disable FSP from locking access to the RTC NVRAM */
cfg->rtc_lock = 0;
/* Enable Audio clk gate and power gate */
cfg->hd_audio_clk_gate = apl->hdaudio_clk_gate_enable;
cfg->hd_audio_pwr_gate = apl->hdaudio_pwr_gate_enable;
/* Bios config lockdown Audio clk and power gate */
cfg->bios_cfg_lock_down = apl->hdaudio_bios_config_lockdown;
apl_fsp_silicon_init_params_cb(apl, cfg);
cfg->usb_otg = true;
cfg->vtd_enable = apl->enable_vtd;
return 0;
return fsp_s_update_config_from_dtb(node, cfg);
}
static void p2sb_set_hide_bit(pci_dev_t dev, int hide)

View File

@ -22,6 +22,7 @@
#include <asm/arch-apollolake/pm.h>
#include <dt-bindings/clock/intel-clock.h>
#include <asm/arch-apollolake/fsp/fsp_m_upd.h>
#include <asm/arch-apollolake/fsp/fsp_s_upd.h>
/ {
model = "Google Coral";
@ -520,8 +521,19 @@
&fsp_s {
u-boot,dm-pre-proper;
fsps,ish-enable = <0>;
fsps,enable-sata = <0>;
fsps,pcie-root-port-en = [00 00 00 00 00 01];
fsps,pcie-rp-hot-plug = [00 00 00 00 00 01];
fsps,i2c6-enable = <I2CX_ENABLE_DISABLED>;
fsps,i2c7-enable = <I2CX_ENABLE_DISABLED>;
fsps,hsuart3-enable = <HSUARTX_ENABLE_DISABLED>;
fsps,spi1-enable = <SPIX_ENABLE_DISABLED>;
fsps,spi2-enable = <SPIX_ENABLE_DISABLED>;
fsps,sdio-enabled = <0>;
/* Disable unused clkreq of PCIe root ports */
pcie-rp-clkreq-pin = /bits/ 8 <0 /* wifi/bt */
fsps,pcie-rp-clk-req-number = /bits/ 8 <0 /* wifi/bt */
CLKREQ_DISABLED
CLKREQ_DISABLED
CLKREQ_DISABLED
@ -575,18 +587,27 @@
* [14:8] steps of delay for Auto Tuning Mode, each 125ps
* [6:0] steps of delay for HS200, each 125ps
*/
emmc = <0x0c16 0x28162828 0x00181717 0x10008>;
/* Enable DPTF */
dptf-enable;
fsps,emmc-tx-data-cntl1 = <0x0c16>;
fsps,emmc-tx-data-cntl2 = <0x28162828>;
fsps,emmc-rx-cmd-data-cntl1 = <0x00181717>;
fsps,emmc-rx-cmd-data-cntl2 = <0x10008>;
/* Enable Audio Clock and Power gating */
hdaudio-clk-gate-enable;
hdaudio-pwr-gate-enable;
hdaudio-bios-config-lockdown;
fsps,hd-audio-clk-gate = <1>;
fsps,hd-audio-pwr-gate = <1>;
fsps,bios-cfg-lock-down = <1>;
/* Enable lpss s0ix */
lpss-s0ix-enable;
fsps,lpss-s0ix-enable = <1>;
fsps,skip-mp-init = <1>;
fsps,spi-eiss = <0>;
fsps,rtc-lock = <0>;
fsps,port-usb20-per-port-pe-txi-set = [07 07 06 06 07 07 07 01];
fsps,port-usb20-per-port-txi-set = [00 02 00 00 00 00 00 03];
/*
* TODO(sjg@chromium.org): Move this to the I2C nodes

View File

@ -6,6 +6,7 @@
#ifndef __ASM_ARCH_FSP_S_UDP_H
#define __ASM_ARCH_FSP_S_UDP_H
#ifndef __ASSEMBLY__
#include <asm/fsp2/fsp_api.h>
struct __packed fsp_s_config {
@ -288,5 +289,206 @@ struct __packed fsps_upd {
u8 unused_upd_space2[46];
u16 upd_terminator;
};
#endif
#define PROC_TRACE_MEM_SIZE_DISABLE 0xff
#define BOOT_P_STATE_HFM 0
#define BOOT_P_STATE_LFM 1
#define PKG_C_STATE_LIMIT_C0_C1 0
#define PKG_C_STATE_LIMIT_C2 1
#define PKG_C_STATE_LIMIT_C3 2
#define PKG_C_STATE_LIMIT_C6 3
#define PKG_C_STATE_LIMIT_C7 4
#define PKG_C_STATE_LIMIT_C7S 5
#define PKG_C_STATE_LIMIT_C8 6
#define PKG_C_STATE_LIMIT_C9 7
#define PKG_C_STATE_LIMIT_C10 8
#define PKG_C_STATE_LIMIT_CMAX 9
#define PKG_C_STATE_LIMIT_CPU_DEFAULT 254
#define PKG_C_STATE_LIMIT_AUTO 255
#define C_STATE_AUTO_DEMOTION_DISABLE_C1_C3 0
#define C_STATE_AUTO_DEMOTION_ENABLE_C3_C6_C7_TO_C1 1
#define C_STATE_AUTO_DEMOTION_ENABLE_C6_C7_TO_C3 2
#define C_STATE_AUTO_DEMOTION_ENABLE_C6_C7_TO_C1_C3 3
#define C_STATE_UN_DEMOTION_DISABLE_C1_C3 0
#define C_STATE_UN_DEMOTION_ENABLE_C1 1
#define C_STATE_UN_DEMOTION_ENABLE_C3 2
#define C_STATE_UN_DEMOTION_ENABLE_C1_C3 3
#define MAX_CORE_C_STATE_UNLIMITED 0
#define MAX_CORE_C_STATE_C1 1
#define MAX_CORE_C_STATE_C3 2
#define MAX_CORE_C_STATE_C6 3
#define MAX_CORE_C_STATE_C7 4
#define MAX_CORE_C_STATE_C8 5
#define MAX_CORE_C_STATE_C9 6
#define MAX_CORE_C_STATE_C10 7
#define MAX_CORE_C_STATE_CCX 8
#define IPU_ACPI_MODE_DISABLE 0
#define IPU_ACPI_MODE_IGFX_CHILD_DEVICE 1
#define IPU_ACPI_MODE_ACPI_DEVICE 1
#define CD_CLOCK_FREQ_144MHZ 0
#define CD_CLOCK_FREQ_288MHZ 1
#define CD_CLOCK_FREQ_384MHZ 2
#define CD_CLOCK_FREQ_576MHZ 3
#define CD_CLOCK_FREQ_624MHZ 4
#define HDA_IO_BUFFER_OWNERSHIP_HDA_ALL_IO 0
#define HDA_IO_BUFFER_OWNERSHIP_HDA_I2S_SPLIT 1
#define HDA_IO_BUFFER_OWNERSHIP_I2S_ALL_IO 2
#define HDA_IO_BUFFER_VOLTAGE_3V3 0
#define HDA_IO_BUFFER_VOLTAGE_1V8 1
#define HDA_VC_TYPE_VC0 0
#define HDA_VC_TYPE_VC1 1
#define HDA_LINK_FREQ_6MHZ 0
#define HDA_LINK_FREQ_12MHZ 1
#define HDA_LINK_FREQ_24MHZ 2
#define HDA_LINK_FREQ_48MHZ 3
#define HDA_LINK_FREQ_96MHZ 4
#define HDA_LINK_FREQ_INVALID 5
#define HDA_I_DISP_LINK_FREQ_6MHZ 0
#define HDA_I_DISP_LINK_FREQ_12MHZ 1
#define HDA_I_DISP_LINK_FREQ_24MHZ 2
#define HDA_I_DISP_LINK_FREQ_48MHZ 3
#define HDA_I_DISP_LINK_FREQ_96MHZ 4
#define HDA_I_DISP_LINK_FREQ_INVALID 5
#define HDA_I_DISP_LINK_T_MODE_2T 0
#define HDA_I_DISP_LINK_T_MODE_1T 1
#define HDA_DISP_DMIC_DISABLE 0
#define HDA_DISP_DMIC_2CH_ARRAY 1
#define HDA_DISP_DMIC_4CH_ARRAY 2
#define HDA_CSE_MEM_TRANSFERS_VC0 0
#define HDA_CSE_MEM_TRANSFERS_VC2 1
#define HDA_HOST_MEM_TRANSFERS_VC0 0
#define HDA_HOST_MEM_TRANSFERS_VC2 1
#define HDA_DSP_FEATURE_MASK_WOV 0x1
#define HDA_DSP_FEATURE_MASK_BT_SIDEBAND 0x2
#define HDA_DSP_FEATURE_MASK_CODEC_VAD 0x4
#define HDA_DSP_FEATURE_MASK_BT_INTEL_HFP 0x20
#define HDA_DSP_FEATURE_MASK_BT_INTEL_A2DP 0x40
#define HDA_DSP_FEATURE_MASK_DSP_BASED_PRE_PROC_DISABLE 0x80
#define HDA_DSP_PP_MODULE_MASK_WOV 0x1
#define HDA_DSP_PP_MODULE_MASK_BT_SIDEBAND 0x2
#define HDA_DSP_PP_MODULE_MASK_CODEC_VAD 0x4
#define HDA_DSP_PP_MODULE_MASK_BT_INTEL_HFP 0x20
#define HDA_DSP_PP_MODULE_MASK_BT_INTEL_A2DP 0x40
#define HDA_DSP_PP_MODULE_MASK_DSP_BASED_PRE_PROC_DISABLE 0x80
#define I2CX_ENABLE_DISABLED 0
#define I2CX_ENABLE_PCI_MODE 1
#define I2CX_ENABLE_ACPI_MODE 2
#define HSUARTX_ENABLE_DISABLED 0
#define HSUARTX_ENABLE_PCI_MODE 1
#define HSUARTX_ENABLE_ACPI_MODE 2
#define SPIX_ENABLE_DISABLED 0
#define SPIX_ENABLE_PCI_MODE 1
#define SPIX_ENABLE_ACPI_MODE 2
#define PCIE_RP_SPEED_AUTO 0
#define PCIE_RP_SPEED_GEN1 1
#define PCIE_RP_SPEED_GEN2 2
#define PCIE_RP_SPEED_GEN3 3
#define PCIE_RP_ASPM_DISABLE 0
#define PCIE_RP_ASPM_L0S 1
#define PCIE_RP_ASPM_L1 2
#define PCIE_RP_ASPM_L0S_L1 3
#define PCIE_RP_ASPM_AUTO 4
#define PCIE_RP_L1_SUBSTATES_DISABLE 0
#define PCIE_RP_L1_SUBSTATES_L1_1 1
#define PCIE_RP_L1_SUBSTATES_L1_2 2
#define PCIE_RP_L1_SUBSTATES_L1_1_L1_2 3
#define SATA_MODE_AHCI 0
#define SATA_MODE_RAID 1
#define SATA_SPEED_LIMIT_SC_SATA_SPEED 0
#define SATA_SPEED_LIMIT_1_5GBS 1
#define SATA_SPEED_LIMIT_3GBS 2
#define SATA_SPEED_LIMIT_6GBS 3
#define SATA_PORT_SOLID_STATE_DRIVE_HARD_DISK_DRIVE 0
#define SATA_PORT_SOLID_STATE_DRIVE_SOLID_STATE_DRIVE 1
#define CRID_SETTING_DISABLE 0
#define CRID_SETTING_CRID_1 1
#define CRID_SETTING_CRID_2 2
#define CRID_SETTING_CRID_3 3
#define RESET_SELECT_WARM_RESET 0x6
#define RESET_SELECT_COLD_RESET 0xe
#define EMMC_HOST_SPEED_MAX_HS400 0
#define EMMC_HOST_SPEED_MAX_HS200 1
#define EMMC_HOST_SPEED_MAX_DDR50 2
#define SERIAL_IRQ_MODE_QUIET_MODE 0
#define SERIAL_IRQ_MODE_CONTINUOUS_MODE 1
#define START_FRAME_PULSE_WIDTH_SCSFPW4CLK 0
#define START_FRAME_PULSE_WIDTH_SCSFPW6CLK 1
#define START_FRAME_PULSE_WIDTH_SCSFPW8CLK 1
#define USB30_MODE_DISABLE 0
#define USB30_MODE_ENABLE 1
#define USB30_MODE_AUTO 2
#define USB_OTG_DISABLE 0
#define USB_OTG_PCI_MODE 1
#define USB_OTG_ACPI_MODE 2
#define SSIC_RATE_A_SERIES 1
#define SSIC_RATE_B_SERIES 2
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MODE_DISABLE 0
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MODE_ENABLE 1
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MODE_AUTO 2
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1NS 0
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32NS 1
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1024NS 2
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32768NS 3
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1048576NS 4
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_33554432NS 5
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MODE_DISABLE 0
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MODE_ENABLE 1
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MODE_AUTO 2
#define PWR_BTN_OVERRIDE_PERIOD_4S 0
#define PWR_BTN_OVERRIDE_PERIOD_6S 1
#define PWR_BTN_OVERRIDE_PERIOD_8S 2
#define PWR_BTN_OVERRIDE_PERIOD_10S 3
#define PWR_BTN_OVERRIDE_PERIOD_12S 4
#define PWR_BTN_OVERRIDE_PERIOD_14S 5
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1NS 0
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32NS 1
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1024NS 2
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32768NS 3
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1048576NS 4
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_33554432NS 5
#define PCIE_RP_SELECTABLE_DEEMPHASIS_6_DB 0
#define PCIE_RP_SELECTABLE_DEEMPHASIS_3_5_DB 1
#endif

View File

@ -8,6 +8,7 @@
#define __ASM_ARCH_FSP_BINDINGS_H
#include <asm/arch/fsp/fsp_m_upd.h>
#include <asm/arch/fsp/fsp_s_upd.h>
#define ARRAY_SIZE_OF_MEMBER(s, m) (ARRAY_SIZE((((s *)0)->m)))
#define SIZE_OF_MEMBER(s, m) (sizeof((((s *)0)->m)))
@ -93,4 +94,17 @@ struct lpddr4_swizzle_cfg {
*/
int fsp_m_update_config_from_dtb(ofnode node, struct fsp_m_config *cfg);
/**
* fsp_s_update_config_from_dtb() - Read FSP-S config from devicetree node
* @node: Valid node reference to read property from
* @cfg: Pointer to FSP-S config structure
* @return 0 on success, -ve on error
*
* This function reads the configuration for FSP-S from the provided
* devicetree node and saves it in the FSP-S configuration structure.
* Configuration options that are not present in the devicetree are
* left at their current value.
*/
int fsp_s_update_config_from_dtb(ofnode node, struct fsp_s_config *cfg);
#endif

View File

@ -0,0 +1,483 @@
* Intel FSP-S configuration
Several Intel platforms require the execution of the Intel FSP (Firmware
Support Package) for initialization. The FSP consists of multiple parts, one
of which is the FSP-S (Silicon initialization phase).
This binding applies to the FSP-S for the Intel Apollo Lake SoC.
The FSP-S is available on Github [1].
For detailed information on the FSP-S parameters see the documentation in
FSP/ApolloLakeFspBinPkg/Docs [2].
The properties of this binding are all optional. If no properties are set the
values of the FSP-S are used.
[1] https://github.com/IntelFsp/FSP
[2] https://github.com/IntelFsp/FSP/tree/master/ApolloLakeFspBinPkg/Docs
Optional properties:
- fsps,active-processor-cores: ActiveProcessorCores
- fsps,disable-core1: Disable Core1
- fsps,disable-core2: Disable Core2
- fsps,disable-core2: Disable Core3
- fsps,vmx-enable: VMX Enable
- fsps,proc-trace-mem-size: Memory region allocation for Processor Trace
0xFF: Disable (default)
- fsps,proc-trace-enable: Enable Processor Trace
- fsps,eist: Eist
- fsps,boot-p-state: Boot PState
0: HFM (default)
1: LFM
- fsps,enable-cx: CPU power states (C-states)
- fsps,c1e: Enhanced C-states
- fsps,bi-proc-hot: Bi-Directional PROCHOT#
- fsps,pkg-c-state-limit: Max Pkg Cstate
0: PkgC0C1
1: PkgC2
2: PkgC3 (default)
3: PkgC6
4: PkgC7
5: PkgC7s
6: PkgC8
7: PkgC9
8: PkgC10
9: PkgCMax
254: PkgCpuDefault
255: PkgAuto
- fsps,c-state-auto-demotion: C-State auto-demotion
0: Disable C1 and C3 Auto-demotion (default)
1: Enable C3/C6/C7 Auto-demotion to C1
2: Enable C6/C7 Auto-demotion to C3
3: Enable C6/C7 Auto-demotion to C1 and C3
- fsps,c-state-un-demotion: C-State un-demotion
0: Disable C1 and C3 Un-demotion (default)
1: Enable C1 Un-demotion
2: Enable C3 Un-demotion
3: Enable C1 and C3 Un-demotion
- fsps,max-core-c-state: Max Core C-State
0: Unlimited
1: C1
2: C3
3: C6
4: C7
5: C8
6: C9
7: C10
8: CCx (default)
- fsps,pkg-c-state-demotion: Package C-State Demotion
- fsps,pkg-c-state-un-demotion: Package C-State Un-demotion
- fsps,turbo-mode: Turbo Mode
- fsps,hda-verb-table-entry-num: SC HDA Verb Table Entry Number
0: (default)
- fsps,hda-verb-table-ptr: SC HDA Verb Table Pointer
0x00000000: (default)
- fsps,p2sb-unhide: Enable/Disable P2SB device hidden
- fsps,ipu-en: IPU Enable/Disable
- fsps,ipu-acpi-mode: IMGU ACPI mode selection
0: Auto
1: IGFX Child device (default)
2: ACPI device
- fsps,force-wake: Enable ForceWake
- fsps,gtt-mm-adr: GttMmAdr
0xbf000000: (default)
- fsps,gm-adr: GmAdr
0xa0000000: (default)
- fsps,pavp-lock: Enable PavpLock
- fsps,graphics-freq-modify: Enable GraphicsFreqModify
- fsps,graphics-freq-req: Enable GraphicsFreqReq
- fsps,graphics-video-freq: Enable GraphicsVideoFreq
- fsps,pm-lock: Enable PmLock
- fsps,dop-clock-gating: Enable DopClockGating
- fsps,unsolicited-attack-override: Enable UnsolicitedAttackOverride
- fsps,wopcm-support: Enable WOPCMSupport
- fsps,wopcm-size: Enable WOPCMSize
- fsps,power-gating: Enable PowerGating
- fsps,unit-level-clock-gating: Enable UnitLevelClockGating
- fsps,fast-boot: Enable FastBoot
- fsps,dyn-sr: Enable DynSR
- fsps,sa-ipu-enable: Enable SaIpuEnable
- fsps,pm-support: GT PM Support
- fsps,enable-render-standby: RC6(Render Standby)
- fsps,logo-size: BMP Logo Data Size
- fsps,logo-ptr: BMP Logo Data Pointer
- fsps,graphics-config-ptr: Graphics Configuration Data Pointer
- fsps,pavp-enable: PAVP Enable
- fsps,pavp-pr3: PAVP PR3
- fsps,cd-clock: CdClock Frequency selection
0: 144MHz
1: 288MHz
2: 384MHz
3: 576MHz
4: 624MHz (default)
- fsps,pei-graphics-peim-init: Enable/Disable PeiGraphicsPeimInit
- fsps,write-protection-enable: Write Protection Support
- fsps,read-protection-enable: Read Protection Support
- fsps,protected-range-limit: Protected Range Limitation
0x0FFF: (default)
- fsps,protected-range-base: Protected Range Base
0x0000: (default)
- fsps,gmm: Enable SC Gaussian Mixture Models
- fsps,clk-gating-pgcb-clk-trunk: GMM Clock Gating - PGCB Clock Trunk
- fsps,clk-gating-sb: GMM Clock Gating - Sideband
- fsps,clk-gating-sb-clk-trunk: GMM Clock Gating - Sideband
- fsps,clk-gating-sb-clk-partition: GMM Clock Gating - Sideband Clock
Partition
- fsps,clk-gating-core: GMM Clock Gating - Core
- fsps,clk-gating-dma: GMM Clock Gating - DMA
- fsps,clk-gating-reg-access: GMM Clock Gating - Register Access
- fsps,clk-gating-host: GMM Clock Gating - Host
- fsps,clk-gating-partition: GMM Clock Gating - Partition
- fsps,clk-gating-trunk: Clock Gating - Trunk
- fsps,hda-enable: HD Audio Support
- fsps,dsp-enable: HD Audio DSP Support
- fsps,pme: Azalia wake-on-ring
- fsps,hd-audio-io-buffer-ownership: HD-Audio I/O Buffer Ownership
0: HD-Audio link owns all the I/O buffers (default)
1: HD-Audio link owns 4 I/O buffers and I2S port owns 4 I/O buffers
3: I2S port owns all the I/O buffers
- fsps,hd-audio-io-buffer-voltage: HD-Audio I/O Buffer Voltage
0: 3.3V (default)
1: 1.8V
- fsps,hd-audio-vc-type: HD-Audio Virtual Channel Type
0: VC0 (default)
1: VC1
- fsps,hd-audio-link-frequency: HD-Audio Link Frequency
0: 6MHz (default)
1: 12MHz
2: 24MHz
3: 48MHz
4: 96MHz
5: Invalid
- fsps,hd-audio-i-disp-link-frequency: HD-Audio iDisp-Link Frequency
0: 6MHz (default)
1: 12MHz
2: 24MHz
3: 48MHz
4: 96MHz
5: Invalid
- fsps,hd-audio-i-disp-link-tmode: HD-Audio iDisp-Link T-Mode
0: 2T (default)
1: 1T
- fsps,dsp-endpoint-dmic: HD-Audio Disp DMIC
0: disable,
1: 2ch array (default)
2: 4ch array
- fsps,dsp-endpoint-bluetooth: HD-Audio Bluetooth
- fsps,dsp-endpoint-i2s-skp: HD-Audio I2S SHK
- fsps,dsp-endpoint-i2s-hp: HD-Audio I2S HP
- fsps,audio-ctl-pwr-gate: HD-Audio Controller Power Gating (deprecated)
- fsps,audio-dsp-pwr-gate: HD-Audio ADSP Power Gating (deprecated)
- fsps,mmt: HD-Audio CSME Memory Transfers
0: VC0 (default)
1: VC2
- fsps,hmt: HD-Audio Host Memory Transfers
0: VC0 (default)
1: VC2
- fsps,hd-audio-pwr-gate: HD-Audio Power Gating
- fsps,hd-audio-clk-gate: HD-Audio Clock Gating
- fsps,dsp-feature-mask: Bitmask of DSP Feature
0x01: WoV
0x02: BT Sideband
0x04: Codec VAD
0x20: BT Intel HFP
0x40: BT Intel A2DP
0x80: DSP based speech pre-processing disabled
- fsps,dsp-pp-module-mask: Bitmask of supported DSP Post-Processing Modules
0x01: WoV
0x02: BT Sideband
0x04: Codec VAD
0x20: BT Intel HFP
0x40: BT Intel A2DP
0x80: DSP based speech pre-processing disabled
- fsps,bios-cfg-lock-down: HD-Audio BIOS Configuration Lock Down
- fsps,hpet: Enable High Precision Timer
- fsps,hpet-bdf-valid: Hpet Valid BDF Value
- fsps,hpet-bus-number: Bus Number of Hpet
0xFA: (default)
- fsps,hpet-device-number: Device Number of Hpet
0x1F: (default)
- fsps,hpet-function-number: Function Number of Hpet
0x00: (default)
- fsps,io-apic-bdf-valid: IoApic Valid BDF Value
- fsps,io-apic-bus-number: Bus Number of IoApic
0xFA: (default)
- fsps,io-apic-device-number: Device Number of IoApic
0x0F: (default)
- fsps,io-apic-function-number: Function Number of IoApic
0x00: (default)
- fsps,io-apic-entry24-119: IOAPIC Entry 24-119
- fsps,io-apic-id: IO APIC ID
0x01: (default)
- fsps,io-apic-range-select: IoApic Range
0x00: (default)
- fsps,ish-enable: ISH Controller
- fsps,bios-interface: BIOS Interface Lock Down
- fsps,bios-lock: Bios LockDown Enable
- fsps,spi-eiss: SPI EISS Status
- fsps,bios-lock-sw-smi-number: BiosLock SWSMI Number
0xA9: (default)
- fsps,lpss-s0ix-enable: LPSS IOSF PMCTL S0ix Enable
- fsps,i2c-clk-gate-cfg: LPSS I2C Clock Gating Configuration
- fsps,hsuart-clk-gate-cfg: LPSS HSUART Clock Gating Configuration
- fsps,spi-clk-gate-cfg: LPSS SPI Clock Gating Configuration
- fsps,i2cX-enable: 2C Device X
0: Disabled
1: PCI Mode (default)
2: ACPI Mode
- fsps,hsuartX-enable: UART Device X
0: Disabled
1: PCI Mode (default)
2: ACPI Mode
- fsps,spiX-enable: SPI UART Device X
0: Disabled
1: PCI Mode (default)
2: ACPI Mode
- fsps,os-dbg-enable: OS Debug Feature
- fsps,dci-en: DCI Feature
- fsps,uart2-kernel-debug-base-address: UART Debug Base Address
0x00000000: (default)
- fsps,pcie-clock-gating-disabled: Enable PCIE Clock Gating
- fsps,pcie-root-port8xh-decode: Enable PCIE Root Port 8xh Decode
- fsps,pcie8xh-decode-port-index: PCIE 8xh Decode Port Index
0x00: (default)
- fsps,pcie-root-port-peer-memory-write-enable: Enable PCIE Root Port Peer
Memory Write
- fsps,pcie-aspm-sw-smi-number: PCIE SWSMI Number
0xAA: (default)
- fsps,pcie-root-port-en: PCI Express Root Port
- fsps,pcie-rp-hide: Hide PCIE Root Port Configuration Space
- fsps,pcie-rp-slot-implemented: PCIE Root Port Slot Implement
- fsps,pcie-rp-hot-plug: Hot Plug
- fsps,pcie-rp-pm-sci: PCIE PM SCI
- fsps,pcie-rp-ext-sync: PCIE Root Port Extended Sync
- fsps,pcie-rp-transmitter-half-swing: Transmitter Half Swing
- fsps,pcie-rp-acs: ACS
- fsps,pcie-rp-clk-req-supported: Clock Request Support
- fsps,pcie-rp-clk-req-number: Configure CLKREQ Number
- fsps,pcie-rp-clk-req-detect: CLKREQ# Detection
- fsps,advanced-error-reportingt: Advanced Error Reporting
- fsps,pme-interrupt: PME Interrupt
- fsps,fatal-error-report: URR
- fsps,no-fatal-error-report: FER
- fsps,correctable-error-report: NFER
- fsps,system-error-on-fatal-error: CER
- fsps,system-error-on-non-fatal-error: SEFE
- fsps,system-error-on-correctable-error: SENFE
- fsps,pcie-rp-speed: SECE
- fsps,physical-slot-number: PCIe Speed
0: Auto (default)
1: Gen1
2: Gen2
3: Gen3
- fsps,pcie-rp-completion-timeout: Physical Slot Number
0x00, 0x01, 0x02, 0x03, 0x04, 0x05 (default)
- fsps,enable-ptm: PTM Support
- fsps,pcie-rp-aspm: ASPM
- fsps,pcie-rp-l1-substates: L1 Substates
- fsps,pcie-rp-ltr-enable: PCH PCIe LTR
- fsps,pcie-rp-ltr-config-lock: PCIE LTR Lock
- fsps,pme-b0-s5-di: PME_B0_S5 Disable bit
- fsps,pci-clock-run: PCI Clock Run
- fsps,timer8254-clk-setting: Enable/Disable Timer 8254 Clock Setting
- fsps,enable-sata: Chipset SATA
- fsps,sata-mode: SATA Mode Selection
0: AHCI (default)
1: RAID
- fsps,sata-salp-support: Aggressive LPM Support
- fsps,sata-pwr-opt-enable: SATA Power Optimization
- fsps,e-sata-speed-limit: eSATA Speed Limit
- fsps,speed-limit: SATA Speed Limit
0x1: 1.5Gb/s(Gen 1)
0x2: 3Gb/s(Gen 2)
0x3: 6Gb/s(Gen 3)
- fsps,sata-ports-enable: SATA Port
- fsps,sata-ports-dev-slp: SATA Port DevSlp
- fsps,sata-ports-hot-plug: SATA Port HotPlug
- fsps,sata-ports-interlock-sw: Mechanical Presence Switch
- fsps,sata-ports-external: External SATA Ports
- fsps,sata-ports-spin-up: Spin Up Device
- fsps,sata-ports-solid-state-drive: SATA Solid State
0: Hard Disk Drive (default)
1: Solid State Drive
- fsps,sata-ports-enable-dito-config: DITO Configuration
- fsps,sata-ports-dm-val: DM Value
0x0F: Maximum (default)
- fsps,sata-ports-dito-val: DITO Value
0x0271 (default)
- fsps,sub-system-vendor-id: Subsystem Vendor ID
0x8086: (default)
- fsps,sub-system-id: Subsystem ID
0x7270: (default)
- fsps,crid-setting: CRIDSettings
0: Disable (default)
1: CRID_1
2: CRID_2
3: CRID_3
- fsps,reset-select: ResetSelect
0x6: warm reset (default)
0xE: cold reset
- fsps,sdcard-enabled: SD Card Support (D27:F0)
- fsps,e-mmc-enabled: SeMMC Support (D28:F0)
- fsps,emmc-host-max-speed: eMMC Max Speed
0: HS400(default)
1: HS200
2: DDR50
- fsps,ufs-enabled: UFS Support (D29:F0)
- fsps,sdio-enabled: SDIO Support (D30:F0)
- fsps,gpp-lock: GPP Lock Feature
- fsps,sirq-enable: Serial IRQ
- fsps,sirq-mode: Serial IRQ Mode
0: Quiet mode (default)
1: Continuous mode
- fsps,start-frame-pulse: Start Frame Pulse Width
0: ScSfpw4Clk (default)
1: ScSfpw6Clk
2: ScSfpw8Clk
- fsps,smbus-enable: SMBus
- fsps,arp-enable: SMBus ARP Support
- fsps,num-rsvd-smbus-addresses: SMBus Table Elements
0x0080: (default)
- fsps,rsvd-smbus-address-table: Reserved SMBus Address Table
0x00: (default)
- fsps,disable-compliance-mode: XHCI Disable Compliance Mode
- fsps,usb-per-port-ctl: USB Per-Port Control
- fsps,usb30-mode: xHCI Mode
0: Disable
1: Enable
2: Auto (default)
- fsps,port-usb20-enable: Enable USB2 ports
- fsps,port-usb20-over-current-pin: USB20 Over Current Pin
- fsps,usb-otg: XDCI Support
0: Disable
1: PCI_Mode (default)
2: ACPI_mode
- fsps,hsic-support-enable: Enable XHCI HSIC Support
- fsps,port-usb30-enable: Enable USB3 ports
- fsps,port-usb30-over-current-pin: USB30 Over Current Pin
- fsps,ssic-port-enable: Enable XHCI SSIC Support
- fsps,dlane-pwr-gating: SSIC Dlane PowerGating
- fsps,vtd-enable: VT-d
- fsps,lock-down-global-smi: SMI Lock bit
- fsps,reset-wait-timer: HDAudio Delay Timer
0x012C: (default)
- fsps,rtc-lock: RTC Lock Bits
- fsps,sata-test-mode: SATA Test Mode Selection
- fsps,ssic-rate: XHCI SSIC RATE
1: A Series (default)
2: B Series
- fsps,dynamic-power-gating: SMBus Dynamic Power Gating
- fsps,pcie-rp-ltr-max-snoop-latency: Max Snoop Latency
0x0000: (default)
- fsps,pcie-rp-snoop-latency-override-mode: Snoop Latency Override
0: Disable
1: Enable
2: Auto (default)
- fsps,pcie-rp-snoop-latency-override-value: Snoop Latency Value
0x003C (default)
- fsps,pcie-rp-snoop-latency-override-multiplier: Snoop Latency Multiplier
0: 1ns
1: 32ns
2: 1024ns (default)
3: 32768ns
4: 1048576ns
5: 33554432ns
- fsps,skip-mp-init: Skip Multi-Processor Initialization
- fsps,dci-auto-detect: DCI Auto Detect
- fsps,pcie-rp-ltr-max-non-snoop-latency: Max Non-Snoop Latency
0x0000: (default)
- fsps,pcie-rp-non-snoop-latency-override-mode: Non Snoop Latency Override
- fsps,tco-timer-halt-lock: Halt and Lock TCO Timer
- fsps,pwr-btn-override-period: Power Button Override Period
000: 4s (default)
001: 6s
010: 8s
011: 10s
100: 12s
101: 14s
- fsps,pcie-rp-non-snoop-latency-override-value:
0x003C: (default)
- fsps,pcie-rp-non-snoop-latency-override-multiplier: Non Snoop Latency Value
0: 1ns
1: 32ns
2: 1024ns (default)
3: 32768ns
4: 1048576ns
5: 33554432ns
- fsps,pcie-rp-slot-power-limit-scale: PCIE Root Port Slot Power Limit Scale
0x00: (default)
- fsps,pcie-rp-slot-power-limit-value:
0x00: (default)
- fsps,disable-native-power-button: Power Button Native Mode Disable
- fsps,power-butter-debounce-mode: Power Button Debounce Mode
- fsps,sdio-tx-cmd-cntl: SDIO_TX_CMD_DLL_CNTL
0x505: (default)
- fsps,sdio-tx-data-cntl1: SDIO_TX_DATA_DLL_CNTL1
0xE: (default)
- fsps,sdio-tx-data-cntl2: SDIO_TX_DATA_DLL_CNTL2
0x22272828: (default)
- fsps,sdio-rx-cmd-data-cntl1: SDIO_RX_CMD_DATA_DLL_CNTL1
0x16161616: (default)
- fsps,sdio-rx-cmd-data-cntl2: SDIO_RX_CMD_DATA_DLL_CNTL2
0x10000: (default)
- fsps,sdcard-tx-cmd-cntl: SDCARD_TX_CMD_DLL_CNTL
0x505 (default)
- fsps,sdcard-tx-data-cntl1: SDCARD_TX_DATA_DLL_CNTL1
0xA13: (default)
- fsps,sdcard-tx-data-cntl2: SDCARD_TX_DATA_DLL_CNTL2
0x24242828: (default)
- fsps,sdcard-rx-cmd-data-cntl1: SDCARD_RX_CMD_DATA_DLL_CNTL1
0x73A3637 (default)
- fsps,sdcard-rx-strobe-cntl: SDCARD_RX_STROBE_DLL_CNTL
0x0: (default)
- fsps,sdcard-rx-cmd-data-cntl2: SDCARD_RX_CMD_DATA_DLL_CNTL2
0x10000: (default)
- fsps,emmc-tx-cmd-cntl: EMMC_TX_CMD_DLL_CNTL
0x505: (default)
- fsps,emmc-tx-data-cntl1: EMMC_TX_DATA_DLL_CNTL1
0xC11: (default)
- fsps,emmc-tx-data-cntl2: EMMC_TX_DATA_DLL_CNTL2
0x1C2A2927: (default)
- fsps,emmc-rx-cmd-data-cntl1: EMMC_RX_CMD_DATA_DLL_CNTL1
0x000D162F: (default)
- fsps,emmc-rx-strobe-cntl: EMMC_RX_STROBE_DLL_CNTL
0x0a0a: (default)
- fsps,emmc-rx-cmd-data-cntl2: EMMC_RX_CMD_DATA_DLL_CNTL2
0x1003b: (default)
- fsps,emmc-master-sw-cntl: EMMC_MASTER_DLL_CNTL
0x001: (default)
- fsps,pcie-rp-selectable-deemphasis: PCIe Selectable De-emphasis
1: -3.5 dB (default)
0: -6 dB
- fsps,monitor-mwait-enable: Monitor Mwait Enable
- fsps,hd-audio-dsp-uaa-compliance: Universal Audio Architecture
compliance for DSP enabled system
- fsps,ipc: IRQ Interrupt Polarity Control
- fsps,sata-ports-disable-dynamic-pg: Disable ModPHY dynamic power gate
- fsps,init-s3-cpu: Init CPU during S3 resume
- fsps,skip-punit-init: Skip P-unit Initialization
- fsps,port-usb20-per-port-tx-pe-half: PerPort Half Bit Pre-emphasis
- fsps,port-usb20-per-port-pe-txi-set: PerPort HS Pre-emphasis Bias
- fsps,port-usb20-per-port-txi-set: PerPort HS Transmitter Bias
- fsps,port-usb20-hs-skew-sel: Select the skew direction for HS transition
- fsps,port-usb20-i-usb-tx-emphasis-en: PerPort HS Transmitter Emphasis
- fsps,port-usb20-per-port-rxi-set: PerPort HS Receiver Bias
- fsps,port-usb20-hs-npre-drv-sel: Delay/skew's strength control for HS driver
Example:
&fsp_s {
u-boot,dm-pre-proper;
fsps,ish-enable = <0>;
fsps,enable-sata = <0>;
fsps,pcie-root-port-en = [00 00 00 00 00 01];
fsps,pcie-rp-hot-plug = [00 00 00 00 00 01];
fsps,i2c6-enable = <I2CX_ENABLE_DISABLED>;
fsps,i2c7-enable = <I2CX_ENABLE_DISABLED>;
fsps,hsuart3-enable = <HSUARTX_ENABLE_DISABLED>;
fsps,spi1-enable = <SPIX_ENABLE_DISABLED>;
fsps,spi2-enable = <SPIX_ENABLE_DISABLED>;
fsps,sdio-enabled = <0>;
...
};