Commit Graph

2085 Commits

Author SHA1 Message Date
Priyanka Jain
35cc100bba armv8: fsl-layerscape: Add vid support for LS2080AQDS
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Arpit Goel <arpit.goel@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-14 08:44:03 -07:00
Priyanka Jain
29ca713cc1 armv8: fsl-lsch3: Update VID support
VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like
LS2088A, LS2080A differs from existing logic.
-VDD voltage array is different
-Registers are different
-VDD calculation logic is different

Add new function adjust_vdd() for LSCH3 compliant SoCs

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Arpit Goel <arpit.goel@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-14 08:44:03 -07:00
York Sun
4961eafc25 armv8: layerscape: Update early MMU for DDR after initialization
In early MMU table, DDR has to be mapped as device memory to avoid
speculative access. After DDR is initialized, it needs to be updated
to normal memory to allow code execution. To simplify the code,
dram_init() is moved into a common file as a weak function.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14 08:44:03 -07:00
York Sun
36cc0de0b9 armv8: layerscape: Rewrite memory reservation
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved
at the end of DDR. DDR is spit into two or three banks. This patch
reverts commit aabd7ddb and simplifies the calculation of reserved
memory, and moves the code into common SoC file. Secure memory is
carved out first. DDR bank size is reduced. Reserved memory is then
allocated on the top of available memory. U-Boot still has access
to reserved memory as data transferring is needed. Device tree is
fixed with reduced memory size to hide the reserved memory from OS.
The same region is reserved for efi_loader.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14 08:44:03 -07:00
Tom Rini
285226785e Freescale/NXP: Migrate CONFIG_FSL_CAAM to defconfigs
In some cases this is absolutely required, so select this for some secure
features.  This also requires migration of RSA_FREESCALE_EXP

Cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: Naveen Burmi <NaveenBurmi@freescale.com>
Cc: Po Liu <po.liu@freescale.com>
Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Cc: Priyanka Jain <Priyanka.Jain@freescale.com>
Cc: Sumit Garg <sumit.garg@nxp.com>
Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
Cc: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Feng Li <feng.li_2@nxp.com>
Cc: Alison Wang <alison.wang@freescale.com>
Cc: Mingkai Hu <Mingkai.Hu@freescale.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Saksham Jain <saksham.jain@nxp.freescale.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-03-09 11:37:24 -05:00
Masahiro Yamada
e856bdcfb4 flash: complete CONFIG_SYS_NO_FLASH move with renaming
We repeated partial moves for CONFIG_SYS_NO_FLASH, but this is
not completed. Finish this work by the tool.

During this move, let's rename it to CONFIG_MTD_NOR_FLASH.
Actually, we have more instances of "#ifndef CONFIG_SYS_NO_FLASH"
than those of "#ifdef CONFIG_SYS_NO_FLASH".  Flipping the logic will
make the code more readable.  Besides, negative meaning symbols do
not fit in obj-$(CONFIG_...) style Makefiles.

This commit was created as follows:

[1] Edit "default n" to "default y" in the config entry in
    common/Kconfig.

[2] Run "tools/moveconfig.py -y -r HEAD SYS_NO_FLASH"

[3] Rename the instances in defconfigs by the following:
  find . -path './configs/*_defconfig' | xargs sed -i \
  -e '/CONFIG_SYS_NO_FLASH=y/d' \
  -e 's/# CONFIG_SYS_NO_FLASH is not set/CONFIG_MTD_NOR_FLASH=y/'

[4] Change the conditionals by the following:
  find . -name '*.[ch]' | xargs sed -i \
  -e 's/ifndef CONFIG_SYS_NO_FLASH/ifdef CONFIG_MTD_NOR_FLASH/' \
  -e 's/ifdef CONFIG_SYS_NO_FLASH/ifndef CONFIG_MTD_NOR_FLASH/' \
  -e 's/!defined(CONFIG_SYS_NO_FLASH)/defined(CONFIG_MTD_NOR_FLASH)/' \
  -e 's/defined(CONFIG_SYS_NO_FLASH)/!defined(CONFIG_MTD_NOR_FLASH)/'

[5] Modify the following manually
  - Rename the rest of instances
  - Remove the description from README
  - Create the new Kconfig entry in drivers/mtd/Kconfig
  - Remove the old Kconfig entry from common/Kconfig
  - Remove the garbage comments from include/configs/*.h

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-12 14:30:25 -05:00
Tom Rini
c83a824e62 Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	configs/ls1046aqds_defconfig
	configs/ls1046aqds_nand_defconfig
	configs/ls1046aqds_qspi_defconfig
	configs/ls1046aqds_sdcard_ifc_defconfig
	configs/ls1046aqds_sdcard_qspi_defconfig
	configs/ls1046ardb_emmc_defconfig
	configs/ls1046ardb_qspi_defconfig
	configs/ls1046ardb_sdcard_defconfig
2017-02-03 20:33:42 -05:00
Prabhakar Kushwaha
5b404be671 armv8: ls1012a: Add support of PPA
The PPA implements PSCI which requires for power managment.

Added support of PPA for LS1012AQDS, LS1012ARDB and LS1012AFRDM.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-02-03 14:30:47 -08:00
Prabhakar Kushwaha
7d559604d0 board: freescale: ls1012a: Enable secure DDR on LS1012A platforms
PPA binary needs to be relocated on secure DDR, hence marking out
a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag
is set

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-02-03 14:30:28 -08:00
York Sun
e9866cf759 armv7: ls1021aqds: Set cpo_sample for erratum A-009942
Set cpo_sample as suggested by the driver
"WARN: pls set popts->cpo_sample = 0x58 in <board>/ddr.c to optimize
cpo".

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2017-01-31 09:25:22 -08:00
Peng Fan
e389033f72 imx: mx6sxsabreauto: enable more dm drivers
Enable MMC/I2C/GPIO/PMIC/REGULATOR/PCA953X DM drivers
for mx6sxsabreauto board. Drop non-DM code.

Note:
The i.MX DM drivers has such dependency.
  MXC GPIO -> MXC I2C -> PFUZE/REGULATOR
  MXC GPIO -> PCA953X
  MXC GPIO -> FSL_USDHC

So the drivers needs to be enabled all to avoid
compiling error.

The uboot dm tree log:
=> dm tree
 Class       Probed   Name
 ----------------------------------------
  root        [ + ]    root_driver
  thermal     [   ]    |-- imx_thermal
  simple_bus  [ + ]    |-- soc
  simple_bus  [ + ]    |   |-- aips-bus@02000000
  simple_bus  [   ]    |   |   |-- spba-bus@02000000
  gpio        [ + ]    |   |   |-- gpio@0209c000
  gpio        [ + ]    |   |   |-- gpio@020a0000
  gpio        [ + ]    |   |   |-- gpio@020a4000
  gpio        [ + ]    |   |   |-- gpio@020a8000
  gpio        [ + ]    |   |   |-- gpio@020ac000
  gpio        [ + ]    |   |   |-- gpio@020b0000
  gpio        [ + ]    |   |   |-- gpio@020b4000
  simple_bus  [   ]    |   |   |-- anatop@020c8000
  simple_bus  [   ]    |   |   |-- snvs@020cc000
  pinctrl     [ + ]    |   |   `-- iomuxc@020e0000
  pinconfig   [ + ]    |   |       `-- imx6x-sabreauto
  pinconfig   [ + ]    |   |           |-- i2c2grp-1
  pinconfig   [ + ]    |   |           |-- i2c3grp-2
  pinconfig   [   ]    |   |           |-- uart1grp
  pinconfig   [ + ]    |   |           |-- usdhc3grp
  pinconfig   [   ]    |   |           |-- usdhc3grp-100mhz
  pinconfig   [   ]    |   |           |-- usdhc3grp-200mhz
  pinconfig   [ + ]    |   |           |-- usdhc4grp
  pinconfig   [ + ]    |   |           `-- vccsd3grp
  simple_bus  [ + ]    |   |-- aips-bus@02100000
  mmc         [ + ]    |   |   |-- usdhc@02198000
  mmc         [ + ]    |   |   |-- usdhc@0219c000
  i2c         [ + ]    |   |   |-- i2c@021a4000
  i2c_generic [ + ]    |   |   |   |-- generic_8
  i2c_generic [ + ]    |   |   |   `-- generic_4e
  i2c         [ + ]    |   |   `-- i2c@021a8000
  gpio        [ + ]    |   |       |-- gpio@30
  gpio        [ + ]    |   |       `-- gpio@32
  simple_bus  [   ]    |   `-- aips-bus@02200000
  simple_bus  [   ]    |       `-- spba-bus@02200000
  simple_bus  [ + ]    `-- regulators
  regulator   [ + ]        `-- regulator@0

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2017-01-27 10:53:14 +01:00
Simon Glass
cbcbf71bf2 powerpc: Drop probecpu() in favour of arch_cpu_init()
To avoid an unnecessary arch-specific call in board_init_f(), rename this
function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-01-25 17:38:41 -05:00
Tom Rini
88077715d8 NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUST
Introduce board/freescale/common/Kconfig so that we have a single place
for CONFIG options that are shared between ARM and PowerPC NXP platforms.

Cc: York Sun <york.sun@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-24 10:33:59 -05:00
Tom Rini
0675f992db Merge git://git.denx.de/u-boot-fsl-qoriq 2017-01-19 12:22:23 -05:00
Yangbo Lu
5e4a6db8f4 armv8: ls1012a: define esdhc_status_fixup for RDB board
On LS1012ARDB board, three dual 1:4 mux/demux devices drive the SDHC2
signals to eMMC, SDIO wifi, SPI and Ardiuno shield. Only when we select
eMMC and SDIO wifi, the SDHC2 could be used. Otherwise, the command
inhibit bits of eSDHC2_PRSSTAT register will never release. This would
cause below continious error messages in linux since it uses polling
mode to detect card.
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
This patch is to define esdhc_status_fixup function for RDB to disable
SDHC2 status if no SDIO wifi or eMMC is selected.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:46:52 -08:00
Yangbo Lu
208e1ae8d1 armv8: ls1012a: define esdhc_status_fixup for QDS board
The LS1012AQDS board has a hardware issue. When there is no eMMC
adapter card inserted in SDHC2 adapter slot, the command inhibit
bits of eSDHC2_PRSSTAT register will never release. This would cause
below continious error messages in linux since it uses polling mode
to detect card.
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
This patch is to define esdhc_status_fixup function for QDS to
disable SDHC2 status if no eMMC adapter card is detected.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:46:45 -08:00
Hou Zhiqiang
dccef2ec01 ls1046ardb: Add support power initialization
Add the chip power supply voltage initialization on LS1046ARDB.
Add function power_init_board(), and it will initialize the
PMIC and call the chip power initialization function.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:29:13 -08:00
Hou Zhiqiang
6424577b1b ls1046ardb: cpld: add API for selecting core volt
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:29:02 -08:00
Hou Zhiqiang
4394ad1227 pmic: pmic_mc34vr500: Add APIs to set/get SWx volt
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-01-18 09:28:57 -08:00
Tom Rini
4386feb73d SPL: Adjust more debug prints for ulong entry_point
With entry_point now being an unsigned long we need to adapt the last
two debug prints to use %lX not %X.

Fixes: 11e1479b9e ("SPL: make struct spl_image 64-bit safe")
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-11 10:45:48 -05:00
Jagan Teki
a8eac0acdc mx6ullevk: Add missing MAINTAINERS for mx6ull_14x14_evk_plugin_defconfig
Add 'Peng Fan' as MAINTAINERS of configs/mx6ull_14x14_evk_plugin_defconfig
which is missing in below commit
"imx: mx6ull_14x14_evk: add plugin defconfig"
(sha1: b90ebf49bb)

Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
2017-01-08 10:07:10 -05:00
York Sun
51370d5618 ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS
These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:52 -05:00
York Sun
146ded4d25 powerpc: T2081QDS: Remove macro T2081QDS
Use TARGET_T2081QDS from Kconfig instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:28 -05:00
York Sun
86e0a31321 powerpc: T2080RDB: Remove macro CONFIG_T2080RDB
Use TARGET_T2080RDB from Kconfig instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:27 -05:00
York Sun
80d261881f powerpc: T2080QDS: Remove macro T2080QDS
Use TARGET_T2080QDS from Kconfig instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:26 -05:00
York Sun
960286b6d9 powerpc: T1024RDB: Remove macro CONFIG_T1024RDB
Use TARGET_T1024RDB from Kconfig instead.

Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Get missing hunk in board/freescale/t102xrdb/ddr.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-04 19:40:24 -05:00
York Sun
9082405d47 powerpc: T1023RDB: Remove macro CONFIG_T1023RDB
Use TARGET_T1023RDB from Kconfig instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-01-04 19:40:22 -05:00
Fabio Estevam
cfb37772a1 mx6qsabreauto: Fix the EIM clock for the mx6qp variant
On the MX6Q the aclk_eim_slow_podf field is '1' after POR, while on the
MX6DQP it is '3'.

This makes the EIM clock to be only 66MHz on the mx6qp variant, instead of
132 MHz.

Instead of relying on the POR values for the CSMR1 register, make sure to
manually configure the clk_eim_slow_sel field as '00' so that EIM clock is
derived from AXI clock and the aclk_eim_slow_podf field as '1' so that EIM
clock can be AXI clock divided by 2.

This way a consistent EIM clock frequency is configured for all the mx6
variants.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2017-01-02 17:12:37 +01:00
Peng Fan
47895838a4 imx: mx6sllevk: add MAINTAINERS file
add MAINTAINERS files

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-12-27 11:24:19 -05:00
Tom Rini
8ea05705a7 Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Migrate CONFIG_ARCH_USE_MEMSET/MEMCPY with this merge.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-18 17:43:20 -05:00
Peng Fan
8e1d92fdbc imx: mx6sllevk: add plugin support
Add plugin support for mx6sllevk board.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-12-16 11:38:24 +01:00
Peng Fan
47f73504d8 arm: imx: add i.MX6SLL EVK board support
Add i.MX6SLL EVK board support.
1. Add imx6sll-evk device tree.
2. Enable SDHC/I2C/UART.
3. Enable REGULATOR/PMIC/I2C/GPIO/SDHC/PINCTRL driver.

Boot Log:
U-Boot 2016.11-00127-gc635871-dirty (Nov 24 2016 - 13:28:19 +0800)

CPU:   Freescale i.MX6SLL rev1.0 at 792MHz
CPU:   Commercial temperature grade (0C to 95C)Reset cause: POR
Model: Freescale i.MX6SLL EVK Board
Board: MX6SLL EVK
DRAM:  2 GiB
i2c bus 0 at 35258368, no gpio pinctrl state.
PMIC: PFUZE100! DEV_ID=0x10 REV_ID=0x21
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
In:    serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-12-16 11:38:24 +01:00
Peng Fan
708f692753 imx: clock: gate clk before changing pix clk mux
The LCDIF Pixel clock mux is not glitchless, so need
to gate before changing mux.

Also change enable_lcdif_clock prototype with a new input
parameter to indicate disable or enable.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-12-16 11:38:24 +01:00
macro.wave.z@gmail.com
c151cb5b51 ARMv8: LS1043A: Enable LS1043A default PSCI support
A most basic PSCI implementation with only one psci_version is added for
LS1043A, this can verify the generic PSCI framework, and more platform specific
implementation will be added later.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-15 11:57:56 -08:00
Shengzhou Liu
90101386f1 fsl/board/ddr: optimize board-specific cpo for erratum A-009942
Optimize board-specific cpo for erratum A-009942 on b4860qds,
ls1043aqds, ls1043ardb, ls1046aqds, ls1046ardb, ls2080ardb,
t102xqds, t102xrdb, t1040qds, t104xrdb, t208xqds, t208xrdb,
t4qds, t4rdb boards.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-15 11:56:39 -08:00
Shengzhou Liu
02fb276157 fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum
- add additional function erratum_a009942_check_cpo to check if the
  board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
  fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-05 08:31:45 -08:00
Tom Rini
4d6647ab17 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-11-30 09:57:52 -05:00
Tom Rini
6b29a395b6 Merge git://git.denx.de/u-boot-mpc85xx 2016-11-29 19:42:48 -05:00
Angus Ainslie
9cd37b02a0 imx7: SPI: add suport for SPI flash in mikroBUS slot
Enable the escpi3 nets attached to the mikroBUS slot
on the i.MX7 Sabre evalution board. Also enble the SPI flash
commands to work with the "flash click" board.

This is V2 of this patch with changes recommended by the maintainer

CC: Jagan Teki <jteki@openedev.com>
2016-11-29 17:00:31 +01:00
York Sun
37376ae0dc powerpc: MPC8641HPCN: Remove macro CONFIG_MPC8641HPCN
Use TARGET_MPC8641HPCN from Kconfig instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:16 -08:00
York Sun
51f05ff914 powerpc: MPC8610HPCD: Remove macro CONFIG_MPC8610HPCD
Use TARGET_MPC8610HPCD from Kconfig instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:16 -08:00
York Sun
49ec8aa840 powerpc: T4240RDB: Remove macro CONFIG_T4240RDB
Use CONFIG_TARGET_T4240RDB instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:15 -08:00
York Sun
12ffdb3b12 powerpc: T4160RDB: Separate from T4240RDB in Kconfig
Use TARGET_T4160RDB to simplify Kconfig options.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:15 -08:00
York Sun
673c01c708 powerpc: T4240QDS: Remove macro CONFIG_T4240QDS
Use CONFIG_TARGET_T4240QDS instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:15 -08:00
York Sun
9c21d06c67 powerpc: T4160QDS: Separate from T4240QDS in Kconfig
Use TARGET_T4160QDS to simplify Kconfig options.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:15 -08:00
York Sun
01671e668b powerpc: T2080RDB: Rename from T208XRDB in Kconfig
T208XRDB only has one target T2080RDB. Use TARGET_T2080RDB in Kconfig
and clean up existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:14 -08:00
York Sun
638d5be055 powerpc: T208XQDS: Split as T2080QDS and T2081QDS
Use two separated targets in Kconfig to simplify configurations.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:14 -08:00
York Sun
78e5699523 powerpc: T104xRDB: Remove macro CONFIG_T104xRDB and T104xD4RDB
CONFIG_T104xRDB is defined in T104xRDB.h, so it is always enabled for
all T1040RDB, T1040D4RDB, T1042RDB, T1042D4RDB, T1042RDB_PI.
CONFIG_T104XD4RDB is defined for all T1040D4RDB, T1042D4RDB.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:14 -08:00
York Sun
0167369cff powerpc: T1042RDB: Remove macro CONFIG_T1042RDB
Use TARGET_T1042RDB instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:14 -08:00
York Sun
319ed24a8a powerpc: T1042D4RDB: Separate from T1042RDB in Kconfig
Use TARGET_T1042D4RDB in Kconfig to simplify config options.
Remove macro CONFIG_T1042D4RDB.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:14 -08:00
York Sun
55ed8ae367 powerpc: T1042RDB_PI: Split from T1042RDB in Kconfig
Use separated TARGET_T1042RDB_PI to simplify config options.
Remove macro CONFIG_T1042RDB_PI.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:14 -08:00
York Sun
6fcddd0985 powerpc: T1040RDB: Remove macro CONFIG_T1040RDB
Use CONFIG_TARGET_T1040RDB instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:13 -08:00
York Sun
a016735c79 powerpc: T1040D4RDB: Separate from T1040RDB in Kconfig
Use TARGET_T1040D4RDB in Kconfig to simplify config macros. Replace
CONFIG_T1040D4RDB with TARGET_T1040D4RDB and clean up existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:13 -08:00
York Sun
5d73701073 powerpc: T1040: Remove macro CONFIG_PPC_T1040
Replace CONFIG_PPC_T1040 with ARCH_T1040 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:13 -08:00
York Sun
95a809b918 powerpc: T104XRDB: Split to T1040RDB and T1042RDB in Kconfig
Split ARCH_T104XRDB as ARCH_T1040RDB and ARCH_T1042RDB in Kconfig to
simplify config options.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:13 -08:00
York Sun
e5d5f5a8be powerpc: T1024: Remove macro CONFIG_PPC_T1024
Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:13 -08:00
York Sun
6f53bd475a powerpc: T1024QDS: Rename Kconfig option to match the name
Rename TARGET_T102XQDS to TARGET_T1024QDS to match the name.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:13 -08:00
York Sun
08c752920d powerpc: T102xRDB: Split as T1023RDB and T1024RDB
The defconfig files are separated. Splitting targets in Kconfig simplifies
config options.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:12 -08:00
York Sun
b41f192b67 powerpc: B4420: Remove macro CONFIG_PPC_B4420
Replace CONFIG_PPC_B4420 with ARCH_B4420 in Kconfig and clean up
existing macros.
2016-11-23 23:42:12 -08:00
York Sun
d46a4a1378 powerpc: B4860QDS: Remove macro CONFIG_B4860QDS
Use CONFIG_TARGET_B4860QDS instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:12 -08:00
York Sun
45a8d11782 powerpc: B4420QDS: Split from B4860QDS in Kconfig
Use TARGET_B4420QDS to simplify Kconfig options.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:12 -08:00
York Sun
161b472482 powerpc: P5040DS: Remove macro CONFIG_P5040DS
Use CONFIG_TARGET_P5040DS instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:11 -08:00
York Sun
3b83649d53 powerpc: P5020DS: Remove macro CONFIG_P5020DS
Use CONFIG_TARGET_P5020DS instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:11 -08:00
York Sun
529fb06208 powerpc: P4080DS: Remove macro CONFIG_P4080DS
Use CONFIG_TARGET_P4080DS instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:11 -08:00
York Sun
850af2c7a9 powerpc: P3041DS: Remove macro CONFIG_P3041DS
Use CONFIG_TARGET_P3041DS instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:11 -08:00
York Sun
37107facbc powerpc: P2041RDB: Remove macro CONFIG_P2041RDB
Use CONFIG_TARGET_P2041RDB instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:10 -08:00
York Sun
e5cc150945 powerpc: P1_P2_RDB_PC: Drop TARGET_P1_P2_RDB_PC
All boards covered by this group have been converted to their own
targers. Drop TARGET_P1_P2_RDB_PC from Kconfig.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:09 -08:00
York Sun
8435aa777e powerpc: P2020RDB-PC: Separate from P1_P2_RDB_PC in Kconfig
Use TARGET_P2020RDB_PC instead of sharing with P1_P2_RDB_PC to
simplify Kconfig and config macros.

Remove macro CONFIG_P2020RDB.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:09 -08:00
York Sun
b0c98b4b9f powerpc: P1025RDB: Separate from P1_P2_RDB_PC in Kconfig
Use TARGET_P1025RDB instead of sharing with P1_P2_RDB_PC to
simplify Kconfig and config macros.

Remove macro CONFIG_P1025RDB.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:09 -08:00
York Sun
4eedabfe93 powerpc: P1024RDB: Separate from P1_P2_RDB_PC in Kconfig
Use TARGET_P1024RDB instead of sharing with TARGET_P1_P2_RDB_PC to
simplify Kconfig and macros.

Remove macro CONFIG_P1024RDB.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:09 -08:00
York Sun
da439db35a powerpc: P1021RDB: Separate from P1_P2_RDB_PC in Kconfig
Use TARGET_P1021RDB instead of sharing with TARGET_P1_P2_RDB_PC to
simplify Kconfig and macros.

Remove macro CONFIG_P1021RDB.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:09 -08:00
York Sun
e9bc8a8fc1 powerpc: P1020UTM: Separate from P1_P2_RDB_P2 in Kconfig
Use TARGET_P1020UTM instead of sharing with TARGET_P1_P2_RDB_PC
to simplify Kconfig and config macros.

Remove macro CONFIG_P1020UTM.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:08 -08:00
York Sun
f404b66ce1 powerpc: P1020RDB-PD: Separate from P1_P2_RDB_PC in Kconfig
Use TARGET_P1020RDB_PD instead of sharing with P1_P2_RDB_PC
to simplify Kconfig and config macros.

Remove macro CONFIG_P1020RDB_PD.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:08 -08:00
York Sun
aa14620c2e powerpc: P1020RDB-PC: Separate from P1_P2_RDB_PC in Kconfig
Use TARGET_P1020RDB_PC instead of sharing with TARGET_P1_P2_RDB_PC
to simplify Kconfig and config macros.

Remove macro CONFIG_P1020RDB_PC.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:08 -08:00
York Sun
fedae6ebaf powerpc: P1020MBG: Separate from P1_P2_RDB_PC in Kconfig
Use TARGET_P1020MBG instead of sharing with TARGET_P1_P2_RDB_PC to
simplify Kconfig and other macros.

Remove macro CONFIG_P1020MBG.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:08 -08:00
York Sun
aa6e241a4c powerpc: P1022DS: Remove macro CONFIG_P1022DS
Use CONFIG_TARGET_P1022DS instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:07 -08:00
York Sun
7601686c60 powerpc: P1010RDB: Remove macros CONFIG_P1010RDB_PA and CONFIG_P1010RDB_PB
Remove CONFIG_P1010RDB_PA and CONFIG_P1010RDB_PB and split TARGET_P1010RDB
to TARGET_P1010RDB_PA and TARGET_P1010RDB_PB in Kconfig.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:07 -08:00
York Sun
2fe0cd8582 powerpc: MPC8572DS: Remove macro CONFIG_MPC8572DS
Use CONFIG_TARGET_MPC8572DS instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:06 -08:00
York Sun
3759b5b649 powerpc: MPC8569MDS: Remove macro CONFIG_MPC8569MDS
Use CONFIG_TARGET_MPC8569MDS instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:06 -08:00
York Sun
2f2d54b7cd powerpc: MPC8555CDS: Remove macro CONFIG_MPC8555CDS
Use CONFIG_TARGET_MPC8555CDS instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:05 -08:00
York Sun
4096f350d5 powerpc: MPC8541CDS: Remove macro CONFIG_MPC8541CDS
Replace with CONFIG_TARGET_MPC8541CDS from Kconfig.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:05 -08:00
York Sun
30411e7cfc powerpc: MPC8536DS: Remove macro CONFIG_MPC8536DS
Use CONFIG_TARGET_MPC8536DS instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:04 -08:00
York Sun
ae59dded8d powerpc: MPC8544DS: Remove macro CONFIG_MPC8544DS
Use CONFIG_TARGET_MPC8544DS instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:03 -08:00
York Sun
4d08d5d9d5 powerpc: MPC8548CDS: Remove macro CONFIG_MPC8548CDS
Use CONFIG_TARGET_MPC8548CDS instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:03 -08:00
Priyanka Jain
9ae836cde7 armv8: fsl-layerscape: Add NXP LS2088A SoC support
The QorIQ LS2088A SoC is built on layerscape architecture.

It is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)It supports TZASC module

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-22 11:37:54 -08:00
Yuan Yao
e2f95e3a6a arm: ls1021a: improve the core frequency to 1.2GHZ
Change core clock to 1.2GHz in the configurations for SD and NAND boot.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21 09:20:32 -08:00
Shaohui Xie
c435a7c8c1 armv8: ls2080aqds: fix SGMII repeater settings
The current value to check whether the PHY was configured has dependency
on MC, it expects MC to start PCS AN, this is not true during boot up,
so it should be changed to remove the dependency.

The PHY's register space should be restore to default after accessing
extended space.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21 09:20:32 -08:00
Priyanka Jain
fc35addea2 armv8: ls2080a: Update serdes protocol support
Add these serdes protocols
Serdes1: 0x39, 0x4B, 0x4C, 0x4D
Serdes2: 0x47, 0x57

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
[YS: Revise commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21 09:20:32 -08:00
Shaohui Xie
fdc2b54cb8 armv8: ls1046aqds: add lpuart support
LPUART0 is used by default, and it's using platform clock.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21 09:20:32 -08:00
Feng Li
20c700f8da armv7: Add support of ls1021a-iot board
The patch adds support for Freescale ls1021a-iot board.

Signed-off-by: Feng Li <feng.li_2@nxp.com>
[YS: rewrite commit message, fix whitespace in Kconfig]
Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-21 09:20:32 -08:00
Alexander Graf
215b1fb9fa ls2080ardb: Reserve DP-DDR RAM
The DP-DDR shouldn't be exposed as conventional memory to an OS, so let's
rather claim it's a reserved region in the EFI memory map

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17 14:18:55 +01:00
Alexander Graf
b7b8410a8f ls2080: Exit dpaa only right before exiting U-Boot
On ls2080 we have a separate network fabric component which we need to
shut down before we enter Linux (or any other OS). Along with that also
comes configuration of the fabric using a description file.

Today we always stop and configure the fabric in the boot script and
(again) exit it on device tree generation. This works ok for the normal
booti case, but with bootefi the payload we're running may still want to
access the network.

So let's add a new fsl_mc command that defers configuration and stopping
the hardware to when we actually exit U-Boot, so that we can still use
the fabric from an EFI payload.

For existing boot scripts, nothing should change with this patch.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
[agraf: Fix x86 build]
2016-11-17 14:18:55 +01:00
Diego Dorta
2ffec69b6f mx6ull_14x14_evk: Add README file
Add a README file to help users getting started with the board.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-11-13 15:54:35 -05:00
Fabio Estevam
4b6035da48 mx6sabresd: Make Ethernet functional again
Since commit ce412b79e7 ("drivers: net: phy: atheros: add separate
config for AR8031") ethernet does not work on mx6sabresd.

This commit correctly assigns ar8031_config() as the configuration
function for AR8031 in the same way as done in the Linux kernel.

However, on mx6sabresd design we need some additional configuration,
such as enabling the 125 MHz AR8031 output that needs to be done
in the board file.

This also aligns with the same method that the kernel performs
the AR8031 fixup in arch/arm/mach-imx/mach-imx6q.c.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-11-06 06:59:27 -05:00
Tom Rini
4f892924d2 Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	common/Kconfig
	configs/dms-ba16_defconfig
2016-10-28 11:12:03 -04:00
Jagan Teki
03bf9d58b9 imx: s/docs\/README.imximage/doc\/README.imximage/g
Fixed typo for doc/README.imximage on respective imximage.cfg files.

Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26 16:53:16 +02:00
Peng Fan
ab1f75a7db imx: mx6ullevk: correct boot device macro
Correct boot device macro according to kconfig entry
in common/Kconfig

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-10-24 10:58:18 +02:00
Peng Fan
204d1f60c1 imx: mx6ullevk: support plugin
Add plugin code for mx6ullevk.
Define CONFIG_USE_IMXIMG_PLUGIN in defconfig file to use plugin code.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-10-24 10:58:18 +02:00
Diego Dorta
9cc3ad6c6a mx6sabresd: Add README file
Add a README to explain the steps for booting mx6sabresd in different ways:
    1. Booting via Normal U-Boot (u-boot.imx)
    2. Booting via SPL (SPL and u-boot.img)
    3. Booting via Falcon mode (SPL launches the kernel directly)

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
2016-10-17 09:18:32 +02:00
Diego Dorta
d96796ca23 mx6sabresd: Add Falcon mode support
Allow i.MX6Q Sabre SD to load the kernel and dtb via SPL in Falcon mode.

Based on the Falcon mode code for MX6 Gateworks Ventana board.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
2016-10-17 09:18:01 +02:00
Zhao Qiang
c5938c10ef pbl: use "wait" command instead of "flush" command
PBL flush command is restricted to CCSR memory space. So use WAIT
PBI command to provide enough time for data to get flush in
target memory.

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
[York Sun: rewrap commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2016-10-14 10:21:30 -07:00
Zhao Qiang
ec90ac7359 Txxx/RCW: Split unified RCW to RCWs for sd, spi and nand.
T series boards use unified RCW for sd, spi and nand boot.
Now split txxx_rcw.cfg to txxx_sd_rcw.cfg, txxx_spi_rcw.cfg
and txxx_nand_rcw.cfg for SPI/NAND/SD boot.
And modify RCW[PBI_SRC] for them:
	PBI_SRC=5            for SPI 24-bit addressing
	PBI_SRC=6            for SD boot
	PBI_SRC=14           for IFC NAND boot

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-10-14 10:21:03 -07:00
Tom Rini
711b534120 Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	include/configs/ls1021aqds.h
	include/configs/ls1021atwr.h
2016-10-12 08:29:42 -04:00
Tom Rini
f5fd45ff64 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-10-08 09:33:37 -04:00
Simon Glass
ea022a3775 spi: Move freescale-specific code into a private header
At present there are two SPI functions only used by freescale which are
defined in the spi_flash.h header. One function name matches an existing
generic SPL function.

Move these into a private header to avoid confusion.

Arcturus looks like it does not actually support SPI, so drop the SPI code
from that board.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-10-06 15:07:35 -04:00
Xiaoliang Yang
f85a8e8d1d armv7: LS1021a: enable i-cache in start.S
Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and
ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First
stage of u-boot can run faster after that. There is a description
about skip lowlevel init in board/freescale/ls1021atwr/README.

Signed-off-by: Xiaoliang Yang <xiaoliang.yang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-10-06 09:55:08 -07:00
Sumit Garg
b259732d36 fsl_sec_mon: Update driver for Security Monitor
Update the API's for transition of Security Monitor states. Instead
of providing both initial and final states for transition, just
provide final state for transition as Security Monitor driver will
take care of it internally.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
[York Sun: Reformatted commit message slightly]
Reviewed-by: York Sun <york.sun@nxp.com>
2016-10-06 09:54:14 -07:00
Peng Fan
55a42b33f2 arm: imx: add i.MX6ULL 14x14 EVK board support
Add i.MX6ULL EVK board support:
Add device tree file, which is copied from NXP Linux.
Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR.
The uart iomux settings are still keeped in board file.

Boot Log:
U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800)

CPU:   Freescale i.MX6ULL rev1.0 at 396MHz
CPU:   Commercial temperature grade (0C to 95C) at 15C
Reset cause: POR
Model: Freescale i.MX6 ULL 14x14 EVK Board
Board: MX6ULL 14x14 EVK
DRAM:  512 MiB
MMC:   initialized IMX pinctrl driver
FSL_SDHC: 0, FSL_SDHC: 1
In:    serial
Out:   serial
Err:   serial
Net:   CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0
=> mmc dev 1
switch to partitions #0, OK
mmc1 is current device

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-10-04 15:42:07 +02:00
Fabio Estevam
3b30eece27 mx6sabresd: Make SPL DDR configuration to match the DCD table
When using SPL on i.mx6 we frequently notice some DDR initialization
mismatches between the SPL code and the non-SPL code.

This causes stability issues like the ones reported at 7dbda25ecd
("mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang") and also:
http://lists.denx.de/pipermail/u-boot/2016-September/266355.html .

As the non-SPL code have been tested for long time and proves to be reliable,
let's configure the DDR in the exact same way as the non-SPL case.

The idea is simple: just use the DCD table and write directly to the DDR
registers.

Retrieved the DCD tables from:
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
and
board/freescale/mx6sabresd/mx6qp.cfg
(NXP U-Boot branch imx_v2015.04_4.1.15_1.0.0_ga)

This method makes it easier for people converting from non-SPL to SPL code.

Other benefit is that the SPL binary size is reduced from 44 kB to 39.9 kB.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-10-04 12:01:14 +02:00
Sriram Dash
a5c289b9bc usb: fsl: Rename fdt_fixup_dr_usb
The function fdt_fixup_dr_usb is specific to fsl/nxp. So,
make the function name explicit and rename fdt_fixup_dr_usb
into fsl_fdt_fixup_dr_usb.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
2016-09-27 23:30:27 +02:00
Tom Rini
cbe7706ab8 Merge git://git.denx.de/u-boot-fsl-qoriq
trini: Drop local memset() from
examples/standalone/mem_to_mem_idma2intr.c

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-26 17:10:56 -04:00
York Sun
1fdcc8dfc7 driver: ddr: fsl_mmdc: Pass board parameters through data structure
Instead of using multiple macros, a data structure is used to pass
board-specific parameters to MMDC DDR driver.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-26 08:53:07 -07:00
Masahiro Yamada
1221ce459d treewide: replace #include <asm/errno.h> with <linux/errno.h>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap <asm-generic/errno.h>)

Replace all include directives for <asm/errno.h> with <linux/errno.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-23 17:55:42 -04:00
Masahiro Yamada
63a7578e4e arch, board: squash lines for immediate return
Remove unneeded variables and assignments.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Reviewed-by: Angelo Dureghello <angelo@sysam.it>
2016-09-23 17:53:53 -04:00
Shaohui Xie
126fe70d77 armv8: ls1046aqds: Add LS1046AQDS board support
LS1046AQDS Specification:
-------------------------
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe: supports Gen 1 and Gen 2

SATA 3.0: one SATA 3.0 port

USB 3.0: two micro AB connector and one type A connector

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14 14:11:10 -07:00
Mingkai Hu
dd02936f81 armv8: ls1046ardb: Add LS1046ARDB board support
LS1046ARDB Specification:
-------------------------
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 512 Mbyte NAND flash
 * Two 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card
 * On-board 4G eMMC

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe:
 * PCIe1 (SerDes2 Lane0) to miniPCIe slot
 * PCIe2 (SerDes2 Lane1) to x2 PCIe slot
 * PCIe3 (SerDes2 Lane2) to x4 PCIe slot

SATA:
 * SerDes2 Lane3 to SATA port

USB 3.0: one super speed USB 3.0 type A port
	 one Micro-AB port

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14 14:11:00 -07:00
Shengzhou Liu
b9e745bbe2 driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012a
This general MMDC driver adds basic support for Freescale MMDC
(Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8
LS1012A SoC for DDR3L, there will be a update to this driver to
support more flexible configuration if new features (DDR4, multiple
controllers/chip selections, etc) are implimented in future.

Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/
LS1012AFRDM.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14 14:08:22 -07:00
Shengzhou Liu
93a6d3284c armv7:ls1021a: Enable workaround for DDR erratum A-009942
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14 14:08:15 -07:00
Hongbo Zhang
214ffae02d nxp: ls102xa: add LS1 PSCI system suspend
The deep sleep function of LS1 platform, is mapped into PSCI system
suspend function, this patch adds implementation of it.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14 14:08:04 -07:00
York Sun
b63a950629 armv8: ls2080a: Remove debug server support
Debug server feature has been dropped from roadmap.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-09-14 14:07:19 -07:00
Hou Zhiqiang
b392a6d4b0 fsl-layerscape: Add workaround for PCIe erratum A010315
As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14 14:07:13 -07:00
Hou Zhiqiang
664b652058 fsl: csu: add an API to set R/W permission to PCIe
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14 14:07:08 -07:00
Hou Zhiqiang
c37fdbdbb0 fsl: csu: add an API to set individual device access permission
Add this API to make the individual device is able to be set to
the specified permission.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14 14:07:02 -07:00
Hou Zhiqiang
341238fd13 arm: fsl-layerscape: move forward the non-secure access permission setup
Move forward the basic non-secure access enable operation, so the
subsequent individual device access permission can override it.
And collect the dispersed callers in board level, and then move
them to SoC level.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14 14:06:56 -07:00
Sumit Garg
285c74811e board: ls1043ardb: move sec_init to board_init
sec_init() which was earlier called in misc_init_r()
is now done in board_init() before PPA init as SEC
block will be used during PPA image validation.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-14 14:06:23 -07:00
Fabio Estevam
ab25f0f69f mx6ul_14x14_ev: Enable the CCGR clocks earlier
To be in the safe side we need to enable the CCGR clocks prior
to calling arch_cpu_init().

Inspired by Tim Harvey's commit d783c2744f ("imx: ventana: fix boot to SD").

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Tested-by: Eric Nelson <eric@nelint.com>
2016-09-06 18:22:48 +02:00
Fabio Estevam
b343417e29 mx6ul_14x14_evk: Adjust SPL DDR3 settings
Adjust DDR3 initialization done in SPL by comparing them against
the NXP DCD table.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
2016-09-06 18:22:48 +02:00
Fabio Estevam
7dbda25ecd mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang
When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk,
we observe a hang when going into the lowest operational point of cpufreq.

This hang issue does not happen on the NXP U-Boot version.

After comparing the SPL DDR initialization against the DCD table
from NXP U-Boot, the key difference that causes the hang is the
MDREF register setting:

DATA 4 0x021B0020 0x00000800

,which means:

REF_SEL = 0 --> Periodic refresh cycle: 64kHz
REFR = 1 ---> Refresh Rate - 2 refreshes

So adjust the MDREF initialization for mx6ul_evk accordingly
to fix the kernel hang issue at low bus frequency.

Reported-by: Eric Nelson <eric@nelint.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
2016-09-06 18:22:48 +02:00
Fabio Estevam
edf0093732 mx6: ddr: Allow changing REFSEL and REFR fields
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.

Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:

$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4      0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800

So introduce a mechanism for users to be able to configure
REFSEL and REFR fields as needed.

Keep all the mx6 SPL users in their current REF_SEL and REFR values,
so no functional changes for the existing users.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
2016-09-06 18:22:48 +02:00
Fabio Estevam
946db0cbd0 mx7dsabresd: Directly write to register LDOGCTL
Register LDOGCTL contains only bit 0 as a valid bit, so there is no need
to do a read-modify-write operation.

Simplify the code by writing directly to this register.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06 18:22:48 +02:00
Fabio Estevam
78eed0a6d5 mx7dsabresd: Directly write to register LDOGCTL
Register LDOGCTL contains only bit 0 as a valid bit, so there is no need
to do a read-modify-write operation.

Simplify the code by writing directly to this register.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06 18:22:48 +02:00
Eric Nelson
eb3813ad1a mx6ul_14x14_evk: don't use array for SD2 card detect pad
Only a single pad is changed to change sdhc2_dat3 from an
SDIO pin to and from GPIO4:5, so remove the array and use
the imx_iomux_v3_setup_pad() routine.

Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06 18:22:48 +02:00
Fabio Estevam
76b21efd55 mx7dsabresd: Print secure/non-secure mode info
mx7dsabresd has two targets:

- mx7dsabresd_defconfig: boots in non-secure mode
- mx7dsabresd_secure_defconfig: boots in secure mode

Print the mode that is being used to help users to easily identify
which target is running on the board.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06 18:22:48 +02:00
Masahiro Yamada
c21fc7e223 treewide: fix "followings" to "following"
Most of them are my mistakes.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-26 17:04:58 -04:00
York Sun
473af36a88 board/freescale: Update MAINTAINERS files
Update maintainers for secure boot targets.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-08-02 09:47:34 -07:00
Tom Rini
4711e7f7af Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-07-28 08:45:00 -04:00
Fabio Estevam
4c97077ce7 mx7dsabresd: MAINTAINERS: Add mx7dsabresd_secure_defconfig
Add an entry for the mx7dsabresd_secure_defconfig target.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-07-28 13:27:21 +02:00
Diego Dorta
ec1935a243 mx6ul_14x14_evk: Remove unused define
Remove unused define constant.

Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-07-28 13:27:21 +02:00
Qianyu Gong
8401c7103d armv8: ls1043aqds: add IFC fixup in case QSPI is enabled
QSPI and IFC are pin-multiplexed on LS1043AQDS board. If QSPI is
enabled, IFC would not be initialized correctly. So disable the IFC
node for Linux.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-26 09:03:50 -07:00
Hongbo Zhang
aeb901f2a6 ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention
This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
    psci_version,
    psci_features,
    psci_cpu_suspend,
    psci_affinity_info,
    psci_system_reset,
    psci_system_off.

Tested on LS1021aQDS, LS1021aTWR.

Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-26 09:02:49 -07:00
York Sun
dbb9d04fbd armv8: ls1043aqds: Update MAINTAINERS
Add ls1043aqds_lpuart_defconfig to file list.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-07-26 09:01:58 -07:00
York Sun
0c14c4d65b armv8: ls2080aqds: Update MAINTAINERS
Add ls2080aqds_qspi_defconfig to file list.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-07-26 09:01:58 -07:00
Sumit Garg
e7e720c2ce arm: ls1021atwr: Add SD secure boot target
Add SD secure boot target for ls1021atwr.
Implement board specific spl_board_init() to setup CAAM stream ID and
corresponding stream ID in SMMU. Change the u-boot size defined by a
macro for copying the main U-Boot by SPL to also include the u-boot
Secure Boot header size as header is appended to u-boot image. So header
will also be copied from SD to DDR.

Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-26 09:01:49 -07:00
Sumit Garg
028ac8c733 SECURE_BOOT: Enable chain of trust in SPL framework
Override jump_to_image_no_args function to include validation of
u-boot image using spl_validate_uboot before jumping to u-boot image.
Also define macros in SPL framework to enable crypto operations.

Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-26 09:01:35 -07:00
Sumit Garg
aa36c84edf powerpc/mpc85xx: T104x: Add nand secure boot target
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In non-secure boot scenario from NAND, this address will map to CPC
configured as SRAM. But in case of secure boot, this default address
always maps to IBR (Internal Boot ROM).
The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G
address space i.e. 0x0 - 0xDFFFFFFF.

For secure boot target from NAND, the text base for SPL is kept same as
non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will
be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000)
As a the virtual and physical address of CPC would be different. The
virtual address 0xFFFx_xxxx needs to be mapped to physical address
0xBFFx_xxxx.

Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000
and update DCFG SCRTACH1 register with location of Header required for
secure boot.

The changes are similar to
commit 467a40dfe3
    powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041

While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC
is only 256K and thus SPL framework is used.
The changes are only applicable for SPL U-Boot running out of CPC SRAM
and not the next level U-Boot loaded on DDR.

Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-21 11:09:34 -07:00
Sumit Garg
8f01397ba7 powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPL
As part of Chain of Trust for Secure boot, the SPL U-Boot will validate
the next level U-boot image. Add a new function spl_validate_uboot to
perform the validation.

Enable hardware crypto operations in SPL using SEC block.
In case of Secure Boot, PAMU is not bypassed. For allowing SEC block
access to CPC configured as SRAM, configure PAMU.

Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-21 11:09:23 -07:00
Hou Zhiqiang
0e68a3694d ARMv8/ls1043ardb: Integrate FSL PPA
The PPA use PSCI to make secondary cores bootup. So when PPA was
enabled, add the CONFIG_ARMV8_PSCI to identify the SMP boot-method
between PSCI and spin-table.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-07-19 11:34:26 -07:00
York Sun
e61a7534e3 armv8: Move secure_ram variable out of generic global data
Secure_ram variable was put in generic global data. But only ARMv8
uses this variable. Move it to ARM specific data structure.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-07-15 09:01:43 -07:00
Vanessa Maegima
d6b0c46818 mx6sxsabresd: Avoid hardcoded RAM size
Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
we should better use imx_ddr_size() function, which automatically
determines the RAM size.

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
2016-07-12 17:58:49 +02:00
Vanessa Maegima
432a8a5547 mx6sxsabreauto: Avoid hardcoded RAM size
Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
we should better use imx_ddr_size() function, which automatically
determines the RAM size.

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-07-12 17:58:49 +02:00
Vanessa Maegima
8259e9c9ad mx6slevk: Avoid hardcoded RAM size
Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
we should better use imx_ddr_size() function, which automatically
determines the RAM size.

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-07-12 17:58:49 +02:00
Vanessa Maegima
369012e7e9 mx6qsabreauto: Avoid hardcoded RAM size
Instead of passing the total RAM size via PHYS_SDRAM_SIZE option,
we should better use imx_ddr_size() function, which automatically
determines the RAM size.

Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-07-12 17:58:48 +02:00
Qianyu Gong
581ff00bf7 armv8: ls1043aqds: use configurable clock
Get the clocks from FPGA through I2C, if IFC is disabled.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-28 12:08:43 -07:00
Qianyu Gong
a2fd238e49 armv8: ls1043aqds: fix to get boot device info from FPGA
The LBMAP switches on the board will tell which boot device is used.
Only QSPI boot is supported if the boot device is IFCCard.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-24 08:33:34 -07:00
Tom Rini
a10a31ec91 Merge branch 'master' of git://git.denx.de/u-boot-usb
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
2016-06-18 23:46:21 -04:00
Tom Rini
2372b00129 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-06-18 23:44:22 -04:00
Peng Fan
0d7cdc2abf imx: mx6ulevk: change QSPI PAD DSE to 120ohm
The current pad DSE for QSPI is 60ohm. This setting cause
too strong drive to clock and data signals. Need to change
the DSE to 120ohm for better signal quality.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-06-18 10:29:18 +02:00
Peng Fan
288683280f imx6ulevk: fix LCD_nPWREN setting
Q901 is PMOS, LCD_nPWREN should be at low voltage then output is 3V3.
If LCD_nPWREN is high, output is 2.4V which is not correct.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-06-18 10:29:18 +02:00
Peng Fan
85801579e1 imx6ulevk: fix 74LV OE usage
Fix 74LV OE gpio index. gpio index is wrong,
so gpio output will not have effect, since we
use wrong GPIO5_IO18, but not correct GPIO5_IO8.

And at the end of the initialization of 74lv init, should
keep OE voltage level at LOW to make 74lv output the correct
voltage.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-06-18 10:29:18 +02:00
Ye Li
0fcb85cc0c mx7dsabresd: Fix LCD_PWR_EN output setting
LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect
D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3
is actually 1.2V.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-06-18 10:29:18 +02:00
Marco Franchi
6c51a3644e mx6sabresd: Allow LVDS backlight to be functional after a kernel reboot
Currently the LVDS backlight does not work in U-Boot after a “reboot” comand
in the kernel.

This problem occurs because the kernel uses this pin in PWM mode and U-Boot
does not configure the backlight pin as GPIO functionality.

So fix the problem by explicitly configuring the backlight pin as GPIO in
U-Boot.

Signed-off-by: Marco Franchi <marco.franchi@nxp.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-06-18 10:25:54 +02:00
Stefano Babic
dc557e9a1f Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
2016-06-18 10:25:13 +02:00
Sriram Dash
ef53b8c4ce usb: xhci: fsl: Add workaround for USB erratum A008751
This patch is doing the following:
1. Implementing the errata for LS2080.
2. Adding fixup for fdt for LS2080.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2016-06-13 15:16:46 +02:00
Eddy Petrișor
9702ec00e9 armv8: s32v234: Introduce basic support for s32v234evb
Add initial support for NXP's S32V234 SoC and S32V234EVB board.

The S32V230 family is designed to support computation-intensive applications
for image processing. The S32V234, as part of the S32V230 family, is a
high-performance automotive processor designed to support safe
computation-intensive applications in the area of vision and sensor fusion.

Code originally writen by:
Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com>
Original-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com>
Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com>

Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>
2016-06-13 08:56:35 -04:00
Tom Rini
3fc304b8d7 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2016-06-12 12:51:34 -04:00
Yuan Yao
a646f66981 armv8: ls2080aqds: Enable QSPI boot support
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10 13:45:01 -07:00
Yuan Yao
453418f2d2 armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10 13:45:00 -07:00
Yuan Yao
8c77ef8540 armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable
When QSPI is enabled, NOR flash and QIXIS can't be accessed
through IFC due to pin mux. Enable I2C QIXIS access and I2C
early init to read the sysclk and ddrclk.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10 13:44:59 -07:00
Yuan Yao
916d9f099e armv8: ls2080aqds: Select QSPI CLK div via SCFG
QSPI module output SCLK divisor value is configured through SCFG.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10 13:44:59 -07:00
Pratiyush Mohan Srivastava
30677deefd board: ls2080a: Add "mcinitcmd" env for MC & DPL deployment
Environment variable mcinitcmd is defined to initiate MC and DPL
deployment from the location where it is stored (NOR, NAND, SD, SATA,
USB) during booting. If this variable is not defined then macro
MC_BOOT_ENV_VAR will be null and MC will not be booted and DPL will
not be applied during U-boot booting.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10 13:44:58 -07:00
Tom Rini
cc749523ae Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2016-06-04 12:12:26 -04:00
Tom Rini
715b3a9b24 Merge git://git.denx.de/u-boot-nand-flash 2016-06-04 08:49:47 -04:00
Robert P. J. Day
23d4e5ba49 freescale: Tweak various Makefiles to remove redundancy, fix aesthetics
No intended functional change, just remove redundancies in some
Makefiles, and make whitespace aesthetics uniform.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 22:14:27 -07:00
Shengzhou Liu
5349928277 board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot
We should use unified setup_ddr_tlbs() for spl boot and non-spl boot
to make sure 'M' bit is set for DDR TLB to maintain cache coherence.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 22:12:54 -07:00
Sumit Garg
ed4708aaea powerpc/board: SPL: Enable malloc flag in global data.
For malloc to work in SPL framework enable GD_FLG_FULL_MALLOC_INIT
flag in global data after allocating memory using mem_malloc_init.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 22:12:06 -07:00
Scott Wood
17cb4b8f32 mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_data
These functions are part of the Linux 4.6 sync.  They are being added
before the main sync patch in order to make it easier to address the
issue across all NAND drivers (many/most of which do not closely track
their Linux counterparts) separately from other merge issues.

Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-03 20:27:48 -05:00
Prabhakar Kushwaha
ff78aa2ba1 armv8: ls1012a: Add support of ls1012afrdm board
QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
development platform, with a complete debugging environment.
The LS1012AFRDM board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 14:12:51 -07:00
Prabhakar Kushwaha
3b6e3898c2 armv8: ls1012a: Add support of ls1012ardb board
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 14:12:51 -07:00
Prabhakar Kushwaha
9d044fcb8c armv8: ls1012a: Add support of ls1012aqds board
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 14:12:51 -07:00
Abhimanyu Saini
16dacb26a5 board: freescale: common: Add flag for LBMAP brdcfg reg offset
Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP
configuration register instead of hardcoding it in
set_lbmap() function.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 14:12:51 -07:00
Abhimanyu Saini
3faaa24b11 board: freescale: common: Conditionally compile IFC QXIS func
Check if qixis supports memory-mapped read/write
before compiling IFC based qixis read/write functions.

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 14:12:50 -07:00
Prabhakar Kushwaha
ddd8a08052 armv8: fsl-layerscape: Organize SoC overview at common location
SoC overviews are getting repeated across board folders.
So, Organize SoC overview at common location i.e. fsl-layerscape/doc

Also move README.lsch2 and README.lsch3 in same folder.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 14:12:50 -07:00
Shaohui Xie
3e06ba8f25 armv8: ls1043aqds: fix usb PWRFAULT setting
SCFG_USBPWRFAULT_DEDICATED instead of SCFG_USBPWRFAULT_SHARED should
be used for USB 3 & 2.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 14:12:49 -07:00
York Sun
931e8751af board: ls2080ardb: qds: Fix compiling issue when FSL_MC_ENET not defined
U-Boot should continue to work without management complex (MC).
Fix compiling errors and warnings.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-03 14:12:48 -07:00
Vincent Siles
c4f97b1f53 board: ls102xa: Fix ICID setup
LS102A ref manual dictates that ICID have to be written to the MSB
of the ICID register, not to the LSB.

Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
2016-06-03 14:12:06 -07:00
Shengzhou Liu
e04f9d0c2f board/freescale: Update ddr clk_adjust
This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 14:06:57 -07:00
Sebastien Bourdelin
cb82c38eff cosmetic: mx6slevk: Minor coding-style fix
Fix the brace indentation in board_mmc_init().

Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
2016-05-31 17:37:44 +02:00
Peng Fan
73f366bb5b imx: mx6qsabreauto: drop duplicated net phy configuration
In 'commit d584c68ce0f5bf2f430ccfb2ba00bd506206fb91',
ar8031 is changed to use ar8035_config. ar8035_config
actually does the same thing as mx6_rgmii_rework, so
drop mx6_rgmii_rework and board_phy_config.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2016-05-31 17:36:47 +02:00
Robert P. J. Day
7ffe3cd62e Delete tests of CONFIG_OF_LIBFDT when testing CONFIG_OF_BOARD_SETUP
Since CONFIG_OF_BOARD_SETUP depends on CONFIG_OF_LIBFDT:

  config OF_BOARD_SETUP
          bool "Set up board-specific details in device tree before boot"
          depends on OF_LIBFDT
          ...

remove superfluous tests of CONFIG_OF_LIBFDT when testing for
CONFIG_OF_BOARD_SETUP.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
[trini: Typo fix: s/ifdefi/ifdef/]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-05-27 15:41:16 -04:00
Tom Rini
826d06dbdd Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2016-05-25 07:19:31 -04:00
Ying Zhang
d1fc8ed485 powerpc:t4240rdb: Disable the non-existent ethernet ports on T4240RDB
Disable the non-existent ethernet ports on T4240RDB:FM1_DTSEC5,
FM1_DTSEC6, FM2_DTSEC5 and FM2_DTSEC6.

Signed-off-by: Ying Zhang <ying.zhang22455@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-24 17:11:03 -07:00
Peng Fan
83e1394242 board: mx6sabresd/auto: use simpler runtime cpu dection macros
Use simpler runtime cpu dection macros.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-05-24 14:59:57 +02:00
York Sun
9272611e99 powerpc/t208xrdb: Update MAINTAINERS file
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2016-05-19 10:47:12 -07:00
York Sun
a4d3074209 powerpc/t208xqds: Update MAINTAINERS file
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2016-05-19 10:47:11 -07:00
Shaohui Xie
7942550a14 armv8: ls1043ardb: invert irq pin polarity for AQR105 PHY
To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity
by setting relative bit in SCFG_INTPCR register, because AQR105
interrupt is low active but GIC accepts high active.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18 08:51:47 -07:00
Alex Porosanu
404bf4547e arch/arm, arch/powerpc: add # of SEC engines on the SOC
Some SOCs, specifically the ones in the C29x familiy can have
multiple security engines. This patch adds a system configuration
define which indicates the maximum number of SEC engines that
can be found on a SoC.

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18 08:51:46 -07:00
Qianyu Gong
9718650f8c armv8: ls1043ardb: fix types of variables
Using u16 for cfg_rcw_src and u8 for sd1refclk_sel is enough.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18 08:51:45 -07:00
Qianyu Gong
ec93abe6f7 armv8: ls1043a: remove redundant code in board files
gd->env_addr will be initialized in env_init() in
common/env_nowhere.c if CONFIG_ENV_IS_NOWHERE is defined.
So no need to do it again.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18 08:51:45 -07:00
Qianyu Gong
869bf86811 armv8/ls1043ardb: fix the limitation of using 'cpld reset'
The current 'cpld reset' will just write global_rst register
but couldn't switch to NOR boot if the board's switches are
for NAND/SD boot. So need to write rcw source registers for
NOR boot as well.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18 08:51:44 -07:00
Vincent Siles
12cbf20d78 arm: uniform usage of u32 in ls102x caam config
Mix usage of uint32_t and u32 fixed in favor of u32.

Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18 08:51:44 -07:00