Merge branch 'master' of git://www.denx.de/git/u-boot-imx

This commit is contained in:
Tom Rini 2016-07-28 08:45:00 -04:00
commit 4711e7f7af
78 changed files with 3885 additions and 405 deletions

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@ -102,6 +102,7 @@ F: arch/arm/include/asm/arch-imx/
F: arch/arm/include/asm/arch-mx*/
F: arch/arm/include/asm/arch-vf610/
F: arch/arm/include/asm/imx-common/
F: board/freescale/*mx*/
ARM HISILICON
M: Peter Griffin <peter.griffin@linaro.org>

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@ -148,6 +148,10 @@ config TARGET_PLATINUM_TITANIUM
bool "platinum-titanium"
select SUPPORT_SPL
config TARGET_PCM058
bool "Phytec PCM058 i.MX6 Quad"
select SUPPORT_SPL
config TARGET_SECOMX6
bool "secomx6 boards"
@ -178,6 +182,18 @@ config TARGET_XPRESS
select DM_THERMAL
select SUPPORT_SPL
config TARGET_ZC5202
bool "zc5202"
select SUPPORT_SPL
select DM
select DM_THERMAL
config TARGET_ZC5601
bool "zc5601"
select SUPPORT_SPL
select DM
select DM_THERMAL
endchoice
config SYS_SOC
@ -192,6 +208,7 @@ source "board/boundary/nitrogen6x/Kconfig"
source "board/ccv/xpress/Kconfig"
source "board/compulab/cm_fx6/Kconfig"
source "board/congatec/cgtqmx6eval/Kconfig"
source "board/el/el6x/Kconfig"
source "board/embest/mx6boards/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6qsabreauto/Kconfig"
@ -200,6 +217,7 @@ source "board/freescale/mx6slevk/Kconfig"
source "board/freescale/mx6sxsabresd/Kconfig"
source "board/freescale/mx6sxsabreauto/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/phytec/pcm058/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/seco/Kconfig"

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@ -281,7 +281,7 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
case PLL_BUS:
if (!is_mx6ul()) {
if (pfd_num == 3) {
/* No PFD3 on PPL2 */
/* No PFD3 on PLL2 */
return 0;
}
}
@ -433,9 +433,9 @@ static u32 get_axi_clk(void)
if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
else
root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
else
root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
} else
root_freq = get_periph_clk();

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@ -3,6 +3,8 @@ if ARCH_MX7
config MX7
bool
select ROM_UNIFIED_SECTIONS
select CPU_V7_HAS_VIRT
select CPU_V7_HAS_NONSEC
default y
config MX7D
@ -25,12 +27,19 @@ config TARGET_WARP7
select DM
select DM_THERMAL
config TARGET_COLIBRI_IMX7
bool "Support Colibri iMX7S/iMX7D modules"
select DM
select DM_SERIAL
select DM_THERMAL
endchoice
config SYS_SOC
default "mx7"
source "board/freescale/mx7dsabresd/Kconfig"
source "board/toradex/colibri_imx7/Kconfig"
source "board/warp7/Kconfig"
endif

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@ -248,6 +248,20 @@ int arch_cpu_init(void)
return 0;
}
#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
if (is_mx7d())
setenv("soc", "imx7d");
else
setenv("soc", "imx7s");
#endif
return 0;
}
#endif
#ifdef CONFIG_SERIAL_TAG
void get_board_serial(struct tag_serialnr *serialnr)
{

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@ -102,7 +102,7 @@ iomux_v3_cfg_t const usdhc1_pads[] = {
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
gd->ram_size = imx_ddr_size();
return 0;
}

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@ -12,6 +12,7 @@
#include <dm.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <mtd_node.h>
#include <netdev.h>
#include <errno.h>
#include <usb.h>
@ -28,6 +29,7 @@
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm/platform_data/serial_mxc.h>
#include <jffs2/load_kernel.h>
#include "common.h"
#include "../common/eeprom.h"
#include "../common/common.h"
@ -581,6 +583,17 @@ int cm_fx6_setup_ecspi(void) { return 0; }
#ifdef CONFIG_OF_BOARD_SETUP
#define USDHC3_PATH "/soc/aips-bus@02100000/usdhc@02198000/"
struct node_info nodes[] = {
/*
* Both entries target the same flash chip. The st,m25p compatible
* is used in the vendor device trees, while upstream uses (the
* documented) jedec,spi-nor comptatible.
*/
{ "st,m25p", MTD_DEV_TYPE_NOR, },
{ "jedec,spi-nor", MTD_DEV_TYPE_NOR, },
};
int ft_board_setup(void *blob, bd_t *bd)
{
u32 baseboard_rev;
@ -589,6 +602,8 @@ int ft_board_setup(void *blob, bd_t *bd)
char baseboard_name[16];
int err;
fdt_shrink_to_minimum(blob); /* Make room for new properties */
/* MAC addr */
if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
fdt_find_and_setprop(blob,
@ -607,15 +622,16 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0; /* Assume not an early revision SB-FX6m baseboard */
if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) {
fdt_shrink_to_minimum(blob); /* Make room for new properties */
nodeoffset = fdt_path_offset(blob, USDHC3_PATH);
fdt_delprop(blob, nodeoffset, "cd-gpios");
fdt_find_and_setprop(blob, USDHC3_PATH, "non-removable",
fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd",
NULL, 0, 1);
fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend",
NULL, 0, 1);
}
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
return 0;
}
#endif

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@ -678,14 +678,6 @@ int overwrite_console(void)
return 1;
}
static bool is_mx6q(void)
{
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
return true;
else
return false;
}
int board_early_init_f(void)
{
setup_iomux_uart();
@ -703,7 +695,7 @@ int board_init(void)
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
if (is_mx6q())
if (is_mx6dq())
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
else
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
@ -760,7 +752,7 @@ int misc_init_r(void)
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
if (is_mx6q())
if (is_mx6dq())
setenv("board_rev", "MX6Q");
else
setenv("board_rev", "MX6DL");
@ -1053,7 +1045,7 @@ static void spl_dram_init(int width)
return;
}
if (is_mx6q()) {
if (is_mx6dq()) {
mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g);
} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {

25
board/el/el6x/Kconfig Normal file
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@ -0,0 +1,25 @@
if TARGET_ZC5202
config SYS_BOARD
default "el6x"
config SYS_VENDOR
default "el"
config SYS_CONFIG_NAME
default "zc5202"
endif
if TARGET_ZC5601
config SYS_BOARD
default "el6x"
config SYS_VENDOR
default "el"
config SYS_CONFIG_NAME
default "zc5601"
endif

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@ -0,0 +1,8 @@
EL6X BOARD
M: Stefano Babic <sbabic@denx.de>
S: Maintained
F: board/el/el6x/
F: include/configs/zc5202.h
F: include/configs/zc5601.h
F: configs/zc5202_defconfig
F: configs/zc5601_defconfig

7
board/el/el6x/Makefile Normal file
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@ -0,0 +1,7 @@
#
# Copyright (C) Stefano Babic <sbabic@denx.de>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := el6x.o

640
board/el/el6x/el6x.c Normal file
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@ -0,0 +1,640 @@
/*
* Copyright (C) Stefano Babic <sbabic@denx.de>
*
* Based on other i.MX6 boards
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include <asm/arch/mx6-ddr.h>
DECLARE_GLOBAL_DATA_PTR;
#define OPEN_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_DISABLE | (0 << 12))
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define I2C_PMIC 1
#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
#define ETH_PHY_RESET IMX_GPIO_NR(2, 4)
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
}
#ifdef CONFIG_TARGET_ZC5202
iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
/* Switch Reset */
MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
/* Switch Interrupt */
MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* use CRS and COL pads as GPIOs */
MX6_PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(OPEN_PAD_CTRL),
MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(OPEN_PAD_CTRL),
};
#define BOARD_NAME "EL6x-ZC5202"
#else
iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#define BOARD_NAME "EL6x-ZC5601"
#endif
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
#ifdef CONFIG_TARGET_ZC5202
/* set CRS and COL to input */
gpio_direction_input(IMX_GPIO_NR(4, 9));
gpio_direction_input(IMX_GPIO_NR(4, 12));
/* Reset Switch */
gpio_direction_output(ETH_PHY_RESET , 0);
mdelay(2);
gpio_set_value(ETH_PHY_RESET, 1);
#endif
}
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#ifdef CONFIG_MXC_SPI
#ifdef CONFIG_TARGET_ZC5202
iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const ecspi3_pads[] = {
MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT7__GPIO4_IO28 | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT9__GPIO4_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_DISP0_DAT10__GPIO4_IO31 | MUX_PAD_CTRL(SPI_PAD_CTRL),
};
#endif
iomux_v3_cfg_t const ecspi4_pads[] = {
MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
? (IMX_GPIO_NR(3, 20)) : -1;
}
static void setup_spi(void)
{
#ifdef CONFIG_TARGET_ZC5202
gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0");
gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1");
gpio_direction_output(IMX_GPIO_NR(5, 17), 1);
gpio_direction_output(IMX_GPIO_NR(5, 9), 1);
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
#endif
gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0");
gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
enable_spi_clk(true, 3);
}
#endif
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | I2C_PAD,
.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | I2C_PAD,
.gp = IMX_GPIO_NR(2, 30)
},
.sda = {
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 13)
}
};
static struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
.gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
.gp = IMX_GPIO_NR(1, 5)
},
.sda = {
.i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | I2C_PAD,
.gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | I2C_PAD,
.gp = IMX_GPIO_NR(7, 11)
}
};
iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC2_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
break;
case USDHC4_BASE_ADDR:
ret = 1; /* eMMC/uSDHC4 is always present */
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
#ifndef CONFIG_SPL_BUILD
int ret;
int i;
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* mmc0 SD2
* mmc1 SD3
* mmc2 eMMC
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
i + 1, CONFIG_SYS_FSL_USDHC_NUM);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
#else
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned reg = readl(&psrc->sbmr1) >> 11;
/*
* Upon reading BOOT_CFG register the following map is done:
* Bit 11 and 12 of BOOT_CFG register can determine the current
* mmc port
* 0x1 SD1
* 0x2 SD2
* 0x3 SD4
*/
switch (reg & 0x3) {
case 0x1:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
break;
case 0x3:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
break;
}
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
#endif
}
#endif
/*
* Do not overwrite the console
* Use always serial for U-Boot console
*/
int overwrite_console(void)
{
return 1;
}
int board_eth_init(bd_t *bis)
{
setup_iomux_enet();
enable_enet_clk(1);
return cpu_eth_init(bis);
}
int board_early_init_f(void)
{
setup_iomux_uart();
setup_spi();
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
return 0;
}
int power_init_board(void)
{
struct pmic *p;
int ret;
unsigned int reg;
ret = power_pfuze100_init(I2C_PMIC);
if (ret)
return ret;
p = pmic_get("PFUZE100");
ret = pmic_probe(p);
if (ret)
return ret;
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
/* Increase VGEN3 from 2.5 to 2.8V */
pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
reg &= ~LDO_VOL_MASK;
reg |= LDOB_2_80V;
pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
/* Increase VGEN5 from 2.8 to 3V */
pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
reg &= ~LDO_VOL_MASK;
reg |= LDOB_3_00V;
pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
/* Set SW1AB stanby volage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
reg &= ~SW1x_STBY_MASK;
reg |= SW1x_0_975V;
pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
reg &= ~SW1xCONF_DVSSPEED_MASK;
reg |= SW1xCONF_DVSSPEED_4US;
pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
/* Set SW1C standby voltage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
reg &= ~SW1x_STBY_MASK;
reg |= SW1x_0_975V;
pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
reg &= ~SW1xCONF_DVSSPEED_MASK;
reg |= SW1xCONF_DVSSPEED_4US;
pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
return 0;
}
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
/* 8 bit bus width */
{"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
{NULL, 0},
};
#endif
int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
setenv("board_name", BOARD_NAME);
return 0;
}
int checkboard(void)
{
puts("Board: ");
puts(BOARD_NAME "\n");
return 0;
}
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
#include <libfdt.h>
const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_sdclk_0 = 0x00020030,
.dram_sdclk_1 = 0x00020030,
.dram_cas = 0x00020030,
.dram_ras = 0x00020030,
.dram_reset = 0x00020030,
.dram_sdcke0 = 0x00003000,
.dram_sdcke1 = 0x00003000,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = 0x00003030,
.dram_sdodt1 = 0x00003030,
.dram_sdqs0 = 0x00000030,
.dram_sdqs1 = 0x00000030,
.dram_sdqs2 = 0x00000030,
.dram_sdqs3 = 0x00000030,
.dram_sdqs4 = 0x00000030,
.dram_sdqs5 = 0x00000030,
.dram_sdqs6 = 0x00000030,
.dram_sdqs7 = 0x00000030,
.dram_dqm0 = 0x00020030,
.dram_dqm1 = 0x00020030,
.dram_dqm2 = 0x00020030,
.dram_dqm3 = 0x00020030,
.dram_dqm4 = 0x00020030,
.dram_dqm5 = 0x00020030,
.dram_dqm6 = 0x00020030,
.dram_dqm7 = 0x00020030,
};
const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
.grp_ddr_type = 0x000C0000,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_addds = 0x00000030,
.grp_ctlds = 0x00000030,
.grp_ddrmode = 0x00020000,
.grp_b0ds = 0x00000030,
.grp_b1ds = 0x00000030,
.grp_b2ds = 0x00000030,
.grp_b3ds = 0x00000030,
.grp_b4ds = 0x00000030,
.grp_b5ds = 0x00000030,
.grp_b6ds = 0x00000030,
.grp_b7ds = 0x00000030,
};
const struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p0_mpwldectrl0 = 0x001F001F,
.p0_mpwldectrl1 = 0x001F001F,
.p1_mpwldectrl0 = 0x00440044,
.p1_mpwldectrl1 = 0x00440044,
.p0_mpdgctrl0 = 0x434B0350,
.p0_mpdgctrl1 = 0x034C0359,
.p1_mpdgctrl0 = 0x434B0350,
.p1_mpdgctrl1 = 0x03650348,
.p0_mprddlctl = 0x4436383B,
.p1_mprddlctl = 0x39393341,
.p0_mpwrdlctl = 0x35373933,
.p1_mpwrdlctl = 0x48254A36,
};
/* MT41K128M16JT-125 */
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 1600,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0x00C03F3F, &ccm->CCGR0);
writel(0x0030FC03, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
writel(0x00FFF300, &ccm->CCGR4);
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
/*
* This section requires the differentiation between iMX6 Sabre boards, but
* for now, it will configure only for the mx6q variant.
*/
static void spl_dram_init(void)
{
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = 2,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
/* single chip select */
.ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
};
mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
gpr_init();
/* iomux and setup of i2c */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
#endif

View File

@ -64,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
gd->ram_size = imx_ddr_size();
return 0;
}

View File

@ -61,7 +61,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
gd->ram_size = imx_ddr_size();
return 0;
}

View File

@ -106,7 +106,7 @@ static int port_exp_direction_output(unsigned gpio, int value)
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
gd->ram_size = imx_ddr_size();
return 0;
}

View File

@ -64,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
gd->ram_size = imx_ddr_size();
return 0;
}

View File

@ -60,9 +60,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
#define IOX_SDI IMX_GPIO_NR(5, 10)
#define IOX_STCP IMX_GPIO_NR(5, 7)
#define IOX_SHCP IMX_GPIO_NR(5, 11)

View File

@ -4,3 +4,4 @@ S: Maintained
F: board/freescale/mx7dsabresd
F: include/configs/mx7dsabresd.h
F: configs/mx7dsabresd_defconfig
F: configs/mx7dsabresd_secure_defconfig

View File

@ -132,14 +132,14 @@ void setup_ventana_i2c(void)
/* common to add baseboards */
static iomux_v3_cfg_t const gw_gpio_pads[] = {
/* RS232_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
/* SD3_VSELECT */
IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
};
/* prototype */
static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
/* RS232_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
/* PANLEDG# */
IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
@ -183,6 +183,8 @@ static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
};
static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
/* RS232_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
/* MSATA_EN */
IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* PANLEDG# */
@ -214,6 +216,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
};
static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
/* RS232_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
/* MSATA_EN */
IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* CAN_STBY */
@ -245,6 +249,8 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
};
static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
/* RS232_EN# */
IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
/* MSATA_EN */
IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* CAN_STBY */
@ -332,6 +338,219 @@ static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
/* Digital I/O */
struct dio_cfg gw51xx_dio[] = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
IMX_GPIO_NR(1, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
{
{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
IMX_GPIO_NR(1, 18),
{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
4
},
};
struct dio_cfg gw52xx_dio[] = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
IMX_GPIO_NR(1, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
{
{ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
IMX_GPIO_NR(1, 20),
{ 0, 0 },
0
},
};
struct dio_cfg gw53xx_dio[] = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
IMX_GPIO_NR(1, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
{
{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
IMX_GPIO_NR(1, 20),
{ 0, 0 },
0
},
};
struct dio_cfg gw54xx_dio[] = {
{
{ IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
IMX_GPIO_NR(1, 9),
{ IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
1
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
IMX_GPIO_NR(2, 9),
{ IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
3
},
{
{ IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
IMX_GPIO_NR(2, 10),
{ IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
4
},
};
struct dio_cfg gw551x_dio[] = {
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
};
struct dio_cfg gw552x_dio[] = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
IMX_GPIO_NR(1, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
{
{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
IMX_GPIO_NR(1, 20),
{ 0, 0 },
0
},
{
{IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18) },
IMX_GPIO_NR(5, 18),
{ 0, 0 },
0
},
{
{IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20) },
IMX_GPIO_NR(5, 20),
{ 0, 0 },
0
},
{
{IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21) },
IMX_GPIO_NR(5, 21),
{ 0, 0 },
0
},
{
{IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22) },
IMX_GPIO_NR(5, 22),
{ 0, 0 },
0
},
{
{IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23) },
IMX_GPIO_NR(5, 23),
{ 0, 0 },
0
},
{
{IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25) },
IMX_GPIO_NR(5, 25),
{ 0, 0 },
0
},
};
struct dio_cfg gw553x_dio[] = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
IMX_GPIO_NR(1, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
{
{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
IMX_GPIO_NR(1, 18),
{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
4
},
};
/*
* Board Specific GPIO
@ -341,33 +560,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
{
.gpio_pads = gw54xx_gpio_pads,
.num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
.dio_cfg = {
{
{ IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
IMX_GPIO_NR(1, 9),
{ IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
1
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
IMX_GPIO_NR(2, 9),
{ IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
3
},
{
{ IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
IMX_GPIO_NR(2, 10),
{ IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
4
},
},
.num_gpios = 4,
.dio_cfg = gw54xx_dio,
.dio_num = ARRAY_SIZE(gw54xx_dio),
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 10),
@ -385,33 +579,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
{
.gpio_pads = gw51xx_gpio_pads,
.num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
.dio_cfg = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
IMX_GPIO_NR(1, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
{
{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
IMX_GPIO_NR(1, 18),
{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
4
},
},
.num_gpios = 4,
.dio_cfg = gw51xx_dio,
.dio_num = ARRAY_SIZE(gw51xx_dio),
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 10),
@ -428,33 +597,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
{
.gpio_pads = gw52xx_gpio_pads,
.num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
.dio_cfg = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
IMX_GPIO_NR(1, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
{
{ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
IMX_GPIO_NR(1, 20),
{ 0, 0 },
0
},
},
.num_gpios = 4,
.dio_cfg = gw52xx_dio,
.dio_num = ARRAY_SIZE(gw52xx_dio),
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 7),
@ -468,39 +612,15 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.usb_sel = IMX_GPIO_NR(1, 2),
.wdis = IMX_GPIO_NR(7, 12),
.msata_en = GP_MSATA_SEL,
.rs232_en = GP_RS232_EN,
},
/* GW53xx */
{
.gpio_pads = gw53xx_gpio_pads,
.num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
.dio_cfg = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
IMX_GPIO_NR(1, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
{
{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
IMX_GPIO_NR(1, 20),
{ 0, 0 },
0
},
},
.num_gpios = 4,
.dio_cfg = gw53xx_dio,
.dio_num = ARRAY_SIZE(gw53xx_dio),
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 7),
@ -513,39 +633,15 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.vidin_en = IMX_GPIO_NR(3, 31),
.wdis = IMX_GPIO_NR(7, 12),
.msata_en = GP_MSATA_SEL,
.rs232_en = GP_RS232_EN,
},
/* GW54xx */
{
.gpio_pads = gw54xx_gpio_pads,
.num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
.dio_cfg = {
{
{ IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
IMX_GPIO_NR(1, 9),
{ IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
1
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
IMX_GPIO_NR(2, 9),
{ IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
3
},
{
{ IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
IMX_GPIO_NR(2, 10),
{ IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
4
},
},
.num_gpios = 4,
.dio_cfg = gw54xx_dio,
.dio_num = ARRAY_SIZE(gw54xx_dio),
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 7),
@ -560,27 +656,15 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
.pcie_sson = IMX_GPIO_NR(1, 20),
.wdis = IMX_GPIO_NR(5, 17),
.msata_en = GP_MSATA_SEL,
.rs232_en = GP_RS232_EN,
},
/* GW551x */
{
.gpio_pads = gw551x_gpio_pads,
.num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2,
.dio_cfg = {
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
},
.num_gpios = 2,
.dio_cfg = gw551x_dio,
.dio_num = ARRAY_SIZE(gw551x_dio),
.leds = {
IMX_GPIO_NR(4, 7),
},
@ -592,33 +676,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
{
.gpio_pads = gw552x_gpio_pads,
.num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
.dio_cfg = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
IMX_GPIO_NR(1, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
{
{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
IMX_GPIO_NR(1, 20),
{ 0, 0 },
0
},
},
.num_gpios = 4,
.dio_cfg = gw552x_dio,
.dio_num = ARRAY_SIZE(gw552x_dio),
.leds = {
IMX_GPIO_NR(4, 6),
IMX_GPIO_NR(4, 7),
@ -634,33 +693,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
{
.gpio_pads = gw553x_gpio_pads,
.num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2,
.dio_cfg = {
{
{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
IMX_GPIO_NR(1, 16),
{ 0, 0 },
0
},
{
{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
IMX_GPIO_NR(1, 19),
{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
2
},
{
{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
IMX_GPIO_NR(1, 17),
{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
3
},
{
{ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
IMX_GPIO_NR(1, 18),
{ IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
4
},
},
.num_gpios = 4,
.dio_cfg = gw553x_dio,
.dio_num = ARRAY_SIZE(gw553x_dio),
.leds = {
IMX_GPIO_NR(4, 10),
IMX_GPIO_NR(4, 11),
@ -682,10 +716,6 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
gpio_request(GP_USB_OTG_PWR, "usbotg_pwr");
gpio_direction_output(GP_USB_OTG_PWR, 0);
/* RS232_EN# */
gpio_request(GP_RS232_EN, "rs232_en");
gpio_direction_output(GP_RS232_EN, 0);
if (board >= GW_UNKNOWN)
return;
@ -693,6 +723,12 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
imx_iomux_v3_setup_multiple_pads(gpio_cfg[board].gpio_pads,
gpio_cfg[board].num_pads);
/* RS232_EN# */
if (gpio_cfg[board].rs232_en) {
gpio_request(gpio_cfg[board].rs232_en, "rs232_en");
gpio_direction_output(gpio_cfg[board].rs232_en, 0);
}
/* GW522x Uses GPIO3_IO23 for PCIE_RST# */
if (board == GW52xx && info->model[4] == '2')
gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23);
@ -788,7 +824,10 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
return;
/* RS232_EN# */
gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
if (gpio_cfg[board].rs232_en) {
gpio_direction_output(gpio_cfg[board].rs232_en,
(hwconfig("rs232")) ? 0 : 1);
}
/* MSATA Enable */
if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
@ -806,7 +845,7 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
* Configure DIO pinmux/padctl registers
* see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
*/
for (i = 0; i < gpio_cfg[board].num_gpios; i++) {
for (i = 0; i < gpio_cfg[board].dio_num; i++) {
struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
@ -851,8 +890,10 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
printf("MSATA: %s\n", (hwconfig("msata") ?
"enabled" : "disabled"));
}
printf("RS232: %s\n", (hwconfig("rs232")) ?
"enabled" : "disabled");
if (gpio_cfg[board].rs232_en) {
printf("RS232: %s\n", (hwconfig("rs232")) ?
"enabled" : "disabled");
}
}
}

View File

@ -48,8 +48,8 @@
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/*
* each baseboard has 4 user configurable Digital IO lines which can
* be pinmuxed as a GPIO or in some cases a PWM
* each baseboard has an optional set user configurable Digital IO lines which
* can be pinmuxed as a GPIO or in some cases a PWM
*/
struct dio_cfg {
iomux_v3_cfg_t gpio_padmux[2];
@ -63,8 +63,8 @@ struct ventana {
iomux_v3_cfg_t const *gpio_pads;
int num_pads;
/* DIO pinmux/val */
struct dio_cfg dio_cfg[4];
int num_gpios;
struct dio_cfg *dio_cfg;
int dio_num;
/* various gpios (0 if non-existent) */
int leds[3];
int pcie_rst;
@ -78,6 +78,8 @@ struct ventana {
int usb_sel;
int wdis;
int msata_en;
int rs232_en;
/* various features */
bool usd_vsel;
};

View File

@ -491,14 +491,54 @@ int imx6_pcie_toggle_reset(void)
* GPIO's as PERST# signals for its downstream ports - configure the GPIO's
* properly and assert reset for 100ms.
*/
#define MAX_PCI_DEVS 32
struct pci_dev {
pci_dev_t devfn;
unsigned short vendor;
unsigned short device;
unsigned short class;
unsigned short busno; /* subbordinate busno */
struct pci_dev *ppar;
};
struct pci_dev pci_devs[MAX_PCI_DEVS];
int pci_devno;
int pci_bridgeno;
void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
unsigned short vendor, unsigned short device,
unsigned short class)
{
int i;
u32 dw;
struct pci_dev *pdev = &pci_devs[pci_devno++];
debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
/* store array of devs for later use in device-tree fixup */
pdev->devfn = dev;
pdev->vendor = vendor;
pdev->device = device;
pdev->class = class;
pdev->ppar = NULL;
if (class == PCI_CLASS_BRIDGE_PCI)
pdev->busno = ++pci_bridgeno;
else
pdev->busno = 0;
/* fixup RC - it should be 00:00.0 not 00:01.0 */
if (PCI_BUS(dev) == 0)
pdev->devfn = 0;
/* find dev's parent */
for (i = 0; i < pci_devno; i++) {
if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
pdev->ppar = &pci_devs[i];
break;
}
}
/* assert downstream PERST# */
if (vendor == PCI_VENDOR_ID_PLX &&
(device & 0xfff0) == 0x8600 &&
PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
@ -660,13 +700,14 @@ static const struct boot_mode board_boot_modes[] = {
int misc_init_r(void)
{
struct ventana_board_info *info = &ventana_info;
char buf[256];
int i;
/* set env vars based on EEPROM data */
if (ventana_info.model[0]) {
char str[16], fdt[36];
char *p;
const char *cputype = "";
int i;
/*
* FDT name will be prefixed with CPU type. Three versions
@ -729,6 +770,19 @@ int misc_init_r(void)
setenv("mem_mb", str);
}
/* Set a non-initialized hwconfig based on board configuration */
if (!strcmp(getenv("hwconfig"), "_UNKNOWN_")) {
sprintf(buf, "hwconfig=");
if (gpio_cfg[board_type].rs232_en)
strcat(buf, "rs232;");
for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
char buf1[32];
sprintf(buf1, "dio%d:mode=gpio;", i);
if (strlen(buf) + strlen(buf1) < sizeof(buf))
strcat(buf, buf1);
}
setenv("hwconfig", buf);
}
/* setup baseboard specific GPIO based on board and env */
setup_board_gpio(board_type, info);
@ -802,6 +856,224 @@ static inline void ft_delprop_path(void *blob, const char *path,
}
}
#if defined(CONFIG_CMD_PCI)
#define PCI_ID(x) ( \
(PCI_BUS(x->devfn)<<16)| \
(PCI_DEV(x->devfn)<<11)| \
(PCI_FUNC(x->devfn)<<8) \
)
#define PCIE_PATH "/soc/pcie@0x01000000"
int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
{
uint32_t reg[5];
char node[32];
int np;
sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
np = fdt_subnode_offset(blob, par, node);
if (np >= 0)
return np;
np = fdt_add_subnode(blob, par, node);
if (np < 0) {
printf(" %s failed: no space\n", __func__);
return np;
}
memset(reg, 0, sizeof(reg));
reg[0] = cpu_to_fdt32(PCI_ID(dev));
fdt_setprop(blob, np, "reg", reg, sizeof(reg));
return np;
}
/* build a path of nested PCI devs for all bridges passed through */
int fdt_add_pci_path(void *blob, struct pci_dev *dev)
{
struct pci_dev *bridges[MAX_PCI_DEVS];
int k, np;
/* build list of parents */
np = fdt_path_offset(blob, PCIE_PATH);
if (np < 0)
return np;
k = 0;
while (dev) {
bridges[k++] = dev;
dev = dev->ppar;
};
/* now add them the to DT in reverse order */
while (k--) {
np = fdt_add_pci_node(blob, np, bridges[k]);
if (np < 0)
break;
}
return np;
}
/*
* The GW16082 has a hardware errata errata such that it's
* INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
* of this normal PCI interrupt swizzling will not work so we will
* provide an irq-map via device-tree.
*/
int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
{
int len;
int host;
uint32_t imap_new[8*4*4];
const uint32_t *imap;
uint32_t irq[4];
uint32_t reg[4];
int i;
/* build irq-map based on host controllers map */
host = fdt_path_offset(blob, PCIE_PATH);
if (host < 0) {
printf(" %s failed: missing host\n", __func__);
return host;
}
/* use interrupt data from root complex's node */
imap = fdt_getprop(blob, host, "interrupt-map", &len);
if (!imap || len != 128) {
printf(" %s failed: invalid interrupt-map\n",
__func__);
return -FDT_ERR_NOTFOUND;
}
/* obtain irq's of host controller in pin order */
for (i = 0; i < 4; i++)
irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
/*
* determine number of swizzles necessary:
* For each bridge we pass through we need to swizzle
* the number of the slot we are on.
*/
struct pci_dev *d;
int b;
b = 0;
d = dev->ppar;
while(d && d->ppar) {
b += PCI_DEV(d->devfn);
d = d->ppar;
}
/* create new irq mappings for slots12-15
* <skt> <idsel> <slot> <skt-inta> <skt-intb>
* J3 AD28 12 INTD INTA
* J4 AD29 13 INTC INTD
* J5 AD30 14 INTB INTC
* J2 AD31 15 INTA INTB
*/
for (i = 0; i < 4; i++) {
/* addr matches bus:dev:func */
u32 addr = dev->busno << 16 | (12+i) << 11;
/* default cells from root complex */
memcpy(&imap_new[i*32], imap, 128);
/* first cell is PCI device address (BDF) */
imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
/* third cell is pin */
imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
/* sixth cell is relative interrupt */
imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
}
fdt_setprop(blob, np, "interrupt-map", imap_new,
sizeof(imap_new));
reg[0] = cpu_to_fdt32(0xfff00);
reg[1] = 0;
reg[2] = 0;
reg[3] = cpu_to_fdt32(0x7);
fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
fdt_setprop_string(blob, np, "device_type", "pci");
fdt_setprop_cell(blob, np, "#address-cells", 3);
fdt_setprop_cell(blob, np, "#size-cells", 2);
printf(" Added custom interrupt-map for GW16082\n");
return 0;
}
/* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
{
char *tmp, *end;
char mac[16];
unsigned char mac_addr[6];
int j;
sprintf(mac, "eth1addr");
tmp = getenv(mac);
if (tmp) {
for (j = 0; j < 6; j++) {
mac_addr[j] = tmp ?
simple_strtoul(tmp, &end,16) : 0;
if (tmp)
tmp = (*end) ? end+1 : end;
}
fdt_setprop(blob, np, "local-mac-address", mac_addr,
sizeof(mac_addr));
printf(" Added mac addr for eth1\n");
return 0;
}
return -1;
}
/*
* PCI DT nodes must be nested therefore if we need to apply a DT fixup
* we will walk the PCI bus and add bridge nodes up to the device receiving
* the fixup.
*/
void ft_board_pci_fixup(void *blob, bd_t *bd)
{
int i, np;
struct pci_dev *dev;
for (i = 0; i < pci_devno; i++) {
dev = &pci_devs[i];
/*
* The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
* an EEPROM at i2c1-0x50.
*/
if ((dev->vendor == PCI_VENDOR_ID_TI) &&
(dev->device == 0x8240) &&
(i2c_set_bus_num(1) == 0) &&
(i2c_probe(0x50) == 0))
{
np = fdt_add_pci_path(blob, dev);
if (np > 0)
fdt_fixup_gw16082(blob, np, dev);
}
/* ethernet1 mac address */
else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
(dev->device == 0x4380))
{
np = fdt_add_pci_path(blob, dev);
if (np > 0)
fdt_fixup_sky2(blob, np, dev);
}
}
}
#endif /* if defined(CONFIG_CMD_PCI) */
/*
* called prior to booting kernel or by 'fdt boardsetup' command
*
@ -811,6 +1083,10 @@ static inline void ft_delprop_path(void *blob, const char *path,
* - board (full model from EEPROM)
* - peripherals removed from DTB if not loaded on board (per EEPROM config)
*/
#define UART1_PATH "/soc/aips-bus@02100000/serial@021ec000"
#define WDOG1_PATH "/soc/aips-bus@02000000/wdog@020bc000"
#define WDOG2_PATH "/soc/aips-bus@02000000/wdog@020c0000"
#define GPIO3_PATH "/soc/aips-bus@02000000/gpio@020a4000"
int ft_board_setup(void *blob, bd_t *bd)
{
struct ventana_board_info *info = &ventana_info;
@ -864,94 +1140,140 @@ int ft_board_setup(void *blob, bd_t *bd)
ft_sethdmiinfmt(blob, getenv("hdmiinfmt"));
/*
* disable serial2 node for GW54xx for compatibility with older
* 3.10.x kernel that improperly had this node enabled in the DT
* Board model specific fixups
*/
if (board_type == GW54xx) {
i = fdt_path_offset(blob,
"/soc/aips-bus@02100000/serial@021ec000");
switch (board_type) {
case GW51xx:
/*
* disable wdog node for GW51xx-A/B to work around
* errata causing wdog timer to be unreliable.
*/
if (rev >= 'A' && rev < 'C') {
i = fdt_path_offset(blob, WDOG1_PATH);
if (i)
fdt_status_disabled(blob, i);
}
/* GW51xx-E adds WDOG1_B external reset */
if (rev < 'E')
ft_delprop_path(blob, WDOG1_PATH,
"fsl,ext-reset-output");
break;
case GW52xx:
/* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
if (info->model[4] == '2') {
u32 handle = 0;
u32 *range = NULL;
i = fdt_node_offset_by_compatible(blob, -1,
"fsl,imx6q-pcie");
if (i)
range = (u32 *)fdt_getprop(blob, i,
"reset-gpio", NULL);
if (range) {
i = fdt_path_offset(blob, GPIO3_PATH);
if (i)
handle = fdt_get_phandle(blob, i);
if (handle) {
range[0] = cpu_to_fdt32(handle);
range[1] = cpu_to_fdt32(23);
}
}
/* these have broken usd_vsel */
if (strstr((const char *)info->model, "SP318-B") ||
strstr((const char *)info->model, "SP331-B"))
gpio_cfg[board_type].usd_vsel = 0;
/* GW520x-E adds WDOG1_B external reset */
if (info->model[4] == '0' && rev < 'E')
ft_delprop_path(blob, WDOG1_PATH,
"fsl,ext-reset-output");
/* GW522x-B adds WDOG1_B external reset */
if (info->model[4] == '2' && rev < 'B')
ft_delprop_path(blob, WDOG1_PATH,
"fsl,ext-reset-output");
}
break;
case GW53xx:
/* GW53xx-E adds WDOG1_B external reset */
if (rev < 'E')
ft_delprop_path(blob, WDOG1_PATH,
"fsl,ext-reset-output");
break;
case GW54xx:
/*
* disable serial2 node for GW54xx for compatibility with older
* 3.10.x kernel that improperly had this node enabled in the DT
*/
i = fdt_path_offset(blob, UART1_PATH);
if (i)
fdt_del_node(blob, i);
}
/*
* disable wdog1/wdog2 nodes for GW51xx below revC to work around
* errata causing wdog timer to be unreliable.
*/
if (board_type == GW51xx && rev >= 'A' && rev < 'C') {
i = fdt_path_offset(blob,
"/soc/aips-bus@02000000/wdog@020bc000");
if (i)
fdt_status_disabled(blob, i);
}
/* GW54xx-E adds WDOG2_B external reset */
if (rev < 'E')
ft_delprop_path(blob, WDOG2_PATH,
"fsl,ext-reset-output");
break;
/* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
else if (board_type == GW52xx && info->model[4] == '2') {
u32 handle = 0;
u32 *range = NULL;
case GW551x:
/*
* isolate CSI0_DATA_EN for GW551x-A to work around errata
* causing non functional digital video in (it is not hooked up)
*/
if (rev == 'A') {
u32 *range = NULL;
int len;
const u32 *handle = NULL;
i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
if (i)
range = (u32 *)fdt_getprop(blob, i, "reset-gpio",
NULL);
if (range) {
i = fdt_path_offset(blob,
"/soc/aips-bus@02000000/gpio@020a4000");
i = fdt_node_offset_by_compatible(blob, -1,
"fsl,imx-tda1997x-video");
if (i)
handle = fdt_get_phandle(blob, i);
if (handle) {
range[0] = cpu_to_fdt32(handle);
range[1] = cpu_to_fdt32(23);
handle = fdt_getprop(blob, i, "pinctrl-0",
NULL);
if (handle)
i = fdt_node_offset_by_phandle(blob,
fdt32_to_cpu(*handle));
if (i)
range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
&len);
if (range) {
len /= sizeof(u32);
for (i = 0; i < len; i += 6) {
u32 mux_reg = fdt32_to_cpu(range[i+0]);
u32 conf_reg = fdt32_to_cpu(range[i+1]);
/* mux PAD_CSI0_DATA_EN to GPIO */
if (is_cpu_type(MXC_CPU_MX6Q) &&
mux_reg == 0x260 &&
conf_reg == 0x630)
range[i+3] = cpu_to_fdt32(0x5);
else if (!is_cpu_type(MXC_CPU_MX6Q) &&
mux_reg == 0x08c &&
conf_reg == 0x3a0)
range[i+3] = cpu_to_fdt32(0x5);
}
fdt_setprop_inplace(blob, i, "fsl,pins", range,
len);
}
/* set BT656 video format */
ft_sethdmiinfmt(blob, "yuv422bt656");
}
/* these have broken usd_vsel */
if (strstr((const char *)info->model, "SP318-B") ||
strstr((const char *)info->model, "SP331-B"))
gpio_cfg[board_type].usd_vsel = 0;
}
/*
* isolate CSI0_DATA_EN for GW551x below revB to work around
* errata causing non functional digital video in (it is not hooked up)
*/
else if (board_type == GW551x && rev == 'A') {
u32 *range = NULL;
int len;
const u32 *handle = NULL;
i = fdt_node_offset_by_compatible(blob, -1,
"fsl,imx-tda1997x-video");
if (i)
handle = fdt_getprop(blob, i, "pinctrl-0", NULL);
if (handle)
i = fdt_node_offset_by_phandle(blob,
fdt32_to_cpu(*handle));
if (i)
range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len);
if (range) {
len /= sizeof(u32);
for (i = 0; i < len; i += 6) {
u32 mux_reg = fdt32_to_cpu(range[i+0]);
u32 conf_reg = fdt32_to_cpu(range[i+1]);
/* mux PAD_CSI0_DATA_EN to GPIO */
if (is_cpu_type(MXC_CPU_MX6Q) &&
mux_reg == 0x260 && conf_reg == 0x630)
range[i+3] = cpu_to_fdt32(0x5);
else if (!is_cpu_type(MXC_CPU_MX6Q) &&
mux_reg == 0x08c && conf_reg == 0x3a0)
range[i+3] = cpu_to_fdt32(0x5);
}
fdt_setprop_inplace(blob, i, "fsl,pins", range, len);
}
/* set BT656 video format */
ft_sethdmiinfmt(blob, "yuv422bt656");
/* GW551x-C adds WDOG1_B external reset */
if (rev < 'C')
ft_delprop_path(blob, WDOG1_PATH,
"fsl,ext-reset-output");
break;
}
/* Configure DIO */
for (i = 0; i < gpio_cfg[board_type].num_gpios; i++) {
for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
char arg[10];
@ -976,6 +1298,11 @@ int ft_board_setup(void *blob, bd_t *bd)
"no-1-8-v");
}
#if defined(CONFIG_CMD_PCI)
if (!getenv("nopcifixup"))
ft_board_pci_fixup(blob, bd);
#endif
/*
* Peripheral Config:
* remove nodes by alias path if EEPROM config tells us the

View File

@ -60,7 +60,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
gd->ram_size = imx_ddr_size();
return 0;
}

View File

@ -415,3 +415,34 @@ int checkboard(void)
puts("Board: Inverse Path USB armory MkI\n");
return 0;
}
#ifndef CONFIG_CMDLINE
static char *ext2_argv[] = {
"ext2load",
"mmc",
"0:1",
USBARMORY_FIT_ADDR,
USBARMORY_FIT_PATH
};
static char *bootm_argv[] = {
"bootm",
USBARMORY_FIT_ADDR
};
int board_run_command(const char *cmdline)
{
printf("%s %s %s %s %s\n", ext2_argv[0], ext2_argv[1], ext2_argv[2],
ext2_argv[3], ext2_argv[4]);
if (do_ext2load(NULL, 0, 5, ext2_argv) != 0) {
udelay(5*1000*1000);
return 1;
}
printf("%s %s\n", bootm_argv[0], bootm_argv[1]);
do_bootm(NULL, 0, 2, bootm_argv);
return 1;
}
#endif

View File

@ -0,0 +1,12 @@
if TARGET_PCM058
config SYS_BOARD
default "pcm058"
config SYS_VENDOR
default "phytec"
config SYS_CONFIG_NAME
default "pcm058"
endif

View File

@ -0,0 +1,6 @@
PHYTEC PHYBOARD MIRA
M: Stefano Babic <sbabic@denx.de>
S: Maintained
F: board/phytec/pcm058/
F: include/configs/pcm058.h
F: configs/pcm058_defconfig

View File

@ -0,0 +1,9 @@
#
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := pcm058.o

View File

@ -0,0 +1,35 @@
Board information
-----------------
The SBC produced by Phytec has a SOM based on a i.MX6Q.
The SOM is sold in two versions, with eMMC or with NAND. Support
here is for the SOM with NAND.
The evaluation board "phyBoard-Mira" is thought to be used
together with the SOM.
More information on the board can be found on manufacturer's
website:
http://www.phytec.de/produkt/single-board-computer/phyboard-mira/
http://www.phytec.de/fileadmin/user_upload/images/content/1.Products/SOMs/phyCORE-i.MX6/L-808e_1.pdf
Building U-Boot
-------------------------------
$ make pcm058_defconfig
$ make
This generates the artifacts SPL and u-boot.img.
The SOM can boot from NAND or from SD-Card, having the SPI-NOR
as second option.
The dip switch "DIP-1" on the board let choose between
NAND and SD.
DIP-1 set to off: Boot first from NAND, then try SPI
DIP-1 set to on: Boot first from SD, then try SPI
The bootloader was tested with DIP-1 set to on. If a SD-card
is present, then the RBL tries to load SPL from the SD Card, if not,
RBL loads from SPI-NOR. The SPL tries then to load from the same
device where SPL was loaded (SD or SPI). Booting from NAND is
not supported.

View File

@ -0,0 +1,582 @@
/*
* Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Please note: there are two version of the board
* one with NAND and the other with eMMC.
* Both NAND and eMMC cannot be set because they share the
* same pins (SD4)
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/spi.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <mmc.h>
#include <i2c.h>
#include <fsl_esdhc.h>
#include <nand.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/sys_proto.h>
#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
#define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
#define USDHC1_CD_GPIO IMX_GPIO_NR(6, 31)
#define USER_LED IMX_GPIO_NR(1, 4)
#define IMX6Q_DRIVE_STRENGTH 0x30
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
void board_turn_off_led(void)
{
gpio_direction_output(USER_LED, 0);
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
/* NAND */
static iomux_v3_cfg_t const nfc_pads[] = {
MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
};
/* GPIOS */
static iomux_v3_cfg_t const gpios_pads[] = {
};
static struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
.gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
.gp = IMX_GPIO_NR(1, 5)
},
.sda = {
.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
.gp = IMX_GPIO_NR(1, 6)
}
};
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{.esdhc_base = USDHC1_BASE_ADDR,
.max_bus_width = 4},
#ifndef CONFIG_CMD_NAND
{USDHC4_BASE_ADDR},
#endif
};
static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
#ifndef CONFIG_CMD_NAND
static iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
#endif
int board_mmc_get_env_dev(int devno)
{
return devno - 1;
}
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = !gpio_get_value(USDHC1_CD_GPIO);
break;
case USDHC4_BASE_ADDR:
ret = 1; /* eMMC/uSDHC4 is always present */
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
#ifndef CONFIG_SPL_BUILD
int ret;
int i;
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
#ifndef CONFIG_CMD_NAND
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
break;
#endif
default:
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
i + 1, CONFIG_SYS_FSL_USDHC_NUM);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
#else
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned reg = readl(&psrc->sbmr1) >> 11;
/*
* Upon reading BOOT_CFG register the following map is done:
* Bit 11 and 12 of BOOT_CFG register can determine the current
* mmc port
* 0x1 SD1
* 0x2 SD2
* 0x3 SD4
*/
switch (reg & 0x3) {
case 0x0:
imx_iomux_v3_setup_multiple_pads(
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
usdhc_cfg[0].max_bus_width = 4;
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
break;
}
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
#endif
}
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
mdelay(10);
gpio_set_value(ENET_PHY_RESET_GPIO, 1);
mdelay(30);
}
static void setup_spi(void)
{
gpio_request(IMX_GPIO_NR(3, 19), "spi_cs0");
gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
enable_spi_clk(true, 0);
}
#ifdef CONFIG_CMD_NAND
static void setup_gpmi_nand(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* config gpmi nand iomux */
imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
/* gate ENFC_CLK_ROOT clock first,before clk source switch */
clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
/* config gpmi and bch clock to 100 MHz */
clrsetbits_le32(&mxc_ccm->cs2cdr,
MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
/* enable ENFC_CLK_ROOT clock */
setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
/* enable gpmi and bch clock gating */
setbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
/* enable apbh clock gating */
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
}
#endif
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
if (bus != 0 || (cs != 0))
return -EINVAL;
return IMX_GPIO_NR(3, 19);
}
int board_eth_init(bd_t *bis)
{
setup_iomux_enet();
return cpu_eth_init(bis);
}
int board_early_init_f(void)
{
setup_iomux_uart();
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_SYS_I2C_MXC
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
#endif
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
#ifdef CONFIG_CMD_NAND
setup_gpmi_nand();
#endif
return 0;
}
#ifdef CONFIG_CMD_BMODE
/*
* BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
* see Table 8-11 and Table 5-9
* BOOT_CFG1[7] = 1 (boot from NAND)
* BOOT_CFG1[5] = 0 - raw NAND
* BOOT_CFG1[4] = 0 - default pad settings
* BOOT_CFG1[3:2] = 00 - devices = 1
* BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
* BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
* BOOT_CFG2[2:1] = 01 - Pages In Block = 64
* BOOT_CFG2[0] = 0 - Reset time 12ms
*/
static const struct boot_mode board_boot_modes[] = {
/* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
{"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
{"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
{NULL, 0},
};
#endif
int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
return 0;
}
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
#include <libfdt.h>
static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_sdclk_0 = 0x00000030,
.dram_sdclk_1 = 0x00000030,
.dram_cas = 0x00000030,
.dram_ras = 0x00000030,
.dram_reset = 0x00000030,
.dram_sdcke0 = 0x00000030,
.dram_sdcke1 = 0x00000030,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = 0x00000030,
.dram_sdodt1 = 0x00000030,
.dram_sdqs0 = 0x00000030,
.dram_sdqs1 = 0x00000030,
.dram_sdqs2 = 0x00000030,
.dram_sdqs3 = 0x00000030,
.dram_sdqs4 = 0x00000030,
.dram_sdqs5 = 0x00000030,
.dram_sdqs6 = 0x00000030,
.dram_sdqs7 = 0x00000030,
.dram_dqm0 = 0x00000030,
.dram_dqm1 = 0x00000030,
.dram_dqm2 = 0x00000030,
.dram_dqm3 = 0x00000030,
.dram_dqm4 = 0x00000030,
.dram_dqm5 = 0x00000030,
.dram_dqm6 = 0x00000030,
.dram_dqm7 = 0x00000030,
};
static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
.grp_ddr_type = 0x000C0000,
.grp_ddrmode_ctl = 0x00020000,
.grp_ddrpke = 0x00000000,
.grp_addds = IMX6Q_DRIVE_STRENGTH,
.grp_ctlds = IMX6Q_DRIVE_STRENGTH,
.grp_ddrmode = 0x00020000,
.grp_b0ds = IMX6Q_DRIVE_STRENGTH,
.grp_b1ds = IMX6Q_DRIVE_STRENGTH,
.grp_b2ds = IMX6Q_DRIVE_STRENGTH,
.grp_b3ds = IMX6Q_DRIVE_STRENGTH,
.grp_b4ds = IMX6Q_DRIVE_STRENGTH,
.grp_b5ds = IMX6Q_DRIVE_STRENGTH,
.grp_b6ds = IMX6Q_DRIVE_STRENGTH,
.grp_b7ds = IMX6Q_DRIVE_STRENGTH,
};
static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p0_mpwldectrl0 = 0x00140014,
.p0_mpwldectrl1 = 0x000A0015,
.p1_mpwldectrl0 = 0x000A001E,
.p1_mpwldectrl1 = 0x000A0015,
.p0_mpdgctrl0 = 0x43080314,
.p0_mpdgctrl1 = 0x02680300,
.p1_mpdgctrl0 = 0x430C0318,
.p1_mpdgctrl1 = 0x03000254,
.p0_mprddlctl = 0x3A323234,
.p1_mprddlctl = 0x3E3C3242,
.p0_mpwrdlctl = 0x2A2E3632,
.p1_mpwrdlctl = 0x3C323E34,
};
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 1600,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
.SRT = 1,
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0x00C03F3F, &ccm->CCGR0);
writel(0x0030FC03, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
writel(0x00FFF300, &ccm->CCGR4);
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
static void spl_dram_init(void)
{
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = 2,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
/* single chip select */
.ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
};
mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = spl_boot_device();
printf("Boot device %x\n", spl_boot_list[0]);
switch (spl_boot_list[0]) {
case BOOT_DEVICE_SPI:
spl_boot_list[1] = BOOT_DEVICE_UART;
break;
case BOOT_DEVICE_MMC1:
spl_boot_list[1] = BOOT_DEVICE_SPI;
spl_boot_list[2] = BOOT_DEVICE_UART;
break;
default:
printf("Boot device %x\n", spl_boot_list[0]);
}
}
void board_init_f(ulong dummy)
{
#ifdef CONFIG_CMD_NAND
/* Enable NAND */
setup_gpmi_nand();
#endif
/* setup clock gating */
ccgr_init();
/* setup AIPS and disable watchdog */
arch_cpu_init();
/* setup AXI */
gpr_init();
board_early_init_f();
/* setup GP timer */
timer_init();
setup_spi();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
#endif

View File

@ -367,14 +367,6 @@ int checkboard(void)
return 0;
}
static bool is_mx6q(void)
{
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
return true;
else
return false;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
@ -383,7 +375,7 @@ int board_late_init(void)
else
setenv("board_name", "CUBOXI");
if (is_mx6q())
if (is_mx6dq())
setenv("board_rev", "MX6Q");
else
setenv("board_rev", "MX6DL");
@ -615,7 +607,7 @@ static void spl_dram_init(int width)
.ddr_type = DDR_TYPE_DDR3,
};
if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q))
if (is_mx6dq())
mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
else
mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);

View File

@ -0,0 +1,57 @@
How to Update U-Boot on Pico-imx6ul board
-----------------------------------------
Required software on the host PC:
- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader
- dfu-util: http://dfu-util.sourceforge.net/releases/
Build U-Boot for Pico:
$ make mrproper
$ make pico-imx6ul_defconfig
$ make
This will generate the U-Boot binary called u-boot.imx.
Put pico board in USB download mode (refer to the document
http://www.wandboard.org/images/hobbit/hobbitboard-imx6ul-reva1.pdf page 15)
Connect a USB to serial adapter between the host PC and pico
Connect a USB cable between the OTG pico port and the host PC
Open a terminal program such as minicom
Copy u-boot.imx to the imx_usb_loader folder.
Load u-boot.imx via USB:
$ sudo ./imx_usb u-boot.imx
Then U-Boot should start and its messages will appear in the console program.
Use the default environment variables:
=> env default -f -a
=> saveenv
Run the DFU command:
=> dfu 0 mmc 0
Transfer u-boot.imx that will be flashed into the eMMC:
$ sudo dfu-util -D u-boot.imx -a boot
Then on the U-Boot prompt the following message should be seen after a
successful upgrade:
#DOWNLOAD ... OK
Ctrl+C to exit ...
Remove power from the pico board.
Put pico board into normal boot mode
Power up the board and the new updated U-Boot should boot from eMMC.

View File

@ -14,11 +14,18 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <miiphy.h>
#include <netdev.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include <linux/sizes.h>
#include <usb.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include "../../freescale/common/pfuze.h"
DECLARE_GLOBAL_DATA_PTR;
@ -30,10 +37,113 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE)
#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define RMII_PHY_RESET IMX_GPIO_NR(1, 28)
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C2 for PMIC */
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
.gp = IMX_GPIO_NR(1, 2),
},
.sda = {
.i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3),
},
};
#endif
static iomux_v3_cfg_t const fec_pads[] = {
MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
int board_eth_init(bd_t *bis)
{
setup_iomux_fec();
gpio_direction_output(RMII_PHY_RESET, 0);
/*
* According to KSZ8081MNX-RNB manual:
* For warm reset, the reset (RST#) pin should be asserted low for a
* minimum of 500μs. The strap-in pin values are read and updated
* at the de-assertion of reset.
*/
udelay(500);
gpio_direction_output(RMII_PHY_RESET, 1);
/*
* According to KSZ8081MNX-RNB manual:
* After the de-assertion of reset, wait a minimum of 100μs before
* starting programming on the MIIM (MDC/MDIO) interface.
*/
udelay(100);
return fecmxc_initialize(bis);
}
static int setup_fec(void)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
ret = enable_fec_anatop_clock(1, ENET_50MHZ);
if (ret)
return ret;
enable_enet_clk(1);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@ -59,6 +169,9 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
#define USB_OTHERREGS_OFFSET 0x800
#define UCTRL_PWR_POL (1 << 9)
static iomux_v3_cfg_t const usb_otg_pad[] = {
MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
};
@ -96,9 +209,67 @@ int board_early_init_f(void)
return 0;
}
#ifdef CONFIG_POWER
#define I2C_PMIC 0
static struct pmic *pfuze;
int power_init_board(void)
{
int ret;
unsigned int reg, rev_id;
ret = power_pfuze3000_init(I2C_PMIC);
if (ret)
return ret;
pfuze = pmic_get("PFUZE3000");
ret = pmic_probe(pfuze);
if (ret)
return ret;
pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
/* disable Low Power Mode during standby mode */
pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg);
reg |= 0x1;
pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
/* SW1B step ramp up time from 2us to 4us/25mV */
pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, 0x40);
/* SW1B mode to APS/PFM */
pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, 0xc);
/* SW1B standby voltage set to 0.975V */
pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, 0xb);
return 0;
}
#endif
int board_usb_phy_mode(int port)
{
return USB_INIT_DEVICE;
if (port == 1)
return USB_INIT_HOST;
else
return USB_INIT_DEVICE;
}
int board_ehci_hcd_init(int port)
{
u32 *usbnc_usb_ctrl;
if (port > 1)
return -EINVAL;
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
port * 4);
/* Set Power polarity */
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
return 0;
}
int board_init(void)
@ -106,6 +277,11 @@ int board_init(void)
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_SYS_I2C_MXC
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#endif
setup_fec();
setup_usb();
return 0;

View File

@ -0,0 +1,20 @@
if TARGET_COLIBRI_IMX7
config SYS_BOARD
default "colibri_imx7"
config SYS_VENDOR
default "toradex"
config SYS_CONFIG_NAME
default "colibri_imx7"
config COLIBRI_IMX7_EXT_PHYCLK
bool "External oscillator for Ethernet PHY clock provided"
help
Select this if your module provides a external Ethernet PHY
clock source.
default y
endif

View File

@ -0,0 +1,6 @@
Colibri iMX7
M: Stefan Agner <stefan.agner@toradex.com>
S: Maintained
F: board/toradex/colibri_imx7/
F: include/configs/colibri_imx7.h
F: configs/colibri_imx7_defconfig

View File

@ -0,0 +1,6 @@
# Copyright (C) 2016 Toradex AG
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := colibri_imx7.o

View File

@ -0,0 +1,420 @@
/*
* Copyright (C) 2016 Toradex AG
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <dm.h>
#include <dm/platform_data/serial_mxc.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include <linux/sizes.h>
#include <mmc.h>
#include <miiphy.h>
#include <netdev.h>
#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
PAD_CTL_DSE_3P3V_49OHM)
#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX7D_PAD_GPIO1_IO04__I2C1_SCL | PC,
.gpio_mode = MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | PC,
.gp = IMX_GPIO_NR(1, 4),
},
.sda = {
.i2c_mode = MX7D_PAD_GPIO1_IO05__I2C1_SDA | PC,
.gpio_mode = MX7D_PAD_GPIO1_IO05__GPIO1_IO5 | PC,
.gp = IMX_GPIO_NR(1, 5),
},
};
/* I2C4 for Colibri I2C */
static struct i2c_pads_info i2c_pad_info4 = {
.scl = {
.i2c_mode = MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL | PC,
.gpio_mode = MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 | PC,
.gp = IMX_GPIO_NR(7, 8),
},
.sda = {
.i2c_mode = MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA | PC,
.gpio_mode = MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 | PC,
.gp = IMX_GPIO_NR(7, 9),
},
};
#endif
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc1_pads[] = {
MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#ifdef CONFIG_NAND_MXS
static iomux_v3_cfg_t const gpmi_pads[] = {
MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
};
static void setup_gpmi_nand(void)
{
imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
/* NAND_USDHC_BUS_CLK is set in rom */
set_clk_nand();
}
#endif
static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
#ifdef CONFIG_VIDEO_MXS
static iomux_v3_cfg_t const lcd_pads[] = {
MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
};
static iomux_v3_cfg_t const backlight_pads[] = {
/* Backlight On */
MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* Backlight PWM<A> (multiplexed pin) */
MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#define GPIO_BL_ON IMX_GPIO_NR(5, 1)
#define GPIO_PWM_A IMX_GPIO_NR(1, 8)
static int setup_lcd(void)
{
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
/* Set BL_ON */
gpio_request(GPIO_BL_ON, "BL_ON");
gpio_direction_output(GPIO_BL_ON, 1);
/* Set PWM<A> to full brightness (assuming inversed polarity) */
gpio_request(GPIO_PWM_A, "PWM<A>");
gpio_direction_output(GPIO_PWM_A, 0);
return 0;
}
#endif
#ifdef CONFIG_FEC_MXC
static iomux_v3_cfg_t const fec1_pads[] = {
#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
#else
MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
#endif
MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
}
#endif
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
#ifdef CONFIG_FSL_ESDHC
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0)
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{USDHC1_BASE_ADDR, 0, 4},
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = !gpio_get_value(USDHC1_CD_GPIO);
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
int i, ret;
/* USDHC1 is mmc0 */
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
#endif
#ifdef CONFIG_FEC_MXC
int board_eth_init(bd_t *bis)
{
int ret;
setup_iomux_fec();
ret = fecmxc_initialize_multi(bis, 0,
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
if (ret)
printf("FEC1 MXC: %s:failed\n", __func__);
return ret;
}
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
/*
* Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
* and output it on the pin
*/
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
#else
/* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
#endif
return set_clk_enet(ENET_50MHz);
}
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
#ifdef CONFIG_SYS_I2C_MXC
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
#endif
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
#ifdef CONFIG_VIDEO_MXS
setup_lcd();
#endif
return 0;
}
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
{"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)},
{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
{NULL, 0},
};
#endif
int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
return 0;
}
int checkboard(void)
{
printf("Model: Toradex Colibri iMX7%c\n",
is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
return 0;
}
#ifdef CONFIG_USB_EHCI_MX7
static iomux_v3_cfg_t const usb_otg2_pads[] = {
MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
};
int board_ehci_hcd_init(int port)
{
switch (port) {
case 0:
break;
case 1:
if (is_cpu_type(MXC_CPU_MX7S))
return -ENODEV;
imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
ARRAY_SIZE(usb_otg2_pads));
break;
default:
return -EINVAL;
}
return 0;
}
#endif
static struct mxc_serial_platdata mxc_serial_plat = {
.reg = (struct mxc_uart *)UART1_IPS_BASE_ADDR,
.use_dte = true,
};
U_BOOT_DEVICE(mxc_serial) = {
.name = "serial_mxc",
.platdata = &mxc_serial_plat,
};

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@ -0,0 +1,150 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* 2015 Toradex AG
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : sd
*/
BOOT_FROM sd
/*
* Secure boot support
*/
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* IOMUXC_GPR_GPR1 */
DATA 4 0x30340004 0x4F400005
/* DDR3L */
/* assuming MEMC_FREQ_RATIO = 2 */
/* SRC_DDRC_RCR */
DATA 4 0x30391000 0x00000002
/* DDRC_MSTR */
DATA 4 0x307a0000 0x01040001
/* DDRC_DFIUPD0 */
DATA 4 0x307a01a0 0x80400003
/* DDRC_DFIUPD1 */
DATA 4 0x307a01a4 0x00100020
/* DDRC_DFIUPD2 */
DATA 4 0x307a01a8 0x80100004
/* DDRC_RFSHTMG */
DATA 4 0x307a0064 0x00400045
/* DDRC_MP_PCTRL_0 */
DATA 4 0x307a0490 0x00000001
/* DDRC_INIT0 */
DATA 4 0x307a00d0 0x00020083
/* DDRC_INIT1 */
DATA 4 0x307a00d4 0x00690000
/* DDRC_INIT3 MR0/MR1 */
DATA 4 0x307a00dc 0x09300004
/* DDRC_INIT4 MR2/MR3 */
DATA 4 0x307a00e0 0x04480000
/* DDRC_INIT5 */
DATA 4 0x307a00e4 0x00100004
/* DDRC_RANKCTL */
DATA 4 0x307a00f4 0x0000033f
/* DDRC_DRAMTMG0 */
DATA 4 0x307a0100 0x090b090a
/* DDRC_DRAMTMG1 */
DATA 4 0x307a0104 0x000d020d
/* DDRC_DRAMTMG2 */
DATA 4 0x307a0108 0x03040307
/* DDRC_DRAMTMG3 */
DATA 4 0x307a010c 0x00002006
/* DDRC_DRAMTMG4 */
DATA 4 0x307a0110 0x04020205
/* DDRC_DRAMTMG5 */
DATA 4 0x307a0114 0x03030202
/* DDRC_DRAMTMG8 */
DATA 4 0x307a0120 0x00000803
/* DDRC_ZQCTL0 */
DATA 4 0x307a0180 0x00800020
/* DDRC_ZQCTL1 */
DATA 4 0x307a0184 0x02001000
/* DDRC_DFITMG0 */
DATA 4 0x307a0190 0x02098204
/* DDRC_DFITMG1 */
DATA 4 0x307a0194 0x00030303
/* DDRC_ADDRMAP0 */
DATA 4 0x307a0200 0x0000001f
/* DDRC_ADDRMAP1 */
DATA 4 0x307a0204 0x00080808
/* DDRC_ADDRMAP5 */
DATA 4 0x307a0214 0x07070707
/* DDRC_ADDRMAP6 */
DATA 4 0x307a0218 0x07070707
/* DDRC_ODTCFG */
DATA 4 0x307a0240 0x06000601
/* DDRC_ODTMAP */
DATA 4 0x307a0244 0x00000011
/* SRC_DDRC_RCR */
DATA 4 0x30391000 0x00000000
/* DDR_PHY_PHY_CON0 */
DATA 4 0x30790000 0x17420f40
/* DDR_PHY_PHY_CON1 */
DATA 4 0x30790004 0x10210100
/* DDR_PHY_PHY_CON4 */
DATA 4 0x30790010 0x00060807
/* DDR_PHY_MDLL_CON0 */
DATA 4 0x307900b0 0x1010007e
/* DDR_PHY_DRVDS_CON0 */
DATA 4 0x3079009c 0x00000d6e
/* DDR_PHY_OFFSET_RD_CON0 */
DATA 4 0x30790020 0x08080808
/* DDR_PHY_OFFSET_WR_CON0 */
DATA 4 0x30790030 0x08080808
/* DDR_PHY_CMD_SDLL_CON0 */
DATA 4 0x30790050 0x01000010
DATA 4 0x30790050 0x00000010
/* DDR_PHY_ZQ_CON0 */
DATA 4 0x307900c0 0x0e407304
DATA 4 0x307900c0 0x0e447304
DATA 4 0x307900c0 0x0e447306
/* DDR_PHY_ZQ_CON1 */
CHECK_BITS_SET 4 0x307900c4 0x1
/* DDR_PHY_ZQ_CON0 */
DATA 4 0x307900c0 0x0e447304
DATA 4 0x307900c0 0x0e407304
/* CCM_CCGRn */
DATA 4 0x30384130 0x00000000
/* IOMUXC_GPR_GPR8 */
DATA 4 0x30340020 0x00000178
/* CCM_CCGRn */
DATA 4 0x30384130 0x00000002
/* DDR_PHY_LP_CON0 */
DATA 4 0x30790018 0x0000000f
/* DDRC_STAT */
CHECK_BITS_SET 4 0x307a0004 0x1

View File

@ -19,6 +19,7 @@
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/video.h>
#include <asm/imx-common/sata.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <common.h>
@ -345,6 +346,12 @@ int board_early_init_f(void)
#if defined(CONFIG_VIDEO_IPUV3)
setup_display();
#endif
#ifdef CONFIG_CMD_SATA
/* Only mx6q wandboard has SATA */
if (is_cpu_type(MXC_CPU_MX6Q))
setup_sata();
#endif
return 0;
}
@ -384,7 +391,7 @@ int board_late_init(void)
#endif
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
if (is_mx6dq())
setenv("board_rev", "MX6Q");
else
setenv("board_rev", "MX6DL");
@ -403,7 +410,7 @@ int board_init(void)
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
if (is_mx6dq())
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
else
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);

View File

@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
gd->ram_size = imx_ddr_size();
return 0;
}

View File

@ -0,0 +1,40 @@
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
CONFIG_TARGET_COLIBRI_IMX7=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D"
CONFIG_BOOTDELAY=1
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Colibri iMX7 # "
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_ASKENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Toradex"
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x4020
CONFIG_OF_LIBFDT=y

View File

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
CONFIG_TARGET_MX7DSABRESD=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
@ -29,6 +30,8 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y

View File

@ -0,0 +1,41 @@
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
CONFIG_TARGET_MX7DSABRESD=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y

34
configs/pcm058_defconfig Normal file
View File

@ -0,0 +1,34 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_PCM058=y
CONFIG_SPL=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_HUSH_PARSER=y
CONFIG_MTD=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=n
CONFIG_CMD_DFU=n
CONFIG_CMD_USB_MASS_STORAGE=n
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_FIT=y
CONFIG_DM=y
CONFIG_DM_THERMAL=y
CONFIG_OF_LIBFDT=y

View File

@ -10,6 +10,7 @@ CONFIG_CMD_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
@ -21,4 +22,11 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y

View File

@ -1,10 +1,10 @@
CONFIG_ARM=y
CONFIG_ARCH_MX7=y
CONFIG_TARGET_WARP7=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg"
CONFIG_BOOTDELAY=1
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
CONFIG_CMD_BOOTZ=y
@ -23,4 +23,13 @@ CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_OF_LIBFDT=y

22
configs/zc5202_defconfig Normal file
View File

@ -0,0 +1,22 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_ZC5202=y
CONFIG_SPL=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_LIBFDT=y

22
configs/zc5601_defconfig Normal file
View File

@ -0,0 +1,22 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_ZC5601=y
CONFIG_SPL=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_OF_LIBFDT=y

View File

@ -27,6 +27,11 @@ CONFIG_FEC_MXC_PHYADDR
Optional, selects the exact phy address that should be connected
and function fecmxc_initialize will try to initialize it.
CONFIG_FEC_FIXED_SPEED
Optional, selects a fixed speed on the MAC interface without asking some
phy. This is usefull if there is a direct MAC <-> MAC connection, for
example if the CPU is connected directly via the RGMII interface to a
ethernet-switch.
Reading the ethaddr from the SoC eFuses:
if CONFIG_FEC_MXC is defined and the U-Boot environment does not contain the

View File

@ -233,6 +233,7 @@ static int miiphy_restart_aneg(struct eth_device *dev)
return ret;
}
#ifndef CONFIG_FEC_FIXED_SPEED
static int miiphy_wait_aneg(struct eth_device *dev)
{
uint32_t start;
@ -260,6 +261,7 @@ static int miiphy_wait_aneg(struct eth_device *dev)
return 0;
}
#endif /* CONFIG_FEC_FIXED_SPEED */
#endif
static int fec_rx_task_enable(struct fec_priv *fec)
@ -502,6 +504,8 @@ static int fec_open(struct eth_device *edev)
}
speed = fec->phydev->speed;
}
#elif CONFIG_FEC_FIXED_SPEED
speed = CONFIG_FEC_FIXED_SPEED;
#else
miiphy_wait_aneg(edev);
speed = miiphy_speed(edev->name, fec->phy_id);

View File

@ -458,6 +458,10 @@ void pci_init(void)
{
hose_head = NULL;
/* allow env to disable pci init/enum */
if (getenv("pcidisable") != NULL)
return;
/* now call board specific pci_init()... */
pci_init_board();
}

View File

@ -595,7 +595,7 @@ static int imx_pcie_link_up(void)
while (!imx6_pcie_link_up()) {
udelay(10);
count++;
if (count >= 2000) {
if (count >= 4000) {
#ifdef CONFIG_PCI_SCAN_SHOW
puts("PCI: pcie phy link never came up\n");
#endif

View File

@ -76,6 +76,7 @@
#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
#define UFCR_DCEDTE (1<<6) /* DTE mode select */
#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
#define USR1_RTSS (1<<14) /* RTS pin status */
@ -269,8 +270,13 @@ int mxc_serial_setbrg(struct udevice *dev, int baudrate)
struct mxc_serial_platdata *plat = dev->platdata;
struct mxc_uart *const uart = plat->reg;
u32 clk = imx_get_uartclk();
u32 tmp;
tmp = 4 << UFCR_RFDIV_SHF;
if (plat->use_dte)
tmp |= UFCR_DCEDTE;
writel(tmp, &uart->fcr);
writel(4 << 7, &uart->fcr); /* divide input clock by 2 */
writel(0xf, &uart->bir);
writel(clk / (2 * baudrate), &uart->bmr);

View File

@ -74,6 +74,22 @@ config USB_EHCI_MX6
---help---
Enables support for the on-chip EHCI controller on i.MX6 SoCs.
config USB_EHCI_MX7
bool "Support for i.MX7 on-chip EHCI USB controller"
depends on ARCH_MX7
default y
---help---
Enables support for the on-chip EHCI controller on i.MX7 SoCs.
if USB_EHCI_MX7
config MXC_USB_OTG_HACTIVE
bool "USB Power pin high active"
---help---
Set the USB Power pin polarity to be high active (PWR_POL)
endif
config USB_EHCI_MSM
bool "Support for Qualcomm on-chip EHCI USB controller"
depends on DM_USB

View File

@ -49,7 +49,7 @@
#define USBNC_OFFSET 0x200
#define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
#define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
#define UCTRL_PM (1 << 9) /* OTG Power Mask */
#define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
@ -207,12 +207,20 @@ static void usb_power_config(int index)
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
(0x10000 * index) + USBNC_OFFSET);
void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
/*
* Clear the ACAENB to enable usb_otg_id detection,
* otherwise it is the ACA detection enabled.
*/
clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
/* Set power polarity to high active */
#ifdef CONFIG_MXC_USB_OTG_HACTIVE
setbits_le32(ctrl, UCTRL_PWR_POL);
#else
clrbits_le32(ctrl, UCTRL_PWR_POL);
#endif
}
int usb_phy_mode(int port)
@ -250,11 +258,7 @@ static void usb_oc_config(int index)
setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
#endif
#if defined(CONFIG_MX6)
setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
#elif defined(CONFIG_MX7)
setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM);
#endif
}
/**

View File

@ -39,7 +39,7 @@ void hw_watchdog_init(void)
}
#endif
void reset_cpu(ulong addr)
void __attribute__((weak)) reset_cpu(ulong addr)
{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;

View File

@ -17,7 +17,6 @@
#define CONFIG_MACH_TYPE 4501
#define CONFIG_MMCROOT "/dev/mmcblk0p1"
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M)

View File

@ -251,7 +251,6 @@
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR

View File

@ -18,6 +18,7 @@
#define CONFIG_MACH_TYPE 4273
/* CMD */
#define CONFIG_CMD_MTDPARTS
/* MMC */
#define CONFIG_SYS_FSL_USDHC_NUM 3
@ -53,6 +54,20 @@
#define CONFIG_SF_DEFAULT_SPEED 25000000
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
/* MTD support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_FDT_FIXUP_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SPI_FLASH_MTD
#endif
#define MTDIDS_DEFAULT "nor0=spi0.0"
#define MTDPARTS_DEFAULT "mtdparts=spi0.0:" \
"768k(uboot)," \
"256k(uboot-environment)," \
"-(reserved)"
/* Environment */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
@ -69,6 +84,8 @@
"stderr=serial,vga\0" \
"panel=HDMI\0" \
"autoload=no\0" \
"uImage=uImage-cm-fx6\0" \
"zImage=zImage-cm-fx6\0" \
"kernel=uImage-cm-fx6\0" \
"script=boot.scr\0" \
"dtb=cm-fx6.dtb\0" \
@ -81,10 +98,12 @@
"video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
"doboot=bootm ${loadaddr}\0" \
"doloadfdt=false\0" \
"setboottypez=setenv kernel zImage-cm-fx6;" \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"setboottypez=setenv kernel ${zImage};" \
"setenv doboot bootz ${loadaddr} - ${fdtaddr};" \
"setenv doloadfdt true;\0" \
"setboottypem=setenv kernel uImage-cm-fx6;" \
"setboottypem=setenv kernel ${uImage};" \
"setenv doboot bootm ${loadaddr};" \
"setenv doloadfdt false;\0"\
"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
@ -92,13 +111,13 @@
"nandroot=/dev/mtdblock4 rw\0" \
"nandrootfstype=ubifs\0" \
"mmcargs=setenv bootargs console=${console} root=${mmcroot} " \
"${video}\0" \
"${video} ${extrabootargs}\0" \
"sataargs=setenv bootargs console=${console} root=${sataroot} " \
"${video}\0" \
"${video} ${extrabootargs}\0" \
"nandargs=setenv bootargs console=${console} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype} " \
"${video}\0" \
"${video} ${extrabootargs}\0" \
"nandboot=if run nandloadkernel; then " \
"run nandloadfdt;" \
"run setboottypem;" \
@ -155,7 +174,7 @@
"run setupnandboot;" \
"run nandboot;"
#define CONFIG_PREBOOT "usb start"
#define CONFIG_PREBOOT "usb start;sf probe"
/* SPI */
#define CONFIG_SPI

View File

@ -0,0 +1,247 @@
/*
* Copyright 2016 Toradex AG
*
* Configuration settings for the Colibri iMX7 module.
*
* based on mx7dsabresd.h:
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __COLIBRI_IMX7_CONFIG_H
#define __COLIBRI_IMX7_CONFIG_H
#include "mx7_common.h"
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_USE_ARCH_MEMSET
/*#define CONFIG_DBG_MONITOR*/
#define PHYS_SDRAM_SIZE SZ_512M
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_DISPLAY_BOARDINFO_LATE
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
/* Uncomment to enable secure boot support */
/* #define CONFIG_SECURE_BOOT */
#define CONFIG_CSF_SIZE 0x4000
#define CONFIG_CMD_BMODE
/* Network */
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_TFTP_TSIZE
#define CONFIG_IP_DEFRAG
#define CONFIG_TFTP_BLOCKSIZE 16384
/* ENET1 */
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 1
#undef CONFIG_BOOTM_PLAN9
#undef CONFIG_BOOTM_RTEMS
/* I2C configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
#define MEM_LAYOUT_ENV_SETTINGS \
"fdt_addr_r=0x82000000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x81000000\0" \
"ramdisk_addr_r=0x82100000\0"
#define SD_BOOTCMD \
"sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \
"sdboot=run setup; setenv bootargs ${defargs} ${sdargs} " \
"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
"run m4boot && " \
"load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \
"load mmc 0:1 ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define NFS_BOOTCMD \
"nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
"nfsboot=run setup; " \
"setenv bootargs ${defargs} ${nfsargs} " \
"${setupargs} ${vidargs}; echo Booting from NFS...;" \
"dhcp ${kernel_addr_r} && " \
"tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define UBI_BOOTCMD \
"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
"ubi.fm_autoconvert=1\0" \
"ubiboot=run setup; " \
"setenv bootargs ${defargs} ${ubiargs} " \
"${setupargs} ${vidargs}; echo Booting from NAND...; " \
"ubi part ubi && run m4boot && " \
"ubi read ${kernel_addr_r} kernel && " \
"ubi read ${fdt_addr_r} dtb && " \
"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
#define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot"
#define CONFIG_EXTRA_ENV_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
SD_BOOTCMD \
UBI_BOOTCMD \
"console=ttymxc0\0" \
"defargs=\0" \
"fdt_board=eval-v3\0" \
"fdt_fixup=;\0" \
"m4boot=;\0" \
"ip_dyn=yes\0" \
"kernel_file=zImage\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
"${board}/flash_eth.img && source ${loadaddr}\0" \
"setsdupdate=mmc rescan && setenv interface mmc && " \
"fatload ${interface} 0:1 ${loadaddr} " \
"${board}/flash_blk.img && source ${loadaddr}\0" \
"setup=setenv setupargs " \
"console=tty1 console=${console}" \
",${baudrate}n8 ${memargs} consoleblank=0 ${mtdparts}\0" \
"setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
"setusbupdate=usb start && setenv interface usb && " \
"fatload ${interface} 0:1 ${loadaddr} " \
"${board}/flash_blk.img && source ${loadaddr}\0" \
"splashpos=m,m\0" \
"videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x0c000000)
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
#define CONFIG_STACKSIZE SZ_128K
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_NAND
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
#elif defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_ENV_OFFSET (4 * 1024 * 1024)
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#endif
#define CONFIG_NAND_MXS
#define CONFIG_CMD_NAND_TRIMFFS
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
#define CONFIG_CMD_NAND_TORTURE
/* UBI stuff */
#define CONFIG_RBTREE
#define CONFIG_LZO
#define CONFIG_CMD_UBI
#define CONFIG_MTD_UBI_FASTMAP
#define CONFIG_CMD_UBIFS /* increases size by almost 60 KB */
/* Dynamic MTD partition support */
#define CONFIG_CMD_MTDPARTS /* Enable 'mtdparts' command line support */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define MTDIDS_DEFAULT "nand0=gpmi-nand"
#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:" \
"512k(mx7-bcb)," \
"3584k(u-boot)ro," \
"512k(u-boot-env)," \
"-(ubi)"
/* DMA stuff, needed for GPMI/MXS NAND support */
#define CONFIG_APBH_DMA
#define CONFIG_APBH_DMA_BURST
#define CONFIG_APBH_DMA_BURST8
/* USB Configs */
#define CONFIG_USB_STORAGE
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_IMX_THERMAL
#define CONFIG_USBD_HS
#define CONFIG_USB_FUNCTION_MASS_STORAGE
/* USB Device Firmware Update support */
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_BMP_LOGO
#endif
#endif

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@ -0,0 +1,139 @@
/*
* Copyright (C) Stefano Babic <sbabic@denx.de>
*
* Configuration settings for the E+L i.MX6Q DO82 board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __EL6Q_COMMON_CONFIG_H
#define __EL6Q_COMMON_CONFIG_H
#define CONFIG_BOARD_NAME EL6Q
#include <config_distro_defaults.h>
#include "mx6_common.h"
#define CONFIG_IMX_THERMAL
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_UART
#ifdef CONFIG_SPL
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#define CONFIG_SPL_SPI_LOAD
#include "imx6_spl.h"
#endif
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
/* I2C config */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
/* Commands */
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 3
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONFIG_BAUDRATE 115200
/* Command definition */
#define CONFIG_CMD_BMODE
#define CONFIG_CMD_BOOTZ
#undef CONFIG_CMD_IMLS
#define CONFIG_BOARD_NAME EL6Q
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"board="__stringify(CONFIG_BOARD_NAME)"\0" \
"cma_size="__stringify(EL6Q_CMA_SIZE)"\0" \
"chp_size="__stringify(EL6Q_COHERENT_POOL_SIZE)"\0" \
"console=" CONFIG_CONSOLE_DEV "\0" \
"fdtfile=undefined\0" \
"fdt_high=0xffffffff\0" \
"fdt_addr_r=0x18000000\0" \
"fdt_addr=0x18000000\0" \
"findfdt=setenv fdtfile " CONFIG_DEFAULT_FDT_FILE "\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
BOOTENV
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
func(PXE, PXE, na) \
func(DHCP, dhcp, na)
#define CONFIG_BOOTCOMMAND \
"run findfdt; " \
"run distro_bootcmd"
#include <config_distro_bootcmd.h>
#define CONFIG_ARP_TIMEOUT 200UL
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10800000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
#define CONFIG_STACKSIZE (128 * 1024)
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET 0x0
#endif
#endif /* __EL6Q_COMMON_CONFIG_H */

View File

@ -32,8 +32,6 @@
#define CONFIG_MXC_UART_BASE UART3_BASE
#define CONFIG_CONSOLE_DEV "ttymxc2"
#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
#define CONFIG_SUPPORT_EMMC_BOOT

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@ -33,6 +33,8 @@
#include "imx6_spl.h" /* common IMX6 SPL configuration */
#include "mx6_common.h"
#undef CONFIG_SPL_EXT_SUPPORT
#undef CONFIG_DISPLAY_BOARDINFO
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */
@ -269,15 +271,13 @@
/* Environment */
#define CONFIG_IPADDR 192.168.1.1
#define CONFIG_SERVERIP 192.168.1.146
#define HWCONFIG_DEFAULT \
"hwconfig=rs232;" \
"dio0:mode=gpio;dio1:mode=gpio;dio2:mode=gpio;dio3:mode=gpio\0" \
#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
"pcidisable=1\0" \
"usb_pgood_delay=2000\0" \
"console=ttymxc1\0" \
"bootdevs=usb mmc sata flash\0" \
HWCONFIG_DEFAULT \
"hwconfig=_UNKNOWN_\0" \
"video=\0" \
\
"mtdparts=" MTDPARTS_DEFAULT "\0" \

View File

@ -13,7 +13,6 @@
#define CONFIG_MXC_UART_BASE UART4_BASE
#define CONFIG_CONSOLE_DEV "ttymxc3"
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
/* USB Configs */
#define CONFIG_USB_EHCI

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@ -137,7 +137,6 @@
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_1G
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR

View File

@ -103,7 +103,6 @@
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_2G
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR

View File

@ -132,7 +132,6 @@
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_1G
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR

View File

@ -21,6 +21,7 @@
#define CONFIG_MXC_GPT_HCLK
#define CONFIG_SYSCOUNTER_TIMER
#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
#define CONFIG_TIMER_CLK_FREQ CONFIG_SC_TIMER_CLK
#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_BOOTM_LEN 0x1000000
@ -28,8 +29,9 @@
/* Enable iomux-lpsr support */
#define CONFIG_IOMUX_LPSR
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_LOADADDR 0x80800000
#define CONFIG_SYS_TEXT_BASE 0x87800000
@ -70,15 +72,8 @@
#define CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
/*
* Default boot linux kernel in no secure mode.
* If want to boot kernel in secure mode, please define CONFIG_MX7_SEC
*/
#ifndef CONFIG_MX7_SEC
#define CONFIG_ARMV7_NONSEC
#define CONFIG_ARMV7_PSCI
#define CONFIG_ARMV7_PSCI_NR_CPUS 2
#define CONFIG_ARMV7_SECURE_BASE 0x00900000
#endif
#endif

View File

@ -22,6 +22,8 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_DISPLAY_BOARDINFO
/* Uncomment to enable secure boot support */
/* #define CONFIG_SECURE_BOOT */
#define CONFIG_CSF_SIZE 0x4000
@ -237,8 +239,6 @@
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
/* USB Configs */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX7
#define CONFIG_USB_STORAGE
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_HOST_ETHER

View File

@ -57,7 +57,6 @@
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE 0xF0000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR

140
include/configs/pcm058.h Normal file
View File

@ -0,0 +1,140 @@
/*
* Copyright (C) Stefano Babic <sbabic@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PCM058_CONFIG_H
#define __PCM058_CONFIG_H
#include <config_distro_defaults.h>
#ifdef CONFIG_SPL
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_DMA_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
#include "imx6_spl.h"
#endif
#include "mx6_common.h"
/* Thermal */
#define CONFIG_IMX_THERMAL
/* Serial */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONFIG_CONSOLE_DEV "ttymxc1"
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
/* Early setup */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_DISPLAY_BOARDINFO_LATE
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
/* Ethernet */
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 3
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_KSZ9031
/* SPI Flash */
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_SPEED 100000
#ifndef CONFIG_SPL_BUILD
#define CONFIG_CMD_NAND
/* Enable NAND support */
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_NAND_MXS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_ONFI_DETECTION
#endif
/* DMA stuff, needed for GPMI/MXS NAND support */
#define CONFIG_APBH_DMA
#define CONFIG_APBH_DMA_BURST
#define CONFIG_APBH_DMA_BURST8
/* Filesystem support */
#define CONFIG_LZO
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define MTDIDS_DEFAULT "nand0=nand"
#define MTDPARTS_DEFAULT "mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
/* Various command support */
#define CONFIG_CMD_BMODE /* set eFUSE shadow for a boot dev and reset */
#define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */
#define CONFIG_CMD_GSC
#define CONFIG_CMD_EECONFIG /* Gateworks EEPROM config cmd */
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 1
/* Environment organization */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_ENV_OFFSET (1024 * SZ_1K)
#define CONFIG_ENV_SECT_SIZE (64 * SZ_1K)
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#ifdef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET (0x1E0000)
#define CONFIG_ENV_SECT_SIZE (128 * SZ_1K)
#endif
#endif

View File

@ -17,8 +17,18 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
/* Network support */
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */
#define CONFIG_BOARD_EARLY_INIT_F
@ -42,24 +52,17 @@
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_G_DNL_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
#define CONFIG_G_DNL_MANUFACTURER "FSL"
#define CONFIG_G_DNL_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
#define CONFIG_G_DNL_MANUFACTURER "FSL"
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define CONFIG_DEFAULT_FDT_FILE "imx6ul-pico-hobbit.dtb"
@ -76,6 +79,7 @@
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
@ -86,7 +90,31 @@
"bootz ${loadaddr} - ${fdt_addr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi;\0"
"fi;\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootz; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootz; " \
"fi;\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan; then " \
@ -118,6 +146,18 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* I2C configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1
#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE3000
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH

View File

@ -17,16 +17,13 @@
#define CONFIG_SYS_FSL_CLK
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MXC_GPIO
#define CONFIG_SYS_NO_FLASH
#include <asm/arch/imx-regs.h>
#include <config_distro_defaults.h>
/* U-Boot commands */
/* U-Boot environment */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
@ -69,17 +66,19 @@
#define CONFIG_CMD_FUSE
#define CONFIG_FSL_IIM
/* Linux boot */
/* U-Boot memory offsets */
#define CONFIG_LOADADDR 0x72000000
#define CONFIG_SYS_TEXT_BASE 0x77800000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Linux boot */
#define CONFIG_HOSTNAME usbarmory
#define CONFIG_BOOTCOMMAND \
"run distro_bootcmd; " \
"setenv bootargs console=${console} ${bootargs_default}; " \
"ext2load mmc 0:1 ${kernel_addr_r} /boot/uImage; " \
"ext2load mmc 0:1 ${kernel_addr_r} /boot/zImage; " \
"ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; " \
"bootm ${kernel_addr_r} - ${fdt_addr_r}"
"bootz ${kernel_addr_r} - ${fdt_addr_r}"
#define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0)
@ -99,6 +98,12 @@
"console=ttymxc0,115200\0" \
BOOTENV
#ifndef CONFIG_CMDLINE
#define CONFIG_BOOTARGS "console=ttymxc0,115200 root=/dev/mmcblk0p1 rootwait rw"
#define USBARMORY_FIT_PATH "/boot/usbarmory.itb"
#define USBARMORY_FIT_ADDR "0x70800000"
#endif
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM CSD0_BASE_ADDR

View File

@ -28,6 +28,18 @@
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
/* SATA Configs */
#define CONFIG_CMD_SATA
#ifdef CONFIG_CMD_SATA
#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
#define CONFIG_LIBATA
#endif
/* Command definition */
#define CONFIG_CMD_BMODE
@ -181,7 +193,7 @@
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif /* __CONFIG_H * */

View File

@ -43,7 +43,6 @@
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_512M
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR

View File

@ -21,6 +21,8 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_DISPLAY_BOARDINFO
/* MMC Config*/
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
#define CONFIG_SUPPORT_EMMC_BOOT
@ -114,8 +116,6 @@
#define CONFIG_MMCROOT "/dev/mmcblk2p2"
/* USB Configs */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX7
#define CONFIG_USB_STORAGE
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@ -125,18 +125,9 @@
#define CONFIG_IMX_THERMAL
#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_G_DNL_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
#define CONFIG_G_DNL_MANUFACTURER "FSL"
/* USB Device Firmware Update support */
#define CONFIG_USB_FUNCTION_DFU

37
include/configs/zc5202.h Normal file
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@ -0,0 +1,37 @@
/*
* Copyright (C) Stefano Babic <sbabic@denx.de>
*
* Configuration settings for the E+L i.MX6Q DO82 board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __EL_ZC5202_H
#define __EL_ZC5202_H
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONFIG_CONSOLE_DEV "ttymxc1"
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
#define CONFIG_DEFAULT_FDT_FILE "imx6q-zc5202.dtb"
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#include "el6x_common.h"
/* Ethernet */
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE MII100
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_MV88E6352_SWITCH
#define CONFIG_CMD_PCI
#define CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX
#endif /*__EL6Q_CONFIG_H */

33
include/configs/zc5601.h Normal file
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@ -0,0 +1,33 @@
/*
* Copyright (C) Stefano Babic <sbabic@denx.de>
*
* Configuration settings for the E+L i.MX6Q DO82 board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __EL_ZC5601_H
#define __EL_ZC5601_H
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONFIG_CONSOLE_DEV "ttymxc1"
#define CONFIG_MMCROOT "/dev/mmcblk0p1"
#define CONFIG_DEFAULT_FDT_FILE "imx6q-zc5601.dtb"
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#include "el6x_common.h"
/* Ethernet */
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0x10
#define CONFIG_PHYLIB
#define CONFIG_FEC_FIXED_SPEED 1000 /* No autoneg, fix Gb */
#endif /*__EL6Q_CONFIG_H */

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@ -9,6 +9,7 @@
/* Information about a serial port */
struct mxc_serial_platdata {
struct mxc_uart *reg; /* address of registers in physical memory */
bool use_dte;
};
#endif

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@ -172,7 +172,13 @@ int fdt_increase_size(void *fdt, int add_len);
int fdt_fixup_nor_flash_size(void *blob);
#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
#else
static inline void fdt_fixup_mtdparts(void *fdt, void *node_info,
int node_info_size) {}
#endif
void fdt_del_node_and_alias(void *blob, const char *alias);
u64 fdt_translate_address(void *blob, int node_offset, const __be32 *in_addr);
int fdt_node_offset_by_compat_reg(void *blob, const char *compat,