Commit Graph

63699 Commits

Author SHA1 Message Date
Tom Warren
224595abaa tegra: Enable CONFIG_BOOTP_PREFER_SERVERIP for all Jetson boards
This allows the user to set $serverip in the environment before
executing a DHCP request. If they do, U-Boot will use that IP rather
than using the IP in the DHCP response.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2020-04-02 14:30:01 -07:00
Vishruth
c0d436fe89 ARM: tegra: p2771-0000: enable PIE relocation
U-Boot is configured to build as position independent executable. Enable
relocation of RELA section required to work with different load
addresses.

Signed-off-by: Vishruth <vishruthj@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Peter Robinson <probinson@gmail.com>
2020-04-02 14:30:01 -07:00
Tom Warren
d43c1dc2e8 i2c: t210: Add VI_I2C clock source support
Fix VI_I2C clock source type. Will be needed by VI_I2C driver.
Also added use of INTERNAL_ID macro in two places, needed to keep
the id returned to 8 bits.

Signed-off-by: Tom Warren <twarren@nvidia.com>
2020-04-02 14:30:01 -07:00
Tom Warren
48ba1969c1 t210: pinmux: Remove pinmux/GPIO init from T210 boards
T210 CBoot is now doing the full pinmux and GPIO init, based on the DTB
tables. Remove pinmux/GPIO init tables & code from all T210-based builds
below:

p2371-2180 aka TX1
p2371-0000
e2220-1170
p2571

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2020-04-02 14:30:01 -07:00
JC Kuo
d491dc09e4 t210: do not enable PLLE and UPHY PLL HW PWRSEQ
This commit removes the programming sequence that enables PLLE and UPHY
PLL hardware power sequencers. Per TRM, boot software should enable PLLE
and UPHY PLLs in software controlled power-on state and should power
down PLL before jumping into kernel or the next stage boot software.

Adds call to board_cleanup_before_linux to facilitate this.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2020-04-02 14:30:01 -07:00
Stephen Warren
9eb15cbe5c ARM: tegra: p2371-2180: add I2C nodes to DT
This adds to the DT the I2C controllers that connect to the board ID EEPROM,
etc. With this change, you can now probe all I2C devices on a TX1 board.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2020-04-02 14:30:01 -07:00
Igor Opaniuk
b308ffb0bf colibri_t30: add update_uboot wrapper
Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage.

Create an proper tegra image:
$ cbootimage -s tegra30 colibri_t30.img.cfg colibri_t30.img

Flash in U-boot shell:
> tftpboot ${loadaddr} ${board_name}/${board_name}.img
> run update_uboot

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-04-02 14:30:00 -07:00
Igor Opaniuk
a63dd98400 colibri_t20: add update_uboot wrapper
Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage(NAND).

Create an proper tegra image:
$ cbootimage -s tegra20 colibri_t20-512-v12-nand.img.cfg colibri_t20.img

Flash in U-boot shell:
> tftpboot ${loadaddr} ${board_name}/${board_name}.img
> run update_uboot

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-04-02 14:30:00 -07:00
Igor Opaniuk
195b48367f apalis_t30: add update_uboot wrapper
Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage.

Create an proper tegra image:
$ cbootimage -s tegra30 apalis_t30.img.cfg apalis_t30.img

Flash in U-boot shell:
> tftpboot ${loadaddr} ${board_name}/${board_name}.img
> run update_uboot

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-04-02 14:30:00 -07:00
Igor Opaniuk
c9d1ff70e2 apalis-tk1: add update_uboot wrapper
Add universal update_uboot wrapper that helps to update
U-Boot image on internal storage.

Create an proper tegra image:
$ cbootimage -s tegra124 apalis-tk1.img.cfg apalis-tk1.img

Flash in U-boot shell:
> tftpboot ${loadaddr} ${board_name}/${board_name}.img
> run update_uboot

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-04-02 14:30:00 -07:00
Tom Rini
e0718b3ab7 Vboot vulnerability fix
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Merge tag 'dm-pull-1apr20' of git://git.denx.de/u-boot-dm

Vboot vulnerability fix
2020-04-01 14:29:21 -04:00
Tom Rini
e88c9e6ff1 - Fix device tree of Avenger96 board from Arrow Electronics and add
compatibility with stm32mp15_dhcom_basic_defconfig
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Merge tag 'u-boot-stm32-20200401' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Fix device tree of Avenger96 board from Arrow Electronics and add
  compatibility with stm32mp15_dhcom_basic_defconfig
2020-04-01 09:47:30 -04:00
Simon Glass
0e29648f8e test: vboot: Reduce fake kernel size to 500 bytes
We don't need 5KB to test things out. A smaller size makes it easier to
look at the FIT with fdtdump.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01 07:45:09 -06:00
Simon Glass
da76ed2795 test: vboot: Move key creation into a function
This code is repeated so move it into a function with a parameter.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01 07:45:09 -06:00
Simon Glass
72188f5462 image: Use constants for 'required' and 'key-name-hint'
These are used in multiple places so update them to use a shared #define.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-04-01 07:45:09 -06:00
Simon Glass
b008677daf test: vboot: Fix pylint errors
Fix various minor things noticed by pylint.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01 07:45:09 -06:00
Simon Glass
3156ee35a3 test: vboot: Tidy up the code a little
Fix some long lines and comments. Use a distinct name for the
'required key' test.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01 07:45:09 -06:00
Simon Glass
c3aa81e35c fit_check_sign: Allow selecting the configuration to verify
This tool always verifies the default configuration. It is useful to be
able to verify a specific one. Add a command-line flag for this and plumb
the logic through.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01 07:45:09 -06:00
Simon Glass
8a9d03732e image: Load the correct configuration in fit_check_sign
At present bootm_host_load_images() is passed the configuration that has
been verified, but ignores it and just uses the default configuration.
This may not be the same.

Update this function to use the selected configuration.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01 07:45:09 -06:00
Simon Glass
67acad3db7 image: Check hash-nodes when checking configurations
It is currently possible to use a different configuration's signature and
thus bypass the configuration check. Make sure that the configuration node
that was hashed matches the one being checked, to catch this problem.

Also add a proper function comment to fit_config_check_sig() and make it
static.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01 07:45:09 -06:00
Simon Glass
1b09003202 test: vboot: Parameterise the test
This test is actually made up of five separate tests. Split them out so
that they appear as separate tests.

Unfortunately this restarts U-Boot multiple times which adds about a
second to the already-long vboot test, about 8 seconds total on my
machine. We could add a special 'teardown' test afterwards but if the
tests are executed out of order that would not work.

Changing test_vboot into a class causes it not to be discovered and makes
it different from all other tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01 07:45:09 -06:00
Simon Glass
c021971e13 test: vboot: Add a test for a forged configuration
Add a check to make sure that it is not possible to add a new
configuration and use the hashed nodes and hash of another configuration.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01 07:45:09 -06:00
Simon Glass
477f559edf test: vboot: Drop unnecessary parameter for fit_check_sign
This tool only uses the last -k parameter provided. Drop the earlier one
since it has no effect.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01 07:45:09 -06:00
Simon Glass
472f9113db image: Return an error message from fit_config_verify_sig()
This function only returns an error message sometimes. Update it to always
return an error message if one is available. This makes it easier to see
what went wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01 07:45:09 -06:00
Simon Glass
382cf62039 image: Be a little more verbose when checking signatures
It is useful to be a little more specific about what is being checked.
Update a few messages to help with this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01 07:45:09 -06:00
Simon Glass
390b26dc27 image: Correct comment for fit_conf_get_node()
This should mention that conf_uname can be NULL and should be in the
header file. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-01 07:45:09 -06:00
Marek Vasut
2f3c4b8a0f ARM: dts: stm32: Repair PMIC configuration on AV96
The core and vdd PMIC buck regulators were misconfigured, which caused
instability of the board and malfunction of high-speed interfaces, like
the RGMII. Configure the PMIC correctly to repair these problems. Also,
model the missing Enpirion EP53A8LQI on the DHCOR SoM as a fixed regulator.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01 11:58:00 +02:00
Marek Vasut
4c8e4c6152 ARM: dts: stm32: Add missing ethernet PHY reset on AV96
Add PHY reset GPIO on AV96 ethernet PHY.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01 11:58:00 +02:00
Marek Vasut
6bb45d08cb ARM: dts: stm32: Repair ethernet operation on AV96
The AV96 RGMII uses different pinmux for ETH_RGMII_TXD0, ETH_RGMII_RXD2
and ETH_RGMII_TX_CTL. Use the correct pinmux to make ethernet operational.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01 11:58:00 +02:00
Marek Vasut
955de51111 ARM: dts: stm32: Add alternate pinmux for ethernet RGMII
Add another mux option for DWMAC RGMII, this is used on AV96 board.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01 11:58:00 +02:00
Marek Vasut
e182dcaa1b ARM: dts: stm32: Add configuration EEPROM on AV96
The board has an EEPROM on the same I2C bus as PMIC, at address 0x53.
The EEPROM contains the board MAC address.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Change-Id: I340a0675c11e4599968b2e3ef0515fb8da8d7b42
2020-04-01 11:58:00 +02:00
Marek Vasut
f19312e5f4 ARM: dts: stm32: Use DT alias for the configuration EEPROM
Use DT /aliases node to establish a stable phandle to the configuration
EEPROM. This permits the configuration EEPROM to be moved e.g. to a
different address or a different bus. Adjust the board code to handle
new phandle lookup.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01 11:58:00 +02:00
Marek Vasut
2f0b5d930d ARM: dts: stm32: Add QSPI NOR on AV96
The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it
into the DT.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Change-Id: Ia7c454c496f50e3fc4851ec1154f3641c416e98e
2020-04-01 11:57:31 +02:00
Marek Vasut
df7f49ca27 ARM: dts: stm32: Repair SDMMC2 operation
The eMMC uses different pinmux for the top four data lines, use such
a pinmux, otherwise it takes a very long time until the test for 8bit
operation times out. And this is the correct pinmux per schematic too.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01 10:12:44 +02:00
Marek Vasut
5fdcba6402 ARM: dts: stm32: Add alternate pinmux for SDMMC2 pins 4-7
Add another mux option for SDMMC2 pins 4..7, this is used on AV96 board.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01 10:12:44 +02:00
Marek Vasut
45fa59b407 ARM: dts: stm32: Repair SDMMC1 operation on AV96
The SD uses different pinmux for the D123DIRline, use such a pinmux,
otherwise there is a pinmux collision on the AV96. Add missing SD
voltage regulator switch and enable SDR104 operation.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01 10:12:44 +02:00
Marek Vasut
4fdbe6487d ARM: dts: stm32: Add alternate pinmux for SDMMC1 direction pins
Add another mux option for SDMMC1 direction pins, in particular
SDMMC1_D123DIR, this is used on AV96 board.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01 10:12:44 +02:00
Marek Vasut
81169ca3cc ARM: dts: stm32: Repair SD1 pre-reloc pinmux DT node on AV96
The sdmmc1_dir_pins_a: sdmmc1-dir-0 layout changed in commit 35a54d41d9
("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") such that pins{};
became pins1{};pins2{};, however the SPL extras were not updated to reflect
that change. Fix this.

This fixes booting from SD1 X9 slot on the AV96 board.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Fixes: 35a54d41d9 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01 10:12:44 +02:00
Tom Rini
7dbafe0634 Merge tag 'arc-last-minute-fixes-for-2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-arc
This last minute pull-request is intended to fix some drivers
when used on ARC boards. The problem was introduced by
07906b3dad

What happened while doing one pretty simple improvement to make
U-Boot port more flexible and portable (by switching accessors from
assembly-written to plain C version) we implicitly added 2 problems:

 1. Downgraded accessors from being volatile which signalled to
    the compiler that it's now possible to do all kinds of optimizations
    which may easily include merge of subsequent byte reads/writes into
    word operations. Which is OK for accessing mormal memory but
    breaks operation of peripherals if we access its memory-mapped regs
    in such a "creative" manner.
 2. As a part of assembly-written implementation we had compiler barriers
    in form of the following construction 'asm volatile("" : : : "memory")',
    and we dropped it in C implemntation. This in its turn enabled compiler
    to mess with instruction ordering. Guess what it gives us in the end :)

So with all that we had in some corner-cases veeery funny instruction flows
generated. And in particular it broke DW SPI functionality when we were
writing large amount of data. Funny enough our tests which were writing
small amount of data still worked and only by the chance we caught that
breakage and unrolled that quite interesting loop of unexpected
problems.

The road to hell is paved with good intentions. Amen :)
2020-03-31 15:10:54 -04:00
Eugeniy Paltsev
45bd649511 ARC: IO: add MB for __raw_* memory accessors
We add memory barriers for __raw_readX / __raw_writeX accessors same
way as it is done for readX and writeX accessors as lots of U-boot
driver uses __raw_readX / __raw_writeX instead of proper accessor
with barrier.

It will save us from lot's of debugging in the future and it is OK
as U-Boot is not that performance oriented as real run-time
software like OS or user bare-metal app so we may afford being not
super fast as we only being executed once.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-03-31 18:31:53 +03:00
Eugeniy Paltsev
e9a23c98c9 ARC: IO: add compiler barriers to IO accessors
We must use compiler barriers in C-version read/write IO accessors
before and after operation (read or write) so it won't be reordered
by compiler.

Fixes commit 07906b3dad ("ARC: Switch to generic accessors")

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-03-31 18:31:53 +03:00
Eugeniy Paltsev
7e57022823 ARC: IO: add volatile to accessors
We must use 'volatile' in C-version read/write IO accessors
implementation to avoid merging several reads (writes) into
one read (write), or optimizing them out by compiler.

Fixes commit 07906b3dad ("ARC: Switch to generic accessors")

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-03-31 18:25:16 +03:00
Tom Rini
150db4264d Merge branch '2020-03-31-master-imports'
- mpc8xxx GPIO, SPI bugfixes
- Add VxWorks to FIT images
- macb ethernet driver bugfix
2020-03-31 10:07:01 -04:00
Michal Simek
7f6b0f3357 net: macb: Fix incorrect write function name when MACB_ZYNQ is enabled.
When MACB_ZYNQ is enabled there is compilation warnings
drivers/net/macb.c: In function ‘_macb_init’:
drivers/net/macb.h:675:33: error: ‘MACB_DMACFG’ undeclared (first use in this function);
 did you mean ‘MACB_MCF’?
  writel((value), (port)->regs + MACB_##reg)
                                 ^~~~~

It has been caused by changing macros name by commit below.

Fixes: 6c636514d4 ("net: macb: sync header definitions as taken from Linux")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2020-03-31 10:06:53 -04:00
Rasmus Villemoes
4856cc7a97 mpc8xxx_spi: implement real ->set_speed
Not all boards have the same CSB frequency, nor do every SPI slave
necessarily support running at 16.7 MHz. So implement ->set_speed;
that also allows using a smaller PM (i.e., 0) for slaves that do
support a higher speed.

Based on work by Klaus H. Sørensen.

Cc: Klaus H. Sorensen <khso@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31 10:06:53 -04:00
Rasmus Villemoes
391c40048b mpc8xxx_spi: always use 8-bit characters, don't read or write garbage
There are a few problems with the current driver.

First, it unconditionally reads from dout/writes to din whether or not
those pointers are NULL. So for example a simple "sf probe" ends up
writing four bytes at address 0:

=> md.l 0x0 8
00000000: 45454545 45454545 05050505 05050505    EEEEEEEE........
00000010: 00000000 00000000 07070707 07070707    ................
=> sf probe 0
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53618 din 00000000 bitlen 8
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 0FB536B8 bitlen 48
SF: Detected s25sl032p with page size 256 Bytes, erase size 64 KiB, total 4 MiB
=> md.l 0x0 8
00000000: ff000000 45454545 05050505 05050505    ....EEEE........
00000010: 00000000 00000000 07070707 07070707    ................

(here I've change the first debug statement to a printf, and made it
print the din/dout pointers rather than the uints they point at).

Second, as we can also see above, it always writes a full 32 bits,
even if a smaller amount was requested. So for example

=> mw.l $loadaddr 0xaabbccdd 8
=> md.l $loadaddr 8
02000000: aabbccdd aabbccdd aabbccdd aabbccdd    ................
02000010: aabbccdd aabbccdd aabbccdd aabbccdd    ................
=> sf read $loadaddr 0x400 6
device 0 offset 0x400, size 0x6
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 48
SF: 6 bytes @ 0x400 Read: OK
=> sf read 0x02000010 0x400 8
device 0 offset 0x400, size 0x8
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53848 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000010 bitlen 64
SF: 8 bytes @ 0x400 Read: OK
=> md.l $loadaddr 8
02000000: 45454545 45450000 aabbccdd aabbccdd    EEEEEE..........
02000010: 45454545 45454545 aabbccdd aabbccdd    EEEEEEEE........

Finally, when the bitlen is 24 mod 32 (e.g. requesting to read 3 or 7
bytes), the last three bytes and up being the wrong ones, since the
driver does a full 32 bit read and then shifts the wrong byte out:

=> mw.l $loadaddr 0xaabbccdd 4
=> md.l $loadaddr 4
02000000: aabbccdd aabbccdd aabbccdd aabbccdd    ................
=> sf read $loadaddr 0x444 10
device 0 offset 0x444, size 0x10
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 128
SF: 16 bytes @ 0x444 Read: OK
=> md.l $loadaddr 4
02000000: 552d426f 6f742032 3031392e 30342d30    U-Boot 2019.04-0
=> mw.l $loadaddr 0xaabbccdd 4
=> sf read $loadaddr 0x444 0xb
device 0 offset 0x444, size 0xb
mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 88
SF: 11 bytes @ 0x444 Read: OK
=> md.l $loadaddr 4
02000000: 552d426f 6f742032 31392e00 aabbccdd    U-Boot 219......

Fix all of that by always using a character size of 8, and reject
transfers that are not a whole number of bytes. While it ends being
more work for the CPU, we're mostly bounded by the speed of the SPI
bus, and we avoid writing to the mode register in every loop.

Based on work by Klaus H. Sørensen.

Cc: Klaus H. Sorensen <khso@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31 10:06:53 -04:00
Rasmus Villemoes
1a7b462dee mpc8xxx_spi: put max_cs to use
Currently, max_cs is write-only; it's just set in
mpc8xxx_spi_ofdata_to_platdata and not otherwise used.

My mpc8309 was always resetting during an "sf probe 0". It turns out
dm_gpio_set_dir_flags() was being called with garbage, since nothing
had initialized priv->gpios[0] - our device tree used "cs-gpios"
rather than "gpios", so gpio_request_list_by_name() had returned 0.

That would have been a lot easier to figure out if the chip select
index was sanity checked, so rename max_cs to cs_count, and reject a
xfer with a too large cs index.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31 10:06:52 -04:00
Rasmus Villemoes
96e68c1621 gazerbeam: add clocks property to SPI node
Prepare for supporting setting different speeds in mpc8xxx_spi.c.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31 10:06:52 -04:00
Klaus H. Sorensen
3fb22bc2f8 gpio/mpc83xx_spisel_boot.c: gpio driver for SPISEL_BOOT signal
Some SoCs in the mpc83xx family, e.g. mpc8309, have a dedicated spi
chip select, SPISEL_BOOT, that is used by the boot code to boot from
flash.

This chip select will typically be used to select a SPI boot
flash. The SPISEL_BOOT signal is controlled by a single bit in the
SPI_CS register.

Implement a gpio driver for the spi chip select register. This allows a
spi driver capable of using gpios as chip select, to bind a chip select
to SPISEL_BOOT.

It may be a little odd to do this as a GPIO driver, since the signal
is neither GP or I, but it is quite convenient to present it to the
spi driver that way. The alternative it to teach mpc8xxx_spi to handle
the SPISEL_BOOT signal itself (that is how it's done in the linux
kernel, see commit 69b921acae8a)

Signed-off-by: Klaus H. Sorensen <khso@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31 10:06:52 -04:00
Rasmus Villemoes
dd4cf53f98 gpio: mpc8xxx: don't do RMW on gpdat register when setting value
The driver correctly handles reading back the value of an output gpio
by reading from the shadow register for output, and from gpdat for
inputs.

Unfortunately, when setting the value of some gpio, we do a RMW cycle
on the gpdat register without taking the shadow register into account,
thus accidentally setting other output gpios (at least those whose
value cannot be read back) to 0 at the same time.

When changing a gpio from input to output, we still need to make sure
it initially has the requested value. So, the procedure is

- update the shadow register
- compute the new gpdir register
- write the bitwise and of the shadow and new gpdir register to gpdat
- write the new gpdir register

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31 10:06:52 -04:00