rsa-checsum needs support for hash functions or else will run into
compile errors like:
u-boot/lib/rsa/rsa-checksum.c:28: undefined reference to `hash_progressive_lookup_algo'
So similar to the main FIT_SIGNATURE entry selects HASH,
select SPL_HASH_SUPPORT for SPL_FIT_SIGNATURE.
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
padding_pss_verify only works with the default pss salt setting of -2
(length to be automatically determined based on the PSS block structure)
not -1 (salt length set to the maximum permissible value), which makes
verifications of signatures with that saltlen fail.
Until this gets implemented at least document this behaviour.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
n, rr and rrtmp are used for internal calculations, but in the end
the results are copied into separately allocated elements of the
actual key_prop, so the n, rr and rrtmp elements are not used anymore
when returning from the function and should of course be freed.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When calculating rrtmp/rr rsa_gen_key_prop() tries to make
(((rlen + 31) >> 5) + 1) steps in the rr uint32_t array and
(((rlen + 7) >> 3) + 1) / 4 steps in uint32_t rrtmp[]
with rlen being num_bits * 2
On a 4096bit key this comes down to to 257 uint32_t elements
in rr and 256 elements in rrtmp but with the current allocation
rr and rrtmp only have 129 uint32_t elements.
On 2048bit keys this works by chance as the defined max_rsa_size=4096
allocates a suitable number of elements, but with an actual 4096bit key
this results in other memory parts getting overwritten.
So as suggested by Heinrich Schuchardt just use the actual bit-size
of the key as base for the size calculation, in turn making the code
compatible to any future keysizes.
Suggested-by: Heinrich Schuchardt <xypron.debian@gmx.de>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
rrtmp needs 2 + (((*prop)->num_bits * 2) >> 5) array elements.
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
The exponent field of struct key_prop gets allocated an uint64_t,
and the contents are positioned from the back, so an exponent of
"0x01 0x00 0x01" becomes 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1"
Right now rsa_gen_key_prop() allocates a uint64_t but sets exp_len
to the size returned from the parser, while on the other hand the
when getting the key from the devicetree exp_len always gets set to
sizeof(uint64_t).
So bring that in line with the established code.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Right now in multiple places there are only checks for the full
CONFIG_RSA_VERIFY_WITH_PKEY option, not split into main,spl,tpl variants.
This breaks when the rsa functions get enabled for SPL, for example to
verify u-boot proper from spl.
So fix this by using the existing helpers to distinguis between
build-steps.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
While the SPL may want to do signature checking this won't be
the case for TPL in all cases, as TPL is mostly used when the
amount of initial memory is not enough for a full SPL.
So on a system where SPL uses DM but TPL does not we currently
end up with a TPL compile error of:
lib/rsa/rsa-verify.c:48:25: error: dereferencing pointer to incomplete type ‘struct checksum_algo’
To prevent that change the $(SPL_) to $(SPL_TPL_) to distinguish
between both. If someone really needs FIT signature checking in
TPL as well, a new TPL_RSA_VERIFY config symbol needs to be added.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Even in boot scripts it may be needed to "panic" when all options
are exhausted and the device specification specifies hanging
instead of resetting the board.
So add a new panic command that just wraps around the core panic
call in U-Boot and can take an optional message.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add linefeeds before and after the announce string. This makes the
output easier to read, especially if some text follows the announce
message without a specific additional CR.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
tpm_tis_spi.c directly includes tpm_tis.h and tpm-v2.h which both
define the same enums (see e.g. TPM_ACCESS_VALID). Add an #ifndef to
prevent redeclaration errors.
Signed-off-by: Johannes Holland <johannes.holland@infineon.com>
This solves a compatibility issue with Linux device trees
that contain TPMv2.x hardware. So it's easier to import DTS
from upstream kernel when migrating board init from C code
to DTS.
The issue is that fallback binding is different between Linux
and u-Boot.
Linux: "tcg,tpm_tis-spi"
U-Boot: "tis,tpm2-spi"
As there are currently no in-tree users of the U-Boot binding,
it makes sense to use Linux fallback binding.
Signed-off-by: Bruno Thomsen <bruno.thomsen@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
commit 2bd261dd17 ("gpio: search for gpio label if gpio is not found through bank name")
disabled DM_GPIO_LOOKUP_LABEL which is needed
in sandbox defconfigs, as we have tests for this
functionality.
Signed-off-by: Heiko Schocher <hs@denx.de>
The PHY needs a reset in order to be functionnal for U-Boot, add the old
PHY reset bindings for dwmac until we support the new bindings in the PHY node.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Odroid C4 is an Amlogic SM1 device, the board config and board documentation
are adapted from the Odroid-N2 support from the same vendor.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
[narmstrong: fix odroid-c4.rst typos and structure]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
This imports the changes and the new Odroid-C4 board from the Linux
commit b3a9e3b9622a ("Linux 5.8-rc1").
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Add a proper Odroid-N2 board support to handle the Ethernet MAC
address stored in the in-SoC eFuses.
Signed-off-by: Pascal Vizeli <pvizeli@syshack.ch>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
The ARM Juno boards (-r1 and -r2) feature a Silicon Image 3132 PCIe
SATA controller soldered on the board, providing two SATA ports.
Enable the driver and the sata command in the defconfig, to be able to
load images from SATA disks.
Tested by loading kernels and Grub/EFI from an SSD and successfully
booting a Linux system (with and without using UEFI).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
The ARM Juno boards in their -r1 and -r2 variants sport a PCIe
controller, which we configure already in board specific code to be ECAM
compliant. Hence we can just enable the generic ECAM driver to let
U-Boot use PCIe devices.
Add the respective options to the Juno defconfig to enable the PCI
framework and the generic ECAM driver, and initialise the driver upon
loading U-Boot.
Make some functions in the Juno PCIe init code static on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Even though the sata_sil driver was converted over to the driver model,
it still assumed that the PCI controller is using the legacy interface.
Allow the "devno" member to be a struct udevice pointer and use
DM_PCI_COMPAT to covert the rest of the interface.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
The smc911X driver is now DM enabled, so we can switch the Juno board
over to use DM_ETH for the on-board Fast Ethernet device.
Works out of the box by using the DT.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
When compiled as a DM_ETH driver, the scm911x driver was reading the MAC
address from the optional EEPROM storage, but failed to copy this to the
platdata struct. Since it was also missing a definition of the
read_rom_hwaddr() function, the generic Ethernet code was dismissing
this MAC address, falling back to a random address or denying to start
at all.
Add an implementation of .read_rom_hwaddr, and refactor the function
reading the ROM address to be called by all interested parties.
This fixes MAC address issues when using the driver in DM_ETH "mode".
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Similar to patch 821fec0ceb ("net: remove scary warning about EEPROM
provided MAC address") this removes the somewhat awkward "warning" on
boards using DM_ETH:
In many parts of the computing world having a unique MAC address
sitting in some on-NIC storage is considered the normal case.
If there is a properly provided MAC address (either from ROM or from DT),
remove the warning to not scare the user unnecessarily.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
The arch timer on 64-bit Arm Ltd. platforms is driven by a 24 MHz
crystal oscillator, so the frequency is not 25165824 MHz, as the current
code suggests.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Compiling with clang on ARMv8 shows errors like:
./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w"
asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
^~
%w0
These errors are due to using an incorrect size for the variables used
for writing to and reading from special registers which have 64 bits on
ARMv8.
Mask off reserved bits when reading the exception level.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
On ARM systems gd is stored in register r9 or x18. When compiling with
clang gd is defined as a macro calling function gd_ptr(). So we can not
make assignments to gd.
Use function set_gd() for setting the register on ARM.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Truncate file names if the buffer size is exceeded to avoid a buffer
overflow.
Use Sphinx style function description.
Add a TODO comment.
Reported-by: CID 303779
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
make the sleep time and the margin configurable.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
dm_gpio_lookup_name() searches for a gpio through
the bank name. But we have also gpio labels, and it
makes sense to search for a gpio also in the labels
we have defined, if no gpio is found through the
bank name definition.
This is useful for example if you have a wp pin on
different gpios on different board versions.
If dm_gpio_lookup_name() searches also for the gpio labels,
you can give the gpio an unique label name and search
for this label, and do not need to differ between
board revisions.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Don't enable by default]
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch adds MAC and PHY related configs (needed for proper
ethernet operations) for Action Semi S700 SoC.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
This patch selects CONFIG_DM_ETH (ethernet driver is base on DM model)
for Action semi owl SoC.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
This patch adds node for ethernet controller found on Action Semi OWL
S700 SoC.
Since, there is no upstream Linux binding exist for S700 ethernet
controller, Changes are put in u-boot specific dtsi file.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
This patchs adds glue logic to enable designware mac present on
Action Semi based S700 SoC, Configures SoC specific bits.
Undocumented bit that programs the PHY interface select register
comes from vendor source.
It has been tested on Cubieboard7-lite based on S700 SoC.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
RTL8201F PHY module found on Actions Semi Cubieboard7 seems to have
specific Rx/Tx interface timings requirement for proper PHY operations.
These timing values are not documented anywhere and picked from vendor
code.
This commits lets proper packets to be transmitted over the network.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
This patch adds support for Realtek PHY RTL8201F 10/100Mbs
(with variants: RTL8201FN and RTL8201FL) PHYceiver. It is
present on Actions Semi Cubieboard7 board.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
This commit adds clocks needed for ethernet operations for
Actions OWL family of SoCs (S700 and S900).
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Now that, we calculate SDRAM size by reading DDR registers,
"CONFIG_SYS_SDRAM_SIZE" is no more needed.
This commit removes "CONFIG_SYS_SDRAM_SIZE" from common configuration
file.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Calculate the SDRAM size from DDR capacity register registers instead
of using hard-coded value. This is quite useful to get correct size
on differnt boards based on Actions OWL family of SoCs (S700 and S900).
There is no documentation available that talks about DDR registers, and
this is very much taken from vendor source.
This commit lets Linux boot on Cubieboard7-lite(based on S700).
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This patch adds support for ZSTD decompression of FIT images.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Add a command to print a list of available block device drivers,
and for each, the list of known block devices.
Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Renamed dm "drivers" subcommand to "compat" (as it listed
compatibility strings) and prevent it from segfaulting when
drivers have no of_match populated.
Added a new "drivers" subcommand to dump a list of all known DM
drivers and for each, their uclass id, uclass driver and names of
attached devices.
Added a new "static" subcommand to dump a list of DM drivers with
statically defined platform data.
Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added command "fstypes" to list supported/included filesystems.
Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Limit to sandbox]
Signed-off-by: Tom Rini <trini@konsulko.com>
Add a subcommand "types" to the part command, which lists the supported
partition table types.
Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
- use OPP information in device tree for 800MHz/650MHz support
- ram: inprovments of test command
- solve boot on closed chip when access to DBGMCU_IDC is protected
- stm32prog command: Add "device anme" during USB enumeration
- update configs: activate WATCHDOG and 'env erase' command,
increase teed partition, support SD card after NOR boot by default and
use env info in env_check
- some sboard cleanups: gpio hog in dh board, specific driver for
type-c stusb1600 controller code in a driver move part of code in spl.c
and in common directory
- fix STM32 compatible for dwc_eth_qos driver
- support of new pinctrl ops get_dir_flags/set_dir_flags in stm32 and stmfx
drivers
- vrefbuf: fix a possible overshoot when re-enabling
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Merge tag 'u-boot-stm32-20200707' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- arch and board update for stm32mp15:
- use OPP information in device tree for 800MHz/650MHz support
- ram: inprovments of test command
- solve boot on closed chip when access to DBGMCU_IDC is protected
- stm32prog command: Add "device anme" during USB enumeration
- update configs: activate WATCHDOG and 'env erase' command,
increase teed partition, support SD card after NOR boot by default and
use env info in env_check
- some sboard cleanups: gpio hog in dh board, specific driver for
type-c stusb1600 controller code in a driver move part of code in spl.c
and in common directory
- fix STM32 compatible for dwc_eth_qos driver
- support of new pinctrl ops get_dir_flags/set_dir_flags in stm32 and stmfx
drivers
- vrefbuf: fix a possible overshoot when re-enabling
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Merge tag 'u-boot-atmel-2020.10-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel features for 2020.10 cycle
ARM Architecture reference manual clearly states that PE pipeline
should be flushed after changes to some system registers. Refer to
paragraph "B2.3.5 Memory Barriers" at page B2-92 of "Arm Architecture
Reference Manual ARMv8 for ARMv8-A Architecture Profile" (ARM DDI
0487B.a).
Failing to issue instruction synchronization barrier can lead to
spurious errors, like synchronous exception when accessing FPU
registers. This is very prominent on CPUs with long instruction
pipeline, like ARM Cortex A72.
This change fixes the following U-Boot panic:
"Synchronous Abort" handler, esr 0x1fe00000
elr: 00000000800948cc lr : 0000000080091e04
x0 : 00000000801ffdc8 x1 : 00000000000000c8
x2 : 00000000800979d4 x3 : 00000000801ffc60
x4 : 00000000801ffd40 x5 : ffffff80ffffffd8
x6 : 00000000801ffd70 x7 : 00000000801ffd70
x8 : 000000000000000a x9 : 0000000000000000
x10: 0000000000000044 x11: 0000000000000000
x12: 0000000000000000 x13: 0000000000000000
x14: 0000000000000000 x15: 0000000000000000
x16: 000000008008b2e0 x17: 0000000000000000
x18: 00000000801ffec0 x19: 00000000800957b0
x20: 00000000000000c8 x21: 00000000801ffdc8
x22: 000000008009909e x23: 0000000000000000
x24: 0000000000000000 x25: 0000000000000000
x26: 0000000000000000 x27: 0000000000000000
x28: 0000000000000000 x29: 00000000801ffc50
Code: a94417e4 a90217e4 a9051fe6 a90617e4 (3d801fe0)
While executing instruction
str q0, [sp, #112]
in vsnprintf() prologue. This panic was observed only on Cortex A72 so
far.
This patch places ISBs on other strategic places as well.
Also, this probably is the right fix for the issue workarounded in the
commit 45f41c134b ("ARM: uniphier: add weird workaround code for LD20")
Reported-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Suggested-by: Julien Grall <julien.grall.oss@gmail.com>
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
CC: Tom Rini <trini@konsulko.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Stefano Stabellini <sstabellini@kernel.org>
Reviewed-by: Julien Grall <julien@xen.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
