mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-sh
- R8A77980 V3H support
This commit is contained in:
Tom Rini
commit
feb5a02f86
|
|
@ -645,6 +645,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
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|||
r8a77965-m3nulcb-u-boot.dtb \
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||||
r8a77965-salvator-x-u-boot.dtb \
|
||||
r8a77970-eagle-u-boot.dtb \
|
||||
r8a77980-condor-u-boot.dtb \
|
||||
r8a77990-ebisu-u-boot.dtb \
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r8a77995-draak-u-boot.dtb
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||||
|
||||
|
|
|
|||
34
arch/arm/dts/r8a77980-condor-u-boot.dts
Normal file
34
arch/arm/dts/r8a77980-condor-u-boot.dts
Normal file
|
|
@ -0,0 +1,34 @@
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|||
// SPDX-License-Identifier: GPL-2.0
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||||
/*
|
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* Device Tree Source extras for U-Boot for the Condor board
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*
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* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
|
||||
*/
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||||
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||||
#include "r8a77980-condor.dts"
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#include "r8a77980-u-boot.dtsi"
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||||
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||||
/ {
|
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aliases {
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||||
spi0 = &rpc;
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||||
};
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||||
};
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|
||||
&rpc {
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num-cs = <1>;
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status = "okay";
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spi-max-frequency = <50000000>;
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||||
#address-cells = <1>;
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||||
#size-cells = <0>;
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||||
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||||
flash0: spi-flash@0 {
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#address-cells = <1>;
|
||||
#size-cells = <1>;
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||||
compatible = "s25fs512s", "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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reg = <0>;
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status = "okay";
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};
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||||
};
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292
arch/arm/dts/r8a77980-condor.dts
Normal file
292
arch/arm/dts/r8a77980-condor.dts
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the Condor board
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
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* Copyright (C) 2018 Cogent Embedded, Inc.
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||||
*/
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||||
/dts-v1/;
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#include "r8a77980.dtsi"
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/ {
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model = "Renesas Condor board based on r8a77980";
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compatible = "renesas,condor", "renesas,r8a77980";
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||||
|
||||
aliases {
|
||||
serial0 = &scif0;
|
||||
ethernet0 = &gether;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0 0x48000000 0 0x78000000>;
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||||
};
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||||
|
||||
d3_3v: regulator-0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
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||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
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vddq_vin01: regulator-1 {
|
||||
compatible = "regulator-fixed";
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||||
regulator-name = "VDDQ_VIN01";
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regulator-min-microvolt = <1800000>;
|
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
|
||||
};
|
||||
|
||||
d1_8v: regulator-2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
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|
||||
hdmi-out {
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||||
compatible = "hdmi-connector";
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||||
type = "a";
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port {
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||||
hdmi_con: endpoint {
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||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds-decoder {
|
||||
compatible = "thine,thc63lvd1024";
|
||||
vcc-supply = <&d3_3v>;
|
||||
|
||||
ports {
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||||
#address-cells = <1>;
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||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
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||||
reg = <0>;
|
||||
thc63lvd1024_in: endpoint {
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||||
remote-endpoint = <&lvds0_out>;
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||||
};
|
||||
};
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||||
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||||
port@2 {
|
||||
reg = <2>;
|
||||
thc63lvd1024_out: endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
x1_clk: x1-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
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||||
clock-frequency = <148500000>;
|
||||
};
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||||
};
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||||
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||||
&canfd {
|
||||
pinctrl-0 = <&canfd0_pins>;
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||||
pinctrl-names = "default";
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||||
status = "okay";
|
||||
|
||||
channel0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&x1_clk>;
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||||
clock-names = "du.0", "dclkin.0";
|
||||
status = "okay";
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||||
};
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||||
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||||
&extal_clk {
|
||||
clock-frequency = <16666666>;
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||||
};
|
||||
|
||||
&extalr_clk {
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||||
clock-frequency = <32768>;
|
||||
};
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||||
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&gether {
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pinctrl-0 = <&gether_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&phy0>;
|
||||
renesas,no-ether-link;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
io_expander0: gpio@20 {
|
||||
compatible = "onnn,pca9654";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
io_expander1: gpio@21 {
|
||||
compatible = "onnn,pca9654";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
|
||||
avdd-supply = <&d1_8v>;
|
||||
dvdd-supply = <&d1_8v>;
|
||||
pvdd-supply = <&d1_8v>;
|
||||
bgvdd-supply = <&d1_8v>;
|
||||
dvdd-3v-supply = <&d3_3v>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
pinctrl-0 = <&mmc_pins>;
|
||||
pinctrl-1 = <&mmc_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&d3_3v>;
|
||||
vqmmc-supply = <&vddq_vin01>;
|
||||
mmc-hs200-1_8v;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pciec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
canfd0_pins: canfd0 {
|
||||
groups = "canfd0_data_a";
|
||||
function = "canfd0";
|
||||
};
|
||||
|
||||
gether_pins: gether {
|
||||
groups = "gether_mdio_a", "gether_rgmii",
|
||||
"gether_txcrefclk", "gether_txcrefclk_mega";
|
||||
function = "gether";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
mmc_pins: mmc {
|
||||
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
|
||||
function = "mmc";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
mmc_pins_uhs: mmc_uhs {
|
||||
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
|
||||
function = "mmc";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk_b";
|
||||
function = "scif_clk";
|
||||
};
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
24
arch/arm/dts/r8a77980-u-boot.dtsi
Normal file
24
arch/arm/dts/r8a77980-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot on RCar R8A77980 SoC
|
||||
*
|
||||
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
|
||||
*/
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&extalr_clk {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
/ {
|
||||
soc {
|
||||
rpc: rpc@0xee200000 {
|
||||
compatible = "renesas,rpc-r8a77980", "renesas,rpc";
|
||||
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
bank-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
1605
arch/arm/dts/r8a77980.dtsi
Normal file
1605
arch/arm/dts/r8a77980.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -22,6 +22,11 @@ config R8A77970
|
|||
imply CLK_R8A77970
|
||||
imply PINCTRL_PFC_R8A77970
|
||||
|
||||
config R8A77980
|
||||
bool "Renesas SoC R8A77980"
|
||||
imply CLK_R8A77980
|
||||
imply PINCTRL_PFC_R8A77980
|
||||
|
||||
config R8A77990
|
||||
bool "Renesas SoC R8A77990"
|
||||
imply CLK_R8A77990
|
||||
|
|
@ -38,6 +43,12 @@ choice
|
|||
prompt "Renesas ARM64 SoCs board select"
|
||||
optional
|
||||
|
||||
config TARGET_CONDOR
|
||||
bool "Condor board"
|
||||
imply R8A77980
|
||||
help
|
||||
Support for Renesas R-Car Gen3 Condor platform
|
||||
|
||||
config TARGET_DRAAK
|
||||
bool "Draak board"
|
||||
imply R8A77995
|
||||
|
|
@ -83,6 +94,7 @@ endchoice
|
|||
config SYS_SOC
|
||||
default "rmobile"
|
||||
|
||||
source "board/renesas/condor/Kconfig"
|
||||
source "board/renesas/draak/Kconfig"
|
||||
source "board/renesas/eagle/Kconfig"
|
||||
source "board/renesas/ebisu/Kconfig"
|
||||
|
|
|
|||
|
|
@ -64,6 +64,7 @@ static const struct {
|
|||
{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
|
||||
{ RMOBILE_CPU_TYPE_R8A77965, "R8A77965" },
|
||||
{ RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
|
||||
{ RMOBILE_CPU_TYPE_R8A77980, "R8A77980" },
|
||||
{ RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
|
||||
{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
|
||||
{ 0x0, "CPU" },
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@
|
|||
#define RMOBILE_CPU_TYPE_R8A7796 0x52
|
||||
#define RMOBILE_CPU_TYPE_R8A77965 0x55
|
||||
#define RMOBILE_CPU_TYPE_R8A77970 0x54
|
||||
#define RMOBILE_CPU_TYPE_R8A77980 0x56
|
||||
#define RMOBILE_CPU_TYPE_R8A77990 0x57
|
||||
#define RMOBILE_CPU_TYPE_R8A77995 0x58
|
||||
|
||||
|
|
|
|||
15
board/renesas/condor/Kconfig
Normal file
15
board/renesas/condor/Kconfig
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
if TARGET_CONDOR
|
||||
|
||||
config SYS_SOC
|
||||
default "rmobile"
|
||||
|
||||
config SYS_BOARD
|
||||
default "condor"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "renesas"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "condor"
|
||||
|
||||
endif
|
||||
6
board/renesas/condor/MAINTAINERS
Normal file
6
board/renesas/condor/MAINTAINERS
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
CONDOR BOARD
|
||||
M: Marek Vasut <marek.vasut+renesas@gmail.com>
|
||||
S: Maintained
|
||||
F: board/renesas/condor/
|
||||
F: include/configs/condor.h
|
||||
F: configs/r8a77980_condor_defconfig
|
||||
13
board/renesas/condor/Makefile
Normal file
13
board/renesas/condor/Makefile
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
#
|
||||
# board/renesas/condor/Makefile
|
||||
#
|
||||
# Copyright (C) 2019 Renesas Electronics Corporation
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y := ../rcar-common/gen3-spl.o
|
||||
else
|
||||
obj-y := condor.o ../rcar-common/common.o
|
||||
endif
|
||||
55
board/renesas/condor/condor.c
Normal file
55
board/renesas/condor/condor.c
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* board/renesas/condor/condor.c
|
||||
* This file is Condor board support.
|
||||
*
|
||||
* Copyright (C) 2019 Marek Vasut <marek.vasut+renesas@gmail.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/errno.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void s_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define RST_BASE 0xE6160000
|
||||
#define RST_CA57RESCNT (RST_BASE + 0x40)
|
||||
#define RST_CA53RESCNT (RST_BASE + 0x44)
|
||||
#define RST_RSTOUTCR (RST_BASE + 0x58)
|
||||
#define RST_CA57_CODE 0xA5A5000F
|
||||
#define RST_CA53_CODE 0x5A5A000F
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
unsigned long midr, cputype;
|
||||
|
||||
asm volatile("mrs %0, midr_el1" : "=r" (midr));
|
||||
cputype = (midr >> 4) & 0xfff;
|
||||
|
||||
if (cputype == 0xd03)
|
||||
writel(RST_CA53_CODE, RST_CA53RESCNT);
|
||||
else if (cputype == 0xd07)
|
||||
writel(RST_CA57_CODE, RST_CA57RESCNT);
|
||||
else
|
||||
hang();
|
||||
}
|
||||
69
configs/r8a77980_condor_defconfig
Normal file
69
configs/r8a77980_condor_defconfig
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_TEXT_BASE=0x50000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_TARGET_CONDOR=y
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
CONFIG_FIT=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_DEFAULT_FDT_FILE="r8a77980-condor.dtb"
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_SPL_TEXT_BASE=0xe6318000
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a77980-condor-u-boot"
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_BLK=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_CLK_RENESAS=y
|
||||
CONFIG_DFU_TFTP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_DFU_SF=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_RCAR_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_IIC=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_SH_ETHER=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_RENESAS_RPC_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SMBIOS_MANUFACTURER=""
|
||||
|
|
@ -72,6 +72,12 @@ config CLK_R8A77970
|
|||
help
|
||||
Enable this to support the clocks on Renesas R8A77970 SoC.
|
||||
|
||||
config CLK_R8A77980
|
||||
bool "Renesas R8A77980 clock driver"
|
||||
depends on CLK_RCAR_GEN3
|
||||
help
|
||||
Enable this to support the clocks on Renesas R8A77980 SoC.
|
||||
|
||||
config CLK_R8A77990
|
||||
bool "Renesas R8A77990 clock driver"
|
||||
depends on CLK_RCAR_GEN3
|
||||
|
|
|
|||
|
|
@ -10,5 +10,6 @@ obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
|
|||
obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
|
||||
|
|
|
|||
255
drivers/clk/renesas/r8a77980-cpg-mssr.c
Normal file
255
drivers/clk/renesas/r8a77980-cpg-mssr.c
Normal file
|
|
@ -0,0 +1,255 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a77980 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2018 Cogent Embedded, Inc.
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A77980_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL3,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_OCO,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a77980_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
DEF_RATE(".oco", CLK_OCO, 32768),
|
||||
|
||||
DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A77980_CLK_RPC),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A77980_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("s0d1", R8A77980_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d2", R8A77980_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A77980_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A77980_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6", R8A77980_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d12", R8A77980_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s0d24", R8A77980_CLK_S0D24, CLK_S0, 24, 1),
|
||||
DEF_FIXED("s1d1", R8A77980_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A77980_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A77980_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A77980_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A77980_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A77980_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A77980_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, CLK_SDSRC, 0x0074),
|
||||
|
||||
DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A77980_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
|
||||
DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8),
|
||||
DEF_GEN3_MDSEL("r", R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77980_mod_clks[] = {
|
||||
DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6),
|
||||
DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6),
|
||||
DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6),
|
||||
DEF_MOD("tmu1", 124, R8A77980_CLK_S0D6),
|
||||
DEF_MOD("tmu0", 125, R8A77980_CLK_CP),
|
||||
DEF_MOD("scif4", 203, R8A77980_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A77980_CLK_S3D4),
|
||||
DEF_MOD("scif1", 206, R8A77980_CLK_S3D4),
|
||||
DEF_MOD("scif0", 207, R8A77980_CLK_S3D4),
|
||||
DEF_MOD("msiof3", 208, R8A77980_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A77980_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A77980_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A77980_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
|
||||
DEF_MOD("cmt3", 300, R8A77980_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A77980_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A77980_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A77980_CLK_R),
|
||||
DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
|
||||
DEF_MOD("sdif", 314, R8A77980_CLK_SD0),
|
||||
DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2),
|
||||
DEF_MOD("rwdt", 402, R8A77980_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
|
||||
DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
|
||||
DEF_MOD("hscif2", 518, R8A77980_CLK_S3D1),
|
||||
DEF_MOD("hscif1", 519, R8A77980_CLK_S3D1),
|
||||
DEF_MOD("hscif0", 520, R8A77980_CLK_S3D1),
|
||||
DEF_MOD("imp4", 521, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("thermal", 522, R8A77980_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A77980_CLK_S0D12),
|
||||
DEF_MOD("impdma1", 526, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("impdma0", 527, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp-ocv4", 528, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1),
|
||||
DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1),
|
||||
DEF_MOD("csi41", 715, R8A77980_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A77980_CLK_CSI0),
|
||||
DEF_MOD("du0", 724, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2),
|
||||
DEF_MOD("gether", 813, R8A77980_CLK_S3D2),
|
||||
DEF_MOD("imp3", 824, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp2", 825, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp1", 826, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp0", 827, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp-ocv1", 828, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp-ocv0", 829, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("impram", 830, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("impcnn", 831, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("gpio5", 907, R8A77980_CLK_CP),
|
||||
DEF_MOD("gpio4", 908, R8A77980_CLK_CP),
|
||||
DEF_MOD("gpio3", 909, R8A77980_CLK_CP),
|
||||
DEF_MOD("gpio2", 910, R8A77980_CLK_CP),
|
||||
DEF_MOD("gpio1", 911, R8A77980_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A77980_CLK_CP),
|
||||
DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2),
|
||||
DEF_MOD("rpc-if", 917, R8A77980_CLK_RPCD2),
|
||||
DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A77980_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A77980_CLK_S3D2),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL2 PLL1 PLL3 OSC
|
||||
* 14 13 (MHz)
|
||||
* --------------------------------------------------------
|
||||
* 0 0 16.66 x 1 x240 x192 x192 /16
|
||||
* 0 1 20 x 1 x200 x160 x160 /19
|
||||
* 1 0 27 x 1 x148 x118 x118 /26
|
||||
* 1 1 33.33 / 2 x240 x192 x192 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
|
||||
(((md) & BIT(13)) >> 13))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 118, 1, 118, 1, 26, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a77980_mstp_table[] = {
|
||||
{ 0x00230000, 0x0, 0x00230000, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x14062FD8, 0x2040, 0x14062FD8, 0 },
|
||||
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0 },
|
||||
{ 0x83FFFFFF, 0x0, 0x83FFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x7FF3FFF4, 0x0, 0x7FF3FFF4, 0 },
|
||||
{ 0xFBF7FF97, 0x0, 0xFBF7FF97, 0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
|
||||
{ 0x000000B7, 0x0, 0x000000B7, 0 },
|
||||
};
|
||||
|
||||
static const void *r8a77980_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a77980_cpg_mssr_info = {
|
||||
.core_clk = r8a77980_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a77980_core_clks),
|
||||
.mod_clk = r8a77980_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a77980_mod_clks),
|
||||
.mstp_table = r8a77980_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a77980_mstp_table),
|
||||
.reset_node = "renesas,r8a77980-rst",
|
||||
.extalr_node = "extalr",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = CLK_EXTALR,
|
||||
.get_pll_config = r8a77980_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a77980_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a77980-cpg-mssr",
|
||||
.data = (ulong)&r8a77980_cpg_mssr_info
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a77980) = {
|
||||
.name = "clk_r8a77980",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a77980_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
|
|
@ -37,8 +37,8 @@
|
|||
#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
|
||||
!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
|
||||
#define flush_cache_wback(addr, len) \
|
||||
flush_dcache_range((u32)addr, \
|
||||
(u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
|
||||
flush_dcache_range((unsigned long)addr, \
|
||||
(unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
|
||||
#else
|
||||
#define flush_cache_wback(...)
|
||||
#endif
|
||||
|
|
@ -46,11 +46,11 @@
|
|||
#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
|
||||
#define invalidate_cache(addr, len) \
|
||||
{ \
|
||||
u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
|
||||
u32 start, end; \
|
||||
unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
|
||||
unsigned long start, end; \
|
||||
\
|
||||
start = (u32)addr; \
|
||||
end = start + len; \
|
||||
start = (unsigned long)addr; \
|
||||
end = start + len; \
|
||||
start &= ~(line_size - 1); \
|
||||
end = ((end + line_size - 1) & ~(line_size - 1)); \
|
||||
\
|
||||
|
|
@ -74,7 +74,7 @@ static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
|
|||
}
|
||||
|
||||
/* packet must be a 4 byte boundary */
|
||||
if ((int)packet & 3) {
|
||||
if ((uintptr_t)packet & 3) {
|
||||
printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
|
||||
, __func__);
|
||||
ret = -EFAULT;
|
||||
|
|
@ -211,7 +211,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
|
|||
|
||||
/* Make sure we use a P2 address (non-cacheable) */
|
||||
port_info->tx_desc_base =
|
||||
(struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
|
||||
(struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
|
||||
port_info->tx_desc_cur = port_info->tx_desc_base;
|
||||
|
||||
/* Initialize all descriptors */
|
||||
|
|
@ -265,7 +265,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
|
|||
|
||||
/* Make sure we use a P2 address (non-cacheable) */
|
||||
port_info->rx_desc_base =
|
||||
(struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
|
||||
(struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
|
||||
|
||||
port_info->rx_desc_cur = port_info->rx_desc_base;
|
||||
|
||||
|
|
@ -281,7 +281,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
|
|||
goto err_buf_alloc;
|
||||
}
|
||||
|
||||
port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
|
||||
port_info->rx_buf_base = (u8 *)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
|
||||
|
||||
/* Initialize all descriptors */
|
||||
for (cur_rx_desc = port_info->rx_desc_base,
|
||||
|
|
@ -374,10 +374,16 @@ static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
|
|||
static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
|
||||
{
|
||||
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
||||
unsigned long edmr;
|
||||
|
||||
/* Configure e-dmac registers */
|
||||
sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
|
||||
(EMDR_DESC | EDMR_EL), EDMR);
|
||||
edmr = sh_eth_read(port_info, EDMR);
|
||||
edmr &= ~EMDR_DESC_R;
|
||||
edmr |= EMDR_DESC | EDMR_EL;
|
||||
#if defined(CONFIG_R8A77980)
|
||||
edmr |= EDMR_NBST;
|
||||
#endif
|
||||
sh_eth_write(port_info, edmr, EDMR);
|
||||
|
||||
sh_eth_write(port_info, 0, EESIPR);
|
||||
sh_eth_write(port_info, 0, TRSCER);
|
||||
|
|
@ -407,7 +413,7 @@ static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
|
|||
|
||||
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
|
||||
sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
|
||||
#elif defined(CONFIG_RCAR_GEN2)
|
||||
#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
|
||||
sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
|
||||
#endif
|
||||
}
|
||||
|
|
@ -426,7 +432,7 @@ static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
|
|||
sh_eth_write(port_info, GECMR_100B, GECMR);
|
||||
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
|
||||
sh_eth_write(port_info, 1, RTRATE);
|
||||
#elif defined(CONFIG_RCAR_GEN2)
|
||||
#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
|
||||
val = ECMR_RTM;
|
||||
#endif
|
||||
} else if (phy->speed == 10) {
|
||||
|
|
@ -694,7 +700,7 @@ static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
|
|||
struct sh_ether_priv *priv = dev_get_priv(dev);
|
||||
struct sh_eth_dev *eth = &priv->shdev;
|
||||
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
||||
uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
|
||||
uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
|
||||
int len;
|
||||
|
||||
len = sh_eth_recv_start(eth);
|
||||
|
|
@ -844,7 +850,7 @@ static int sh_ether_probe(struct udevice *udev)
|
|||
eth->port = CONFIG_SH_ETHER_USE_PORT;
|
||||
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
|
||||
eth->port_info[eth->port].iobase =
|
||||
(void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
|
||||
(void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
|
||||
|
||||
#if CONFIG_IS_ENABLED(CLK)
|
||||
ret = clk_enable(&priv->clk);
|
||||
|
|
@ -931,6 +937,7 @@ static const struct udevice_id sh_ether_ids[] = {
|
|||
{ .compatible = "renesas,ether-r8a7791" },
|
||||
{ .compatible = "renesas,ether-r8a7793" },
|
||||
{ .compatible = "renesas,ether-r8a7794" },
|
||||
{ .compatible = "renesas,gether-r8a77980" },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -15,20 +15,20 @@
|
|||
#if defined(CONFIG_SH)
|
||||
/* Malloc returns addresses in the P1 area (cacheable). However we need to
|
||||
use area P2 (non-cacheable) */
|
||||
#define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
|
||||
#define ADDR_TO_P2(addr) ((((uintptr_t)(addr) & ~0xe0000000) | 0xa0000000))
|
||||
|
||||
/* The ethernet controller needs to use physical addresses */
|
||||
#if defined(CONFIG_SH_32BIT)
|
||||
#define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000))
|
||||
#define ADDR_TO_PHY(addr) ((((uintptr_t)(addr) & ~0xe0000000) | 0x40000000))
|
||||
#else
|
||||
#define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
|
||||
#define ADDR_TO_PHY(addr) ((uintptr_t)(addr) & ~0xe0000000)
|
||||
#endif
|
||||
#elif defined(CONFIG_ARM)
|
||||
#ifndef inl
|
||||
#define inl readl
|
||||
#define outl writel
|
||||
#endif
|
||||
#define ADDR_TO_PHY(addr) ((int)(addr))
|
||||
#define ADDR_TO_PHY(addr) ((uintptr_t)(addr))
|
||||
#define ADDR_TO_P2(addr) (addr)
|
||||
#endif /* defined(CONFIG_SH) */
|
||||
|
||||
|
|
@ -358,6 +358,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
|
|||
#elif defined(CONFIG_R7S72100)
|
||||
#define SH_ETH_TYPE_RZ
|
||||
#define BASE_IO_ADDR 0xE8203000
|
||||
#elif defined(CONFIG_R8A77980)
|
||||
#define SH_ETH_TYPE_GETHER
|
||||
#define BASE_IO_ADDR 0xE7400000
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -374,6 +377,7 @@ enum EDSR_BIT {
|
|||
|
||||
/* EDMR */
|
||||
enum DMAC_M_BIT {
|
||||
EDMR_NBST = 0x80, /* DMA transfer burst mode */
|
||||
EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
|
||||
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
|
||||
EDMR_SRST = 0x03, /* Receive/Send reset */
|
||||
|
|
@ -563,7 +567,7 @@ enum FELIC_MODE_BIT {
|
|||
ECMR_PRM = 0x00000001,
|
||||
#ifdef CONFIG_CPU_SH7724
|
||||
ECMR_RTM = 0x00000010,
|
||||
#elif defined(CONFIG_RCAR_GEN2)
|
||||
#elif defined(CONFIG_RCAR_GEN2) || defined (CONFIG_R8A77980)
|
||||
ECMR_RTM = 0x00000004,
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -97,6 +97,16 @@ config PINCTRL_PFC_R8A77970
|
|||
the GPIO definitions and pin control functions for each available
|
||||
multiplex function.
|
||||
|
||||
config PINCTRL_PFC_R8A77980
|
||||
bool "Renesas RCar Gen3 R8A77980 pin control driver"
|
||||
depends on PINCTRL_PFC
|
||||
help
|
||||
Support pin multiplexing control on Renesas RCar Gen3 R8A77980 SoCs.
|
||||
|
||||
The driver is controlled by a device tree node which contains both
|
||||
the GPIO definitions and pin control functions for each available
|
||||
multiplex function.
|
||||
|
||||
config PINCTRL_PFC_R8A77990
|
||||
bool "Renesas RCar Gen3 R8A77990 pin control driver"
|
||||
depends on PINCTRL_PFC
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
|
|||
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o
|
||||
|
|
|
|||
2897
drivers/pinctrl/renesas/pfc-r8a77980.c
Normal file
2897
drivers/pinctrl/renesas/pfc-r8a77980.c
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -30,6 +30,7 @@ enum sh_pfc_model {
|
|||
SH_PFC_R8A7796,
|
||||
SH_PFC_R8A77965,
|
||||
SH_PFC_R8A77970,
|
||||
SH_PFC_R8A77980,
|
||||
SH_PFC_R8A77990,
|
||||
SH_PFC_R8A77995,
|
||||
};
|
||||
|
|
@ -856,6 +857,10 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev)
|
|||
if (model == SH_PFC_R8A77970)
|
||||
priv->pfc.info = &r8a77970_pinmux_info;
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77980
|
||||
if (model == SH_PFC_R8A77980)
|
||||
priv->pfc.info = &r8a77980_pinmux_info;
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
||||
if (model == SH_PFC_R8A77990)
|
||||
priv->pfc.info = &r8a77990_pinmux_info;
|
||||
|
|
@ -927,6 +932,12 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = {
|
|||
.data = SH_PFC_R8A77970,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77980
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a77980",
|
||||
.data = SH_PFC_R8A77980,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77990
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a77990",
|
||||
|
|
|
|||
|
|
@ -302,6 +302,7 @@ extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
|
|||
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
||||
|
||||
|
|
|
|||
41
include/configs/condor.h
Normal file
41
include/configs/condor.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* include/configs/condor.h
|
||||
* This file is Condor board configuration.
|
||||
*
|
||||
* Copyright (C) 2019 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#ifndef __CONDOR_H
|
||||
#define __CONDOR_H
|
||||
|
||||
#include "rcar-gen3-common.h"
|
||||
|
||||
/* Ethernet RAVB */
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
/* Environment compatibility */
|
||||
#undef CONFIG_ENV_SIZE_REDUND
|
||||
#undef CONFIG_ENV_SECT_SIZE
|
||||
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
|
||||
#define CONFIG_ENV_OFFSET 0x700000
|
||||
|
||||
/* SH Ether */
|
||||
#define CONFIG_SH_ETHER_USE_PORT 0
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
|
||||
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
|
||||
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
|
||||
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
|
||||
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
/* Board Clock */
|
||||
/* XTAL_CLK : 33.33MHz */
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333u
|
||||
|
||||
/* Generic Timer Definitions (use in assembler source) */
|
||||
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
|
||||
|
||||
#endif /* __CONDOR_H */
|
||||
51
include/dt-bindings/clock/r8a77980-cpg-mssr.h
Normal file
51
include/dt-bindings/clock/r8a77980-cpg-mssr.h
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2018 Cogent Embedded, Inc.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a77980 CPG Core Clocks */
|
||||
#define R8A77980_CLK_Z2 0
|
||||
#define R8A77980_CLK_ZR 1
|
||||
#define R8A77980_CLK_ZTR 2
|
||||
#define R8A77980_CLK_ZTRD2 3
|
||||
#define R8A77980_CLK_ZT 4
|
||||
#define R8A77980_CLK_ZX 5
|
||||
#define R8A77980_CLK_S0D1 6
|
||||
#define R8A77980_CLK_S0D2 7
|
||||
#define R8A77980_CLK_S0D3 8
|
||||
#define R8A77980_CLK_S0D4 9
|
||||
#define R8A77980_CLK_S0D6 10
|
||||
#define R8A77980_CLK_S0D12 11
|
||||
#define R8A77980_CLK_S0D24 12
|
||||
#define R8A77980_CLK_S1D1 13
|
||||
#define R8A77980_CLK_S1D2 14
|
||||
#define R8A77980_CLK_S1D4 15
|
||||
#define R8A77980_CLK_S2D1 16
|
||||
#define R8A77980_CLK_S2D2 17
|
||||
#define R8A77980_CLK_S2D4 18
|
||||
#define R8A77980_CLK_S3D1 19
|
||||
#define R8A77980_CLK_S3D2 20
|
||||
#define R8A77980_CLK_S3D4 21
|
||||
#define R8A77980_CLK_LB 22
|
||||
#define R8A77980_CLK_CL 23
|
||||
#define R8A77980_CLK_ZB3 24
|
||||
#define R8A77980_CLK_ZB3D2 25
|
||||
#define R8A77980_CLK_ZB3D4 26
|
||||
#define R8A77980_CLK_SD0H 27
|
||||
#define R8A77980_CLK_SD0 28
|
||||
#define R8A77980_CLK_RPC 29
|
||||
#define R8A77980_CLK_RPCD2 30
|
||||
#define R8A77980_CLK_MSO 31
|
||||
#define R8A77980_CLK_CANFD 32
|
||||
#define R8A77980_CLK_CSI0 33
|
||||
#define R8A77980_CLK_CP 34
|
||||
#define R8A77980_CLK_CPEX 35
|
||||
#define R8A77980_CLK_R 36
|
||||
#define R8A77980_CLK_OSC 37
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */
|
||||
43
include/dt-bindings/power/r8a77980-sysc.h
Normal file
43
include/dt-bindings/power/r8a77980-sysc.h
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2018 Cogent Embedded, Inc.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A77980_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A77980_PD_A2SC2 0
|
||||
#define R8A77980_PD_A2SC3 1
|
||||
#define R8A77980_PD_A2SC4 2
|
||||
#define R8A77980_PD_A2DP0 3
|
||||
#define R8A77980_PD_A2DP1 4
|
||||
#define R8A77980_PD_CA53_CPU0 5
|
||||
#define R8A77980_PD_CA53_CPU1 6
|
||||
#define R8A77980_PD_CA53_CPU2 7
|
||||
#define R8A77980_PD_CA53_CPU3 8
|
||||
#define R8A77980_PD_A2CN 10
|
||||
#define R8A77980_PD_A3VIP0 11
|
||||
#define R8A77980_PD_A2IR5 12
|
||||
#define R8A77980_PD_CR7 13
|
||||
#define R8A77980_PD_A2IR4 15
|
||||
#define R8A77980_PD_CA53_SCU 21
|
||||
#define R8A77980_PD_A2IR0 23
|
||||
#define R8A77980_PD_A3IR 24
|
||||
#define R8A77980_PD_A3VIP1 25
|
||||
#define R8A77980_PD_A3VIP2 26
|
||||
#define R8A77980_PD_A2IR1 27
|
||||
#define R8A77980_PD_A2IR2 28
|
||||
#define R8A77980_PD_A2IR3 29
|
||||
#define R8A77980_PD_A2SC0 30
|
||||
#define R8A77980_PD_A2SC1 31
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A77980_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */
|
||||
Loading…
Reference in New Issue
Block a user