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https://github.com/brain-hackers/u-boot-brain
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ARM: renesas: Add R8A77980 V3H Condor board code
Add board code for the R8A77980 V3H Condor board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
57ede1a3d4
commit
3ebb91914f
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@ -645,6 +645,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
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r8a77965-m3nulcb-u-boot.dtb \
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r8a77965-salvator-x-u-boot.dtb \
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r8a77970-eagle-u-boot.dtb \
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r8a77980-condor-u-boot.dtb \
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r8a77990-ebisu-u-boot.dtb \
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r8a77995-draak-u-boot.dtb
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34
arch/arm/dts/r8a77980-condor-u-boot.dts
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34
arch/arm/dts/r8a77980-condor-u-boot.dts
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@ -0,0 +1,34 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source extras for U-Boot for the Condor board
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*
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* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
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*/
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#include "r8a77980-condor.dts"
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#include "r8a77980-u-boot.dtsi"
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/ {
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aliases {
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spi0 = &rpc;
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};
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};
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&rpc {
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num-cs = <1>;
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status = "okay";
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spi-max-frequency = <50000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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flash0: spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "s25fs512s", "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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reg = <0>;
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status = "okay";
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};
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};
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292
arch/arm/dts/r8a77980-condor.dts
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292
arch/arm/dts/r8a77980-condor.dts
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@ -0,0 +1,292 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the Condor board
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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* Copyright (C) 2018 Cogent Embedded, Inc.
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*/
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/dts-v1/;
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#include "r8a77980.dtsi"
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/ {
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model = "Renesas Condor board based on r8a77980";
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compatible = "renesas,condor", "renesas,r8a77980";
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aliases {
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serial0 = &scif0;
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ethernet0 = &gether;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0 0x48000000 0 0x78000000>;
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};
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d3_3v: regulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "D3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vddq_vin01: regulator-1 {
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compatible = "regulator-fixed";
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regulator-name = "VDDQ_VIN01";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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d1_8v: regulator-2 {
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compatible = "regulator-fixed";
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regulator-name = "D1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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hdmi-out {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_con: endpoint {
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remote-endpoint = <&adv7511_out>;
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};
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};
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};
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lvds-decoder {
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compatible = "thine,thc63lvd1024";
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vcc-supply = <&d3_3v>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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thc63lvd1024_in: endpoint {
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remote-endpoint = <&lvds0_out>;
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};
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};
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port@2 {
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reg = <2>;
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thc63lvd1024_out: endpoint {
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remote-endpoint = <&adv7511_in>;
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};
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};
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};
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};
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x1_clk: x1-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <148500000>;
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};
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};
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&canfd {
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pinctrl-0 = <&canfd0_pins>;
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pinctrl-names = "default";
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status = "okay";
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channel0 {
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status = "okay";
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};
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};
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&du {
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clocks = <&cpg CPG_MOD 724>,
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<&x1_clk>;
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clock-names = "du.0", "dclkin.0";
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status = "okay";
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};
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&extal_clk {
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clock-frequency = <16666666>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&gether {
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pinctrl-0 = <&gether_pins>;
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pinctrl-names = "default";
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phy-mode = "rgmii-id";
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phy-handle = <&phy0>;
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renesas,no-ether-link;
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status = "okay";
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phy0: ethernet-phy@0 {
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rxc-skew-ps = <1500>;
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reg = <0>;
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interrupt-parent = <&gpio4>;
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interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "okay";
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clock-frequency = <400000>;
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io_expander0: gpio@20 {
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compatible = "onnn,pca9654";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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io_expander1: gpio@21 {
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compatible = "onnn,pca9654";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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hdmi@39 {
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compatible = "adi,adv7511w";
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reg = <0x39>;
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interrupt-parent = <&gpio1>;
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interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
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avdd-supply = <&d1_8v>;
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dvdd-supply = <&d1_8v>;
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pvdd-supply = <&d1_8v>;
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bgvdd-supply = <&d1_8v>;
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dvdd-3v-supply = <&d3_3v>;
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adi,input-depth = <8>;
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adi,input-colorspace = "rgb";
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adi,input-clock = "1x";
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adi,input-style = <1>;
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adi,input-justification = "evenly";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7511_in: endpoint {
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remote-endpoint = <&thc63lvd1024_out>;
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};
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};
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port@1 {
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reg = <1>;
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adv7511_out: endpoint {
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remote-endpoint = <&hdmi_con>;
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};
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};
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};
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};
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};
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&lvds0 {
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status = "okay";
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ports {
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port@1 {
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lvds0_out: endpoint {
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remote-endpoint = <&thc63lvd1024_in>;
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};
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};
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};
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};
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&mmc0 {
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pinctrl-0 = <&mmc_pins>;
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pinctrl-1 = <&mmc_pins_uhs>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <&d3_3v>;
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vqmmc-supply = <&vddq_vin01>;
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mmc-hs200-1_8v;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&pciec {
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status = "okay";
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};
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&pcie_bus_clk {
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clock-frequency = <100000000>;
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};
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&pcie_phy {
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status = "okay";
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};
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&pfc {
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canfd0_pins: canfd0 {
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groups = "canfd0_data_a";
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function = "canfd0";
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};
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gether_pins: gether {
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groups = "gether_mdio_a", "gether_rgmii",
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"gether_txcrefclk", "gether_txcrefclk_mega";
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function = "gether";
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};
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i2c0_pins: i2c0 {
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groups = "i2c0";
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function = "i2c0";
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};
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mmc_pins: mmc {
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groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
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function = "mmc";
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power-source = <3300>;
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};
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mmc_pins_uhs: mmc_uhs {
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groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
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function = "mmc";
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power-source = <1800>;
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};
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scif0_pins: scif0 {
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groups = "scif0_data";
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function = "scif0";
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};
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scif_clk_pins: scif_clk {
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groups = "scif_clk_b";
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function = "scif_clk";
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};
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};
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&rwdt {
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timeout-sec = <60>;
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status = "okay";
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};
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&scif0 {
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pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&scif_clk {
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clock-frequency = <14745600>;
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};
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@ -43,6 +43,12 @@ choice
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prompt "Renesas ARM64 SoCs board select"
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optional
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config TARGET_CONDOR
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bool "Condor board"
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imply R8A77980
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help
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Support for Renesas R-Car Gen3 Condor platform
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config TARGET_DRAAK
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bool "Draak board"
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imply R8A77995
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@ -88,6 +94,7 @@ endchoice
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config SYS_SOC
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default "rmobile"
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source "board/renesas/condor/Kconfig"
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source "board/renesas/draak/Kconfig"
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source "board/renesas/eagle/Kconfig"
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source "board/renesas/ebisu/Kconfig"
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15
board/renesas/condor/Kconfig
Normal file
15
board/renesas/condor/Kconfig
Normal file
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@ -0,0 +1,15 @@
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if TARGET_CONDOR
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config SYS_SOC
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default "rmobile"
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config SYS_BOARD
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default "condor"
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config SYS_VENDOR
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default "renesas"
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config SYS_CONFIG_NAME
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default "condor"
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endif
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6
board/renesas/condor/MAINTAINERS
Normal file
6
board/renesas/condor/MAINTAINERS
Normal file
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@ -0,0 +1,6 @@
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CONDOR BOARD
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M: Marek Vasut <marek.vasut+renesas@gmail.com>
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S: Maintained
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F: board/renesas/condor/
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F: include/configs/condor.h
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F: configs/r8a77980_condor_defconfig
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13
board/renesas/condor/Makefile
Normal file
13
board/renesas/condor/Makefile
Normal file
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@ -0,0 +1,13 @@
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#
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# board/renesas/condor/Makefile
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#
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# Copyright (C) 2019 Renesas Electronics Corporation
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD
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obj-y := ../rcar-common/gen3-spl.o
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else
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obj-y := condor.o ../rcar-common/common.o
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endif
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55
board/renesas/condor/condor.c
Normal file
55
board/renesas/condor/condor.c
Normal file
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@ -0,0 +1,55 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* board/renesas/condor/condor.c
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* This file is Condor board support.
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*
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* Copyright (C) 2019 Marek Vasut <marek.vasut+renesas@gmail.com>
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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void s_init(void)
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{
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}
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int board_early_init_f(void)
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{
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
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return 0;
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}
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#define RST_BASE 0xE6160000
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#define RST_CA57RESCNT (RST_BASE + 0x40)
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#define RST_CA53RESCNT (RST_BASE + 0x44)
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#define RST_RSTOUTCR (RST_BASE + 0x58)
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#define RST_CA57_CODE 0xA5A5000F
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#define RST_CA53_CODE 0x5A5A000F
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void reset_cpu(ulong addr)
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{
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unsigned long midr, cputype;
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asm volatile("mrs %0, midr_el1" : "=r" (midr));
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cputype = (midr >> 4) & 0xfff;
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if (cputype == 0xd03)
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writel(RST_CA53_CODE, RST_CA53RESCNT);
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else if (cputype == 0xd07)
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writel(RST_CA57_CODE, RST_CA57RESCNT);
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else
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hang();
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}
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69
configs/r8a77980_condor_defconfig
Normal file
69
configs/r8a77980_condor_defconfig
Normal file
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@ -0,0 +1,69 @@
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CONFIG_ARM=y
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CONFIG_ARCH_RMOBILE=y
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CONFIG_SYS_TEXT_BASE=0x50000000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_RCAR_GEN3=y
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CONFIG_TARGET_CONDOR=y
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CONFIG_SMBIOS_PRODUCT_NAME=""
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CONFIG_FIT=y
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
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CONFIG_SUPPORT_RAW_INITRD=y
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CONFIG_DEFAULT_FDT_FILE="r8a77980-condor.dtb"
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CONFIG_VERSION_VARIABLE=y
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CONFIG_SPL_TEXT_BASE=0xe6318000
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_DFU=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_OF_CONTROL=y
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CONFIG_DEFAULT_DEVICE_TREE="r8a77980-condor-u-boot"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_BLK=y
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CONFIG_CLK=y
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CONFIG_CLK_RENESAS=y
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CONFIG_DFU_TFTP=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_DFU_SF=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_RCAR_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_IIC=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_SH_ETHER=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_RENESAS_RPC_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SMBIOS_MANUFACTURER=""
|
||||
41
include/configs/condor.h
Normal file
41
include/configs/condor.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* include/configs/condor.h
|
||||
* This file is Condor board configuration.
|
||||
*
|
||||
* Copyright (C) 2019 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#ifndef __CONDOR_H
|
||||
#define __CONDOR_H
|
||||
|
||||
#include "rcar-gen3-common.h"
|
||||
|
||||
/* Ethernet RAVB */
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
/* Environment compatibility */
|
||||
#undef CONFIG_ENV_SIZE_REDUND
|
||||
#undef CONFIG_ENV_SECT_SIZE
|
||||
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
|
||||
#define CONFIG_ENV_OFFSET 0x700000
|
||||
|
||||
/* SH Ether */
|
||||
#define CONFIG_SH_ETHER_USE_PORT 0
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
|
||||
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
|
||||
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
|
||||
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
|
||||
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
/* Board Clock */
|
||||
/* XTAL_CLK : 33.33MHz */
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333u
|
||||
|
||||
/* Generic Timer Definitions (use in assembler source) */
|
||||
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
|
||||
|
||||
#endif /* __CONDOR_H */
|
||||
Loading…
Reference in New Issue
Block a user