MSCC: add board support for the Luton based evaluation board
Adding the support for the Luton boards PCB91 which share common code with the Ocelots boards, including board code, device tree and configuration. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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@ -518,6 +518,7 @@ M: Lars Povlsen <lars.povlsen@microchip.com>
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M: Horatiu Vultur <horatiu.vultur@microchip.com>
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S: Maintained
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F: arch/mips/mach-mscc/
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F: arch/mips/dts/luton*
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F: arch/mips/dts/mscc*
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F: arch/mips/dts/ocelot*
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F: board/mscc/
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@ -0,0 +1,36 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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/dts-v1/;
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#include "mscc,luton.dtsi"
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/ {
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model = "Luton10 PCB091 Reference Board";
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compatible = "mscc,luton-pcb091", "mscc,luton";
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aliases {
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serial0 = &uart0;
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spi0 = &spi0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&uart0 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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spi-flash@0 {
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compatible = "spi-flash";
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spi-max-frequency = <18000000>; /* input clock */
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reg = <0>; /* CS0 */
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spi-cs-high;
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};
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};
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@ -0,0 +1,87 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mscc,luton";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips24KEc";
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device_type = "cpu";
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reg = <0>;
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};
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};
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aliases {
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serial0 = &uart0;
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};
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ahb_clk: ahb-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <208333333>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x60000000 0x10200000>;
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uart0: serial@10100000 {
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pinctrl-0 = <&uart_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x10100000 0x20>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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gpio: pinctrl@70068 {
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compatible = "mscc,luton-pinctrl";
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reg = <0x70068 0x68>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 32>;
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uart_pins: uart-pins {
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pins = "GPIO_30", "GPIO_31";
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function = "uart";
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};
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};
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gpio_spi_bitbang: gpio@10000064 {
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compatible = "mscc,spi-bitbang-gpio";
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reg = <0x10000064 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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spi0: spi-bitbang {
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compatible = "spi-gpio";
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status = "okay";
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gpio-sck = <&gpio_spi_bitbang 6 0>;
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gpio-miso = <&gpio_spi_bitbang 0 0>;
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gpio-mosi = <&gpio_spi_bitbang 5 0>;
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cs-gpios = <&gpio_spi_bitbang 1 0>;
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num-chipselects = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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@ -81,4 +81,6 @@ endchoice
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source "board/mscc/ocelot/Kconfig"
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source "board/mscc/luton/Kconfig"
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endmenu
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@ -0,0 +1,14 @@
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# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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if SOC_LUTON
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config SYS_VENDOR
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default "mscc"
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config SYS_BOARD
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default "luton"
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config SYS_CONFIG_NAME
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default "luton"
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endif
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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obj-$(CONFIG_SOC_LUTON) := luton.o
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@ -0,0 +1,28 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <common.h>
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#include <asm/io.h>
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#define MSCC_GPIO_ALT0 0x88
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#define MSCC_GPIO_ALT1 0x8C
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DECLARE_GLOBAL_DATA_PTR;
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void board_debug_uart_init(void)
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{
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/* too early for the pinctrl driver, so configure the UART pins here */
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setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(30) | BIT(31));
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}
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int board_early_init_r(void)
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{
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/* Prepare SPI controller to be used in master mode */
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writel(0, BASE_CFG + ICPU_SW_MODE);
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/* Address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
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return 0;
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}
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@ -0,0 +1,64 @@
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CONFIG_MIPS=y
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CONFIG_SYS_TEXT_BASE=0x40000000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_DEBUG_UART_BOARD_INIT=y
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CONFIG_DEBUG_UART_BASE=0x70100000
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CONFIG_DEBUG_UART_CLOCK=208333333
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CONFIG_ARCH_MSCC=y
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CONFIG_TARGET_LUTON_PCB091=y
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CONFIG_DDRTYPE_MT47H128M8HQ=y
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CONFIG_SYS_LITTLE_ENDIAN=y
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CONFIG_MIPS_BOOT_FDT=y
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CONFIG_DEBUG_UART=y
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CONFIG_FIT=y
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CONFIG_BOOTDELAY=3
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyS0,115200"
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CONFIG_LOGLEVEL=7
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CONFIG_DISPLAY_CPUINFO=y
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CONFIG_SYS_PROMPT="pcb091 # "
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# CONFIG_CMD_BDI is not set
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# CONFIG_CMD_CONSOLE is not set
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# CONFIG_CMD_ELF is not set
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# CONFIG_CMD_EXPORTENV is not set
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# CONFIG_CMD_IMPORTENV is not set
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# CONFIG_CMD_CRC32 is not set
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CONFIG_CMD_MD5SUM=y
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_MEMTEST=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_DHCP=y
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# CONFIG_NET_TFTP_VARS is not set
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# CONFIG_CMD_NFS is not set
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CONFIG_CMD_PING=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
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CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m@1m(linux)"
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# CONFIG_ISO_PARTITION is not set
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CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_CLK=y
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CONFIG_DM_GPIO=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_SPI_FLASH_MTD=y
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CONFIG_DM_ETH=y
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CONFIG_PINCTRL=y
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CONFIG_PINCONF=y
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CONFIG_DM_SERIAL=y
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_SOFT_SPI=y
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CONFIG_LZMA=y
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