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https://github.com/brain-hackers/u-boot-brain
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f8c8cedd7a
Adding the support for the Luton boards PCB91 which share common code with the Ocelots boards, including board code, device tree and configuration. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
88 lines
1.5 KiB
Plaintext
88 lines
1.5 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mscc,luton";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips24KEc";
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device_type = "cpu";
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reg = <0>;
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};
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};
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aliases {
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serial0 = &uart0;
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};
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ahb_clk: ahb-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <208333333>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x60000000 0x10200000>;
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uart0: serial@10100000 {
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pinctrl-0 = <&uart_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x10100000 0x20>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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gpio: pinctrl@70068 {
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compatible = "mscc,luton-pinctrl";
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reg = <0x70068 0x68>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 32>;
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uart_pins: uart-pins {
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pins = "GPIO_30", "GPIO_31";
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function = "uart";
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};
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};
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gpio_spi_bitbang: gpio@10000064 {
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compatible = "mscc,spi-bitbang-gpio";
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reg = <0x10000064 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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spi0: spi-bitbang {
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compatible = "spi-gpio";
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status = "okay";
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gpio-sck = <&gpio_spi_bitbang 6 0>;
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gpio-miso = <&gpio_spi_bitbang 0 0>;
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gpio-mosi = <&gpio_spi_bitbang 5 0>;
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cs-gpios = <&gpio_spi_bitbang 1 0>;
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num-chipselects = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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