mmc: dwmmc: Change designware MMC 'clksel' callback function to return status
Change 'clksel' callback function to allow the code to return a status. This patch is a preparation for enabling Arm-Trusted-Firmware (ATF) in Intel SoC FPGA. This patch does not change functionality. When using Arm-Trusted-Firmware (ATF) in Intel SoC FPGA, the MMC clock related register is secure register which is required to be written via SMC/PCSI call. It is possible that U-Boot fail to write the register if there is unexpected error between U-Boot and ATF. As a result, there maybe signal integrity on MMC connection due to clock. So, the code should reports error to user when 'clksel' fail. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
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@ -40,7 +40,7 @@ struct ca_dwmmc_priv_data {
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u8 ds;
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u8 ds;
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};
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};
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static void ca_dwmci_clksel(struct dwmci_host *host)
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static int ca_dwmci_clksel(struct dwmci_host *host)
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{
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{
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struct ca_dwmmc_priv_data *priv = host->priv;
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struct ca_dwmmc_priv_data *priv = host->priv;
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u32 val = readl(priv->sd_dll_reg);
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u32 val = readl(priv->sd_dll_reg);
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@ -52,6 +52,8 @@ static void ca_dwmci_clksel(struct dwmci_host *host)
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val |= SD_CLK_SEL_100MHZ;
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val |= SD_CLK_SEL_100MHZ;
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writel(val, priv->sd_dll_reg);
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writel(val, priv->sd_dll_reg);
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return 0;
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}
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}
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static void ca_dwmci_board_init(struct dwmci_host *host)
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static void ca_dwmci_board_init(struct dwmci_host *host)
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@ -496,8 +496,13 @@ static int dwmci_set_ios(struct mmc *mmc)
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dwmci_writel(host, DWMCI_UHS_REG, regs);
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dwmci_writel(host, DWMCI_UHS_REG, regs);
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if (host->clksel)
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if (host->clksel) {
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host->clksel(host);
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int ret;
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ret = host->clksel(host);
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if (ret)
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return ret;
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}
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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if (mmc->vqmmc_supply) {
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if (mmc->vqmmc_supply) {
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@ -44,7 +44,7 @@ struct dwmci_exynos_priv_data {
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* Function used as callback function to initialise the
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* Function used as callback function to initialise the
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* CLKSEL register for every mmc channel.
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* CLKSEL register for every mmc channel.
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*/
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*/
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static void exynos_dwmci_clksel(struct dwmci_host *host)
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static int exynos_dwmci_clksel(struct dwmci_host *host)
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{
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{
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#ifdef CONFIG_DM_MMC
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#ifdef CONFIG_DM_MMC
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struct dwmci_exynos_priv_data *priv =
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struct dwmci_exynos_priv_data *priv =
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@ -53,6 +53,8 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
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struct dwmci_exynos_priv_data *priv = host->priv;
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struct dwmci_exynos_priv_data *priv = host->priv;
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#endif
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#endif
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dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
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dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
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return 0;
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}
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}
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unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
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unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
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@ -51,7 +51,7 @@ struct nexell_dwmmc_priv {
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struct clk *clk_get(const char *id);
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struct clk *clk_get(const char *id);
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static void nx_dw_mmc_clksel(struct dwmci_host *host)
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static int nx_dw_mmc_clksel(struct dwmci_host *host)
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{
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{
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/* host->priv is pointer to "struct udevice" */
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/* host->priv is pointer to "struct udevice" */
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struct nexell_dwmmc_priv *priv = dev_get_priv(host->priv);
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struct nexell_dwmmc_priv *priv = dev_get_priv(host->priv);
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@ -65,6 +65,8 @@ static void nx_dw_mmc_clksel(struct dwmci_host *host)
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DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(3);
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DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(3);
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dwmci_writel(host, DWMCI_CLKSEL, val);
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dwmci_writel(host, DWMCI_CLKSEL, val);
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return 0;
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}
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}
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static void nx_dw_mmc_reset(int ch)
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static void nx_dw_mmc_reset(int ch)
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@ -46,7 +46,7 @@ static void socfpga_dwmci_reset(struct udevice *dev)
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reset_deassert_bulk(&reset_bulk);
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reset_deassert_bulk(&reset_bulk);
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}
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}
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static void socfpga_dwmci_clksel(struct dwmci_host *host)
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static int socfpga_dwmci_clksel(struct dwmci_host *host)
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{
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{
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struct dwmci_socfpga_priv_data *priv = host->priv;
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struct dwmci_socfpga_priv_data *priv = host->priv;
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u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
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u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
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@ -66,6 +66,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
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/* Enable SDMMC clock */
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/* Enable SDMMC clock */
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setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
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setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
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CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
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CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
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return 0;
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}
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}
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static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
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static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
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@ -174,7 +174,7 @@ struct dwmci_host {
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struct mmc *mmc;
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struct mmc *mmc;
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void *priv;
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void *priv;
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void (*clksel)(struct dwmci_host *host);
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int (*clksel)(struct dwmci_host *host);
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void (*board_init)(struct dwmci_host *host);
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void (*board_init)(struct dwmci_host *host);
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/**
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/**
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