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https://github.com/brain-hackers/u-boot-brain
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Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
- ae350 related dts fixes.
This commit is contained in:
commit
7e585b5a61
52
arch/riscv/dts/ae350-u-boot.dtsi
Normal file
52
arch/riscv/dts/ae350-u-boot.dtsi
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@ -0,0 +1,52 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/ {
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cpus {
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u-boot,dm-spl;
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CPU0: cpu@0 {
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u-boot,dm-spl;
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CPU0_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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CPU1: cpu@1 {
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u-boot,dm-spl;
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CPU1_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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CPU2: cpu@2 {
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u-boot,dm-spl;
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CPU2_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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CPU3: cpu@3 {
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u-boot,dm-spl;
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CPU3_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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};
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memory@0 {
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u-boot,dm-spl;
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};
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soc {
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u-boot,dm-spl;
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plic1: interrupt-controller@e6400000 {
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u-boot,dm-spl;
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};
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plmt0@e6000000 {
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u-boot,dm-spl;
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};
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};
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serial0: serial@f0300000 {
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u-boot,dm-spl;
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};
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};
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@ -1,6 +1,9 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/dts-v1/;
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/dts-v1/;
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#include "binman.dtsi"
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#include "binman.dtsi"
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#include "ae350-u-boot.dtsi"
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/ {
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/ {
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#address-cells = <1>;
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#address-cells = <1>;
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@ -133,8 +136,7 @@
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plic0: interrupt-controller@e4000000 {
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plic0: interrupt-controller@e4000000 {
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compatible = "riscv,plic0";
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compatible = "riscv,plic0";
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#address-cells = <1>;
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#interrupt-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-controller;
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reg = <0xe4000000 0x2000000>;
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reg = <0xe4000000 0x2000000>;
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riscv,ndev=<71>;
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riscv,ndev=<71>;
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@ -146,7 +148,6 @@
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plic1: interrupt-controller@e6400000 {
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plic1: interrupt-controller@e6400000 {
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compatible = "riscv,plic1";
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compatible = "riscv,plic1";
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#address-cells = <1>;
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#interrupt-cells = <1>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-controller;
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reg = <0xe6400000 0x400000>;
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reg = <0xe6400000 0x400000>;
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@ -1,6 +1,9 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/dts-v1/;
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/dts-v1/;
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#include "binman.dtsi"
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#include "binman.dtsi"
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#include "ae350-u-boot.dtsi"
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/ {
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/ {
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#address-cells = <2>;
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#address-cells = <2>;
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@ -133,7 +136,6 @@
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plic0: interrupt-controller@e4000000 {
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plic0: interrupt-controller@e4000000 {
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compatible = "riscv,plic0";
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compatible = "riscv,plic0";
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#address-cells = <2>;
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#interrupt-cells = <2>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupt-controller;
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reg = <0x0 0xe4000000 0x0 0x2000000>;
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reg = <0x0 0xe4000000 0x0 0x2000000>;
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@ -146,7 +148,6 @@
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plic1: interrupt-controller@e6400000 {
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plic1: interrupt-controller@e6400000 {
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compatible = "riscv,plic1";
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compatible = "riscv,plic1";
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#address-cells = <2>;
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#interrupt-cells = <2>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupt-controller;
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reg = <0x0 0xe6400000 0x0 0x400000>;
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reg = <0x0 0xe6400000 0x0 0x400000>;
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@ -105,9 +105,11 @@ int riscv_clear_ipi(int hart)
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int riscv_get_ipi(int hart, int *pending)
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int riscv_get_ipi(int hart, int *pending)
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{
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{
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unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
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*pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
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*pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
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gd->arch.boot_hart));
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gd->arch.boot_hart));
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*pending = !!(*pending & SEND_IPI_TO_HART(hart));
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*pending = !!(*pending & ipi);
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return 0;
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return 0;
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}
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}
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@ -58,15 +58,6 @@ Platform Level Interrupt Controller (PLIC)
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- Configurable number of targets: 1-16
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- Configurable number of targets: 1-16
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- Preempted interrupt priority stack
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- Preempted interrupt priority stack
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Configurations
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--------------
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CONFIG_SKIP_LOWLEVEL_INIT:
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If you want to boot this system from SPI ROM and bypass e-bios (the
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other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
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in "include/configs/ax25-ae350.h".
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Build and boot steps
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Build and boot steps
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--------------------
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--------------------
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@ -89,12 +80,10 @@ Verification:
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Steps
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Steps
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-----
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-----
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1. Define CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is loaded via gdb from ram.
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1. Ping a server by mac driver
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2. Undefine CONFIG_SKIP_LOWLEVEL_INIT to build u-boot which is booted from spi rom.
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2. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver
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3. Ping a server by mac driver
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3. Burn this u-boot image to spi rom by spi driver
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4. Scan sd card and copy u-boot image which is booted from flash to ram by sd driver.
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4. Re-boot u-boot from spi flash with power off and power on
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5. Burn this u-boot image to spi rom by spi driver
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6. Re-boot u-boot from spi flash with power off and power on.
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Messages of U-Boot boot on AE350 board
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Messages of U-Boot boot on AE350 board
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--------------------------------------
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--------------------------------------
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