u-boot-brain/drivers/ddr/altera/Kconfig

config ALTERA_SDRAM
	bool "SoCFPGA DDR SDRAM driver"
	depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
	select RAM if TARGET_SOCFPGA_GEN5
	select SPL_RAM if TARGET_SOCFPGA_GEN5
	help
	  Enable DDR SDRAM controller for the SoCFPGA devices.
arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig Convert Altera DDR SDRAM driver to use Kconfig method. Enable ALTERA_SDRAM by default if it is on Gen5 target. Arria 10 will have different driver. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> 2017-04-05 18:32:51 +09:00			`config ALTERA_SDRAM`
			`bool "SoCFPGA DDR SDRAM driver"`
configs: Add DDR Kconfig support for Arria 10 This patch enables DDR Kconfig support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org> 2017-12-05 16:58:03 +09:00			`depends on TARGET_SOCFPGA_GEN5 \|\| TARGET_SOCFPGA_ARRIA10`
arm: socfpga: move gen5 SDR driver to DM To clean up reset handling for socfpga gen5, port the DDR driver to DM using UCLASS_RAM and implement proper reset handling. This gets us rid of one ad-hoc call to socfpga_per_reset(). The gen5 driver is implemented in 2 distinct files. One of it (containing the calibration training) is not touched much and is kept at using hard coded addresses since the code grows even more otherwise. SPL is changed from calling hard into the DDR driver code to just probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM driver after that. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> 2019-04-17 05:04:39 +09:00			`select RAM if TARGET_SOCFPGA_GEN5`
			`select SPL_RAM if TARGET_SOCFPGA_GEN5`
arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig Convert Altera DDR SDRAM driver to use Kconfig method. Enable ALTERA_SDRAM by default if it is on Gen5 target. Arria 10 will have different driver. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> 2017-04-05 18:32:51 +09:00			`help`
			`Enable DDR SDRAM controller for the SoCFPGA devices.`