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u-boot-brain/drivers/ddr/altera
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Ley Foon Tan 456d45261b ddr: altera: Stratix10: Add ECC memory scrubbing 
Scrub memory content if ECC is enabled and it is not
from warm reset boot.

Enable icache and dcache before scrub memory
and use "DC ZVA" instruction to clear memory
to zeros. This instruction writes a cache line
at a time and it can prevent false ECC error
trigger if write cache line partially.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-04-17 22:20:17 +02:00
..
Kconfig arm: socfpga: move gen5 SDR driver to DM 2019-04-17 22:20:16 +02:00
Makefile ddr: altera: stratix10: Add DDR support for Stratix10 SoC 2018-07-12 09:22:12 +02:00
sdram_arria10.c ddr: socfpga: Clean up ddr_setup() 2019-03-09 23:25:19 +01:00
sdram_gen5.c arm: socfpga: move gen5 SDR driver to DM 2019-04-17 22:20:16 +02:00
sdram_s10.c ddr: altera: Stratix10: Add ECC memory scrubbing 2019-04-17 22:20:17 +02:00
sequencer.c arm: socfpga: move gen5 SDR driver to DM 2019-04-17 22:20:16 +02:00
sequencer.h arm: socfpga: move gen5 SDR driver to DM 2019-04-17 22:20:16 +02:00