2018-05-10 10:28:29 +09:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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2018-12-03 10:26:49 +09:00
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#include "ddr_ml_wrapper.h"
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#include "mv_ddr_plat.h"
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2018-05-10 10:28:29 +09:00
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#include "mv_ddr_topology.h"
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#include "mv_ddr_common.h"
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#include "mv_ddr_spd.h"
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#include "ddr_topology_def.h"
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#include "ddr3_training_ip_db.h"
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#include "ddr3_training_ip.h"
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2018-12-03 10:26:49 +09:00
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#include "mv_ddr_training_db.h"
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2018-05-10 10:28:29 +09:00
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unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk)
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{
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unsigned int cl = ceil_div(taa_min, tclk);
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return mv_ddr_spd_supported_cl_get(cl);
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}
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unsigned int mv_ddr_cwl_calc(unsigned int tclk)
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{
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unsigned int cwl;
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if (tclk >= 1250)
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cwl = 9;
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else if (tclk >= 1071)
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cwl = 10;
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else if (tclk >= 938)
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cwl = 11;
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else if (tclk >= 833)
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cwl = 12;
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2018-12-03 10:26:49 +09:00
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else if (tclk >= 750)
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cwl = 14;
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else if (tclk >= 625)
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cwl = 16;
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2018-05-10 10:28:29 +09:00
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else
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cwl = 0;
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return cwl;
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}
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2018-12-03 10:26:49 +09:00
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int mv_ddr_topology_map_update(void)
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2018-05-10 10:28:29 +09:00
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{
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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2018-12-03 10:26:49 +09:00
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struct if_params *iface_params = &(tm->interface_params[0]);
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2018-05-10 10:28:29 +09:00
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unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
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2018-12-03 10:26:49 +09:00
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enum mv_ddr_speed_bin speed_bin_index;
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enum mv_ddr_freq freq = MV_DDR_FREQ_LAST;
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2018-05-10 10:28:29 +09:00
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unsigned int tclk;
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unsigned char val = 0;
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int i;
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2018-12-03 10:26:49 +09:00
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if (iface_params->memory_freq == MV_DDR_FREQ_SAR)
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iface_params->memory_freq = mv_ddr_init_freq_get();
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2018-05-10 10:28:29 +09:00
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if (tm->cfg_src == MV_DDR_CFG_SPD) {
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/* check dram device type */
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val = mv_ddr_spd_dev_type_get(&tm->spd_data);
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if (val != MV_DDR_SPD_DEV_TYPE_DDR4) {
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printf("mv_ddr: unsupported dram device type found\n");
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2018-12-03 10:26:49 +09:00
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return -1;
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2018-05-10 10:28:29 +09:00
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}
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/* update topology map with timing data */
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if (mv_ddr_spd_timing_calc(&tm->spd_data, tm->timing_data) > 0) {
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printf("mv_ddr: negative timing data found\n");
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2018-12-03 10:26:49 +09:00
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return -1;
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2018-05-10 10:28:29 +09:00
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}
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/* update device width in topology map */
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2018-12-03 10:26:49 +09:00
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iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data);
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2018-05-10 10:28:29 +09:00
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/* update die capacity in topology map */
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2018-12-03 10:26:49 +09:00
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iface_params->memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data);
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2018-05-10 10:28:29 +09:00
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/* update bus bit mask in topology map */
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tm->bus_act_mask = mv_ddr_bus_bit_mask_get();
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/* update cs bit mask in topology map */
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val = mv_ddr_spd_cs_bit_mask_get(&tm->spd_data);
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2018-12-03 10:26:49 +09:00
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for (i = 0; i < octets_per_if_num; i++)
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iface_params->as_bus_params[i].cs_bitmask = val;
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2018-05-10 10:28:29 +09:00
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/* check dram module type */
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val = mv_ddr_spd_module_type_get(&tm->spd_data);
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switch (val) {
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case MV_DDR_SPD_MODULE_TYPE_UDIMM:
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case MV_DDR_SPD_MODULE_TYPE_SO_DIMM:
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case MV_DDR_SPD_MODULE_TYPE_MINI_UDIMM:
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case MV_DDR_SPD_MODULE_TYPE_72BIT_SO_UDIMM:
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case MV_DDR_SPD_MODULE_TYPE_16BIT_SO_DIMM:
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case MV_DDR_SPD_MODULE_TYPE_32BIT_SO_DIMM:
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break;
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default:
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printf("mv_ddr: unsupported dram module type found\n");
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2018-12-03 10:26:49 +09:00
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return -1;
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2018-05-10 10:28:29 +09:00
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}
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/* update mirror bit mask in topology map */
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val = mv_ddr_spd_mem_mirror_get(&tm->spd_data);
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2018-12-03 10:26:49 +09:00
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for (i = 0; i < octets_per_if_num; i++)
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iface_params->as_bus_params[i].mirror_enable_bitmask = val << 1;
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2018-05-10 10:28:29 +09:00
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2018-12-03 10:26:49 +09:00
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tclk = 1000000 / mv_ddr_freq_get(iface_params->memory_freq);
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2018-05-10 10:28:29 +09:00
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/* update cas write latency (cwl) */
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val = mv_ddr_cwl_calc(tclk);
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if (val == 0) {
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printf("mv_ddr: unsupported cas write latency value found\n");
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2018-12-03 10:26:49 +09:00
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return -1;
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2018-05-10 10:28:29 +09:00
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}
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2018-12-03 10:26:49 +09:00
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iface_params->cas_wl = val;
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2018-05-10 10:28:29 +09:00
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/* update cas latency (cl) */
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mv_ddr_spd_supported_cls_calc(&tm->spd_data);
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val = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk);
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if (val == 0) {
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printf("mv_ddr: unsupported cas latency value found\n");
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2018-12-03 10:26:49 +09:00
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return -1;
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2018-05-10 10:28:29 +09:00
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}
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2018-12-03 10:26:49 +09:00
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iface_params->cas_l = val;
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2018-05-10 10:28:29 +09:00
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} else if (tm->cfg_src == MV_DDR_CFG_DEFAULT) {
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/* set cas and cas-write latencies per speed bin, if they unset */
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2018-12-03 10:26:49 +09:00
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speed_bin_index = iface_params->speed_bin_index;
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freq = iface_params->memory_freq;
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2018-05-10 10:28:29 +09:00
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2018-12-03 10:26:49 +09:00
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if (iface_params->cas_l == 0)
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iface_params->cas_l = mv_ddr_cl_val_get(speed_bin_index, freq);
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2018-05-10 10:28:29 +09:00
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2018-12-03 10:26:49 +09:00
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if (iface_params->cas_wl == 0)
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iface_params->cas_wl = mv_ddr_cwl_val_get(speed_bin_index, freq);
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2018-05-10 10:28:29 +09:00
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}
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2018-12-03 10:26:49 +09:00
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return 0;
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2018-05-10 10:28:29 +09:00
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}
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unsigned short mv_ddr_bus_bit_mask_get(void)
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{
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unsigned short pri_and_ext_bus_width = 0x0;
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
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if (tm->cfg_src == MV_DDR_CFG_SPD) {
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2021-02-20 01:11:11 +09:00
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if (tm->bus_act_mask == BUS_MASK_32BIT)
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tm->spd_data.byte_fields.byte_13.all_bits = MV_DDR_PRI_BUS_WIDTH_32;
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2018-05-10 10:28:29 +09:00
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enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data);
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enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data);
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switch (pri_bus_width) {
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case MV_DDR_PRI_BUS_WIDTH_16:
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pri_and_ext_bus_width = BUS_MASK_16BIT;
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break;
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2021-02-20 01:11:11 +09:00
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case MV_DDR_PRI_BUS_WIDTH_32: /*each bit represents byte, so 0xf-is means 4 bytes-32 bit*/
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2018-05-10 10:28:29 +09:00
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pri_and_ext_bus_width = BUS_MASK_32BIT;
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break;
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case MV_DDR_PRI_BUS_WIDTH_64:
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pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK;
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break;
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default:
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pri_and_ext_bus_width = 0x0;
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}
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if (bus_width_ext == MV_DDR_BUS_WIDTH_EXT_8)
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pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1);
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}
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return pri_and_ext_bus_width;
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}
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unsigned int mv_ddr_if_bus_width_get(void)
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{
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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unsigned int bus_width;
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switch (tm->bus_act_mask) {
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case BUS_MASK_16BIT:
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case BUS_MASK_16BIT_ECC:
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case BUS_MASK_16BIT_ECC_PUP3:
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bus_width = 16;
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break;
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case BUS_MASK_32BIT:
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case BUS_MASK_32BIT_ECC:
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case MV_DDR_32BIT_ECC_PUP8_BUS_MASK:
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bus_width = 32;
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break;
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case MV_DDR_64BIT_BUS_MASK:
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case MV_DDR_64BIT_ECC_PUP8_BUS_MASK:
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bus_width = 64;
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break;
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default:
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printf("mv_ddr: unsupported bus active mask parameter found\n");
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bus_width = 0;
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}
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return bus_width;
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}
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2018-12-03 10:26:49 +09:00
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unsigned int mv_ddr_cs_num_get(void)
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{
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unsigned int cs_num = 0;
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unsigned int cs, sphy;
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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struct if_params *iface_params = &(tm->interface_params[0]);
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unsigned int sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
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for (sphy = 0; sphy < sphy_max; sphy++) {
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VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sphy);
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break;
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}
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for (cs = 0; cs < MAX_CS_NUM; cs++) {
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VALIDATE_ACTIVE(iface_params->as_bus_params[sphy].cs_bitmask, cs);
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cs_num++;
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}
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return cs_num;
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}
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int mv_ddr_is_ecc_ena(void)
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{
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) ||
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DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask) ||
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DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask))
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return 1;
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else
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return 0;
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}
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2020-01-30 08:50:44 +09:00
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int mv_ddr_ck_delay_get(void)
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{
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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if (tm->ck_delay)
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return tm->ck_delay;
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return -1;
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}
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2018-12-03 10:26:49 +09:00
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/* translate topology map definition to real memory size in bits */
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static unsigned int mem_size[] = {
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ADDR_SIZE_512MB,
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ADDR_SIZE_1GB,
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ADDR_SIZE_2GB,
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ADDR_SIZE_4GB,
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ADDR_SIZE_8GB
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/* TODO: add capacity up to 256GB */
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};
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unsigned long long mv_ddr_mem_sz_per_cs_get(void)
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{
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unsigned long long mem_sz_per_cs;
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unsigned int i, sphys, sphys_per_dunit;
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unsigned int sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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struct if_params *iface_params = &(tm->interface_params[0]);
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/* calc number of active subphys excl. ecc one */
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for (i = 0, sphys = 0; i < sphy_max - 1; i++) {
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VALIDATE_BUS_ACTIVE(tm->bus_act_mask, i);
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sphys++;
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}
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/* calc number of subphys per ddr unit */
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if (iface_params->bus_width == MV_DDR_DEV_WIDTH_8BIT)
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sphys_per_dunit = MV_DDR_ONE_SPHY_PER_DUNIT;
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else if (iface_params->bus_width == MV_DDR_DEV_WIDTH_16BIT)
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sphys_per_dunit = MV_DDR_TWO_SPHY_PER_DUNIT;
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else {
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printf("mv_ddr: unsupported bus width type found\n");
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return 0;
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}
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/* calc dram size per cs */
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mem_sz_per_cs = (unsigned long long)mem_size[iface_params->memory_size] *
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(unsigned long long)sphys /
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(unsigned long long)sphys_per_dunit;
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return mem_sz_per_cs;
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}
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unsigned long long mv_ddr_mem_sz_get(void)
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{
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unsigned long long tot_mem_sz = 0;
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unsigned long long mem_sz_per_cs = 0;
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unsigned long long max_cs = mv_ddr_cs_num_get();
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mem_sz_per_cs = mv_ddr_mem_sz_per_cs_get();
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tot_mem_sz = max_cs * mem_sz_per_cs;
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return tot_mem_sz;
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}
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unsigned int mv_ddr_rtt_nom_get(void)
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{
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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unsigned int rtt_nom = tm->edata.mem_edata.rtt_nom;
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if (rtt_nom >= MV_DDR_RTT_NOM_PARK_RZQ_LAST) {
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printf("error: %s: unsupported rtt_nom parameter found\n", __func__);
|
|
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rtt_nom = PARAM_UNDEFINED;
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}
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|
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|
|
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return rtt_nom;
|
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|
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}
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unsigned int mv_ddr_rtt_park_get(void)
|
|
|
|
{
|
|
|
|
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
|
|
|
|
unsigned int cs_num = mv_ddr_cs_num_get();
|
|
|
|
unsigned int rtt_park = MV_DDR_RTT_NOM_PARK_RZQ_LAST;
|
|
|
|
|
|
|
|
if (cs_num > 0 && cs_num <= MAX_CS_NUM)
|
|
|
|
rtt_park = tm->edata.mem_edata.rtt_park[cs_num - 1];
|
|
|
|
|
|
|
|
if (rtt_park >= MV_DDR_RTT_NOM_PARK_RZQ_LAST) {
|
|
|
|
printf("error: %s: unsupported rtt_park parameter found\n", __func__);
|
|
|
|
rtt_park = PARAM_UNDEFINED;
|
|
|
|
}
|
|
|
|
|
|
|
|
return rtt_park;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned int mv_ddr_rtt_wr_get(void)
|
|
|
|
{
|
|
|
|
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
|
|
|
|
unsigned int cs_num = mv_ddr_cs_num_get();
|
|
|
|
unsigned int rtt_wr = MV_DDR_RTT_WR_RZQ_LAST;
|
|
|
|
|
|
|
|
if (cs_num > 0 && cs_num <= MAX_CS_NUM)
|
|
|
|
rtt_wr = tm->edata.mem_edata.rtt_wr[cs_num - 1];
|
|
|
|
|
|
|
|
if (rtt_wr >= MV_DDR_RTT_WR_RZQ_LAST) {
|
|
|
|
printf("error: %s: unsupported rtt_wr parameter found\n", __func__);
|
|
|
|
rtt_wr = PARAM_UNDEFINED;
|
|
|
|
}
|
|
|
|
|
|
|
|
return rtt_wr;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned int mv_ddr_dic_get(void)
|
|
|
|
{
|
|
|
|
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
|
|
|
|
unsigned int dic = tm->edata.mem_edata.dic;
|
|
|
|
|
|
|
|
if (dic >= MV_DDR_DIC_RZQ_LAST) {
|
|
|
|
printf("error: %s: unsupported dic parameter found\n", __func__);
|
|
|
|
dic = PARAM_UNDEFINED;
|
|
|
|
}
|
|
|
|
|
|
|
|
return dic;
|
|
|
|
}
|