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https://github.com/brain-hackers/u-boot-brain
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198 lines
5.3 KiB
C
198 lines
5.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#include "mv_ddr_topology.h"
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#include "mv_ddr_common.h"
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#include "mv_ddr_spd.h"
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#include "ddr3_init.h"
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#include "ddr_topology_def.h"
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#include "ddr3_training_ip_db.h"
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#include "ddr3_training_ip.h"
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unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk)
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{
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unsigned int cl = ceil_div(taa_min, tclk);
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return mv_ddr_spd_supported_cl_get(cl);
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}
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unsigned int mv_ddr_cwl_calc(unsigned int tclk)
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{
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unsigned int cwl;
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if (tclk >= 1250)
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cwl = 9;
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else if (tclk >= 1071)
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cwl = 10;
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else if (tclk >= 938)
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cwl = 11;
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else if (tclk >= 833)
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cwl = 12;
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else
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cwl = 0;
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return cwl;
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}
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struct mv_ddr_topology_map *mv_ddr_topology_map_update(void)
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{
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
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enum hws_speed_bin speed_bin_index;
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enum hws_ddr_freq freq = DDR_FREQ_LAST;
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unsigned int tclk;
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unsigned char val = 0;
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int i;
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if (tm->interface_params[0].memory_freq == DDR_FREQ_SAR)
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tm->interface_params[0].memory_freq = mv_ddr_init_freq_get();
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if (tm->cfg_src == MV_DDR_CFG_SPD) {
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/* check dram device type */
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val = mv_ddr_spd_dev_type_get(&tm->spd_data);
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if (val != MV_DDR_SPD_DEV_TYPE_DDR4) {
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printf("mv_ddr: unsupported dram device type found\n");
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return NULL;
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}
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/* update topology map with timing data */
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if (mv_ddr_spd_timing_calc(&tm->spd_data, tm->timing_data) > 0) {
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printf("mv_ddr: negative timing data found\n");
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return NULL;
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}
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/* update device width in topology map */
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tm->interface_params[0].bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data);
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/* update die capacity in topology map */
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tm->interface_params[0].memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data);
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/* update bus bit mask in topology map */
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tm->bus_act_mask = mv_ddr_bus_bit_mask_get();
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/* update cs bit mask in topology map */
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val = mv_ddr_spd_cs_bit_mask_get(&tm->spd_data);
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for (i = 0; i < octets_per_if_num; i++) {
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tm->interface_params[0].as_bus_params[i].cs_bitmask = val;
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}
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/* check dram module type */
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val = mv_ddr_spd_module_type_get(&tm->spd_data);
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switch (val) {
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case MV_DDR_SPD_MODULE_TYPE_UDIMM:
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case MV_DDR_SPD_MODULE_TYPE_SO_DIMM:
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case MV_DDR_SPD_MODULE_TYPE_MINI_UDIMM:
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case MV_DDR_SPD_MODULE_TYPE_72BIT_SO_UDIMM:
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case MV_DDR_SPD_MODULE_TYPE_16BIT_SO_DIMM:
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case MV_DDR_SPD_MODULE_TYPE_32BIT_SO_DIMM:
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break;
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default:
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printf("mv_ddr: unsupported dram module type found\n");
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return NULL;
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}
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/* update mirror bit mask in topology map */
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val = mv_ddr_spd_mem_mirror_get(&tm->spd_data);
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for (i = 0; i < octets_per_if_num; i++) {
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tm->interface_params[0].as_bus_params[i].mirror_enable_bitmask = val << 1;
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}
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tclk = 1000000 / freq_val[tm->interface_params[0].memory_freq];
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/* update cas write latency (cwl) */
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val = mv_ddr_cwl_calc(tclk);
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if (val == 0) {
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printf("mv_ddr: unsupported cas write latency value found\n");
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return NULL;
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}
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tm->interface_params[0].cas_wl = val;
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/* update cas latency (cl) */
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mv_ddr_spd_supported_cls_calc(&tm->spd_data);
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val = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk);
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if (val == 0) {
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printf("mv_ddr: unsupported cas latency value found\n");
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return NULL;
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}
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tm->interface_params[0].cas_l = val;
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} else if (tm->cfg_src == MV_DDR_CFG_DEFAULT) {
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/* set cas and cas-write latencies per speed bin, if they unset */
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speed_bin_index = tm->interface_params[0].speed_bin_index;
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freq = tm->interface_params[0].memory_freq;
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if (tm->interface_params[0].cas_l == 0)
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tm->interface_params[0].cas_l =
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cas_latency_table[speed_bin_index].cl_val[freq];
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if (tm->interface_params[0].cas_wl == 0)
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tm->interface_params[0].cas_wl =
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cas_write_latency_table[speed_bin_index].cl_val[freq];
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}
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return tm;
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}
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unsigned short mv_ddr_bus_bit_mask_get(void)
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{
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unsigned short pri_and_ext_bus_width = 0x0;
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
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if (tm->cfg_src == MV_DDR_CFG_SPD) {
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enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data);
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enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data);
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switch (pri_bus_width) {
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case MV_DDR_PRI_BUS_WIDTH_16:
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pri_and_ext_bus_width = BUS_MASK_16BIT;
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break;
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case MV_DDR_PRI_BUS_WIDTH_32:
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pri_and_ext_bus_width = BUS_MASK_32BIT;
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break;
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case MV_DDR_PRI_BUS_WIDTH_64:
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pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK;
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break;
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default:
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pri_and_ext_bus_width = 0x0;
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}
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if (bus_width_ext == MV_DDR_BUS_WIDTH_EXT_8)
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pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1);
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}
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return pri_and_ext_bus_width;
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}
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unsigned int mv_ddr_if_bus_width_get(void)
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{
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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unsigned int bus_width;
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switch (tm->bus_act_mask) {
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case BUS_MASK_16BIT:
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case BUS_MASK_16BIT_ECC:
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case BUS_MASK_16BIT_ECC_PUP3:
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bus_width = 16;
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break;
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case BUS_MASK_32BIT:
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case BUS_MASK_32BIT_ECC:
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case MV_DDR_32BIT_ECC_PUP8_BUS_MASK:
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bus_width = 32;
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break;
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case MV_DDR_64BIT_BUS_MASK:
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case MV_DDR_64BIT_ECC_PUP8_BUS_MASK:
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bus_width = 64;
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break;
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default:
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printf("mv_ddr: unsupported bus active mask parameter found\n");
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bus_width = 0;
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}
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return bus_width;
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}
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