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ddr: marvell: a38x: add ddr32 support
commit 32800667b375ebd1f82120da0f3479b1cf52d96d upstream. Required changes made for 32bit ddr support. An update is made to the topology map, according to bus_act_mask, set in the dram_port.c Signed-off-by: Alex Leibovich <alexl@marvell.com> Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com> Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
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@ -144,6 +144,9 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
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unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
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if (tm->cfg_src == MV_DDR_CFG_SPD) {
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if (tm->bus_act_mask == BUS_MASK_32BIT)
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tm->spd_data.byte_fields.byte_13.all_bits = MV_DDR_PRI_BUS_WIDTH_32;
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enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data);
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enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data);
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@ -151,7 +154,7 @@ unsigned short mv_ddr_bus_bit_mask_get(void)
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case MV_DDR_PRI_BUS_WIDTH_16:
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pri_and_ext_bus_width = BUS_MASK_16BIT;
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break;
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case MV_DDR_PRI_BUS_WIDTH_32:
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case MV_DDR_PRI_BUS_WIDTH_32: /*each bit represents byte, so 0xf-is means 4 bytes-32 bit*/
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pri_and_ext_bus_width = BUS_MASK_32BIT;
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break;
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case MV_DDR_PRI_BUS_WIDTH_64:
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