2018-05-07 06:58:06 +09:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2014-10-22 19:13:18 +09:00
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/*
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2015-12-03 20:39:45 +09:00
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* Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
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2014-10-22 19:13:18 +09:00
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*/
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#ifndef _CONFIG_DB_MV7846MP_GP_H
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#define _CONFIG_DB_MV7846MP_GP_H
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/*
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* High Level Configuration Options (easy to change)
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*/
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2015-01-19 19:33:46 +09:00
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#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
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2015-08-06 21:27:36 +09:00
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/*
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* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
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* for DDR ECC byte filling in the SPL before loading the main
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* U-Boot into it.
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*/
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2014-10-22 19:13:18 +09:00
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#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MVTWSI
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2015-04-11 06:09:51 +09:00
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#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
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2014-10-22 19:13:18 +09:00
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#define CONFIG_SYS_I2C_SLAVE 0x0
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#define CONFIG_SYS_I2C_SPEED 100000
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2015-07-23 01:05:43 +09:00
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/* USB/EHCI configuration */
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#define CONFIG_EHCI_IS_TDI
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2015-07-23 22:02:09 +09:00
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
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2015-07-23 01:05:43 +09:00
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2014-10-22 19:13:18 +09:00
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/* Environment in SPI NOR flash */
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#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
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#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
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#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
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#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
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2015-07-15 21:50:05 +09:00
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/* SATA support */
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2015-12-03 20:39:45 +09:00
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#define CONFIG_SYS_SATA_MAX_DEVICE 2
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#define CONFIG_LBA48
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2015-07-15 21:50:05 +09:00
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2015-08-11 16:36:15 +09:00
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/* PCIe support */
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2015-11-25 15:37:00 +09:00
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#ifndef CONFIG_SPL_BUILD
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2015-08-11 16:36:15 +09:00
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#define CONFIG_PCI_SCAN_SHOW
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2015-11-25 15:37:00 +09:00
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#endif
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2015-08-11 16:36:15 +09:00
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2015-07-23 17:26:18 +09:00
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/* NAND */
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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2014-10-22 19:13:18 +09:00
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/*
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* mv-common.h should be defined after CMD configs since it used them
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* to enable certain macros
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*/
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#include "mv-common.h"
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2015-01-19 19:33:46 +09:00
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/*
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* Memory layout while starting into the bin_hdr via the
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* BootROM:
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*
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* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
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* 0x4000.4030 bin_hdr start address
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* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
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* 0x4007.fffc BootROM stack top
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*
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* The address space between 0x4007.fffc and 0x400f.fff is not locked in
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* L2 cache thus cannot be used.
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*/
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/* SPL */
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/* Defines for SPL */
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#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
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#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
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2015-11-25 15:37:00 +09:00
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MALLOC_SIMPLE
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#endif
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2015-01-19 19:33:46 +09:00
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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/* SPL related SPI defines */
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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2015-08-03 19:13:09 +09:00
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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2015-01-19 19:33:46 +09:00
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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#define CONFIG_SPD_EEPROM 0x4e
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2015-12-10 23:02:38 +09:00
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#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
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2015-01-19 19:33:46 +09:00
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2014-10-22 19:13:18 +09:00
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#endif /* _CONFIG_DB_MV7846MP_GP_H */
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