brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

arm: mvebu: Move CONFIG_SYS_TEXT_BASE to an address < 16 MiB

Browse Source 
This patch moves CONFIG_SYS_TEXT_BASE to 0x00800000 for all Armada
XP / 38x boards in mainline U-Boot. This is done in preparation for
the ECC SDRAM scrubbing that needs to be done in the main U-Boot.
The SPL (previously bin_hdr) has already scrubbed the area:
  0x0000.0000 - 0x0100.0000

In this area this main U-Boot needs to get loaded. The main U-Boot
then can scrub the remaining SDRAM area while running from this
location.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This commit is contained in:
Stefan Roese 2015-08-06 14:27:36 +02:00 committed by Luka Perkov
parent 8a83c65f57
commit 2923c2d2fe
3 changed files with 18 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
include/configs/db-88f6820-gp.h
View File

@ -20,7 +20,12 @@
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_SYS_TEXT_BASE 0x04000000
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TEXT_BASE 0x00800000
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/*

7
include/configs/db-mv784mp-gp.h
View File

@ -17,7 +17,12 @@
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_SYS_TEXT_BASE 0x04000000
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TEXT_BASE 0x00800000
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/*

7
include/configs/maxbcm.h
View File

@ -15,7 +15,12 @@
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_SYS_TEXT_BASE 0x04000000
/*
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TEXT_BASE 0x00800000
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/*