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u-boot-brain/drivers/ram/k3-ddrss/lpddr4_structs_if.h

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ram: k3-j721e: Add support for J721E DDR controller The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-07 22:56:36 +09:00
/* SPDX-License-Identifier: BSD-3-Clause */
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 00:22:11 +09:00
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
ram: k3-j721e: Add support for J721E DDR controller The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-07 22:56:36 +09:00
*/
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 00:22:11 +09:00
ram: k3-j721e: Add support for J721E DDR controller The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-07 22:56:36 +09:00
#ifndef LPDDR4_STRUCTS_IF_H
#define LPDDR4_STRUCTS_IF_H
#include <linux/types.h>
#include "lpddr4_if.h"
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 00:22:11 +09:00
struct lpddr4_config_s {
struct lpddr4_ctlregs_s *ctlbase;
ram: k3-j721e: Add support for J721E DDR controller The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-07 22:56:36 +09:00
lpddr4_infocallback infohandler;
lpddr4_ctlcallback ctlinterrupthandler;
lpddr4_phyindepcallback phyindepinterrupthandler;
};
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 00:22:11 +09:00
struct lpddr4_privatedata_s {
struct lpddr4_ctlregs_s *ctlbase;
ram: k3-j721e: Add support for J721E DDR controller The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-07 22:56:36 +09:00
lpddr4_infocallback infohandler;
lpddr4_ctlcallback ctlinterrupthandler;
lpddr4_phyindepcallback phyindepinterrupthandler;
};
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 00:22:11 +09:00
struct lpddr4_debuginfo_s {
u8 pllerror;
u8 iocaliberror;
u8 rxoffseterror;
u8 catraingerror;
u8 wrlvlerror;
u8 gatelvlerror;
u8 readlvlerror;
u8 dqtrainingerror;
ram: k3-j721e: Add support for J721E DDR controller The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-07 22:56:36 +09:00
};
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 00:22:11 +09:00
struct lpddr4_fspmoderegs_s {
u8 mr1data_fn[LPDDR4_INTR_MAX_CS];
u8 mr2data_fn[LPDDR4_INTR_MAX_CS];
u8 mr3data_fn[LPDDR4_INTR_MAX_CS];
u8 mr11data_fn[LPDDR4_INTR_MAX_CS];
u8 mr12data_fn[LPDDR4_INTR_MAX_CS];
u8 mr13data_fn[LPDDR4_INTR_MAX_CS];
u8 mr14data_fn[LPDDR4_INTR_MAX_CS];
u8 mr22data_fn[LPDDR4_INTR_MAX_CS];
ram: k3-j721e: Add support for J721E DDR controller The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-07 22:56:36 +09:00
};
#endif /* LPDDR4_STRUCTS_IF_H */
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