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ram: k3-j721e: Add support for J721E DDR controller

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The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper
logic to integrate these blocks in the device. The DDR subsystem is
used to provide an interface to external SDRAM devices which can be
utilized for storing program or data. Introduce support for the
DDR controller and DDR phy within the DDR subsystem.

Signed-off-by: Kevin Scholz <k-scholz@ti.com
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Kevin Scholz 2019-10-07 19:26:36 +05:30 committed by Tom Rini
parent ffb6b8e540
commit 3bb3f266ee
21 changed files with 32102 additions and 0 deletions
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11
drivers/ram/Kconfig
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@ -54,5 +54,16 @@ config K3_AM654_DDRSS
config add support for the initialization of the external
SDRAM devices connected to DDR subsystem.
config K3_J721E_DDRSS
bool "Enable J721E DDRSS support"
depends on RAM
help
The J721E DDR subsystem comprises DDR controller, DDR PHY and
wrapper logic to integrate these blocks in the device. The DDR
subsystem is used to provide an interface to external SDRAM
devices which can be utilized for storing program or data.
Enabling this config adds support for the DDR memory controller
on J721E family of SoCs.
source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"

1
drivers/ram/Makefile
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@ -14,3 +14,4 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/

8
drivers/ram/k3-j721e/Makefile Normal file
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@ -0,0 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
#
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e-ddrss.o
obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_obj_if.o
obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4.o

119
drivers/ram/k3-j721e/cps_drv_lpddr4.h Normal file
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@ -0,0 +1,119 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/******************************************************************************
*
* Copyright (C) 2017-2018 Cadence Design Systems, Inc.
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*
* cps_drv_lpddr4.h
* Interface for the Register Accaess Layer of Cadence Platform Service (CPS)
*****************************************************************************
*/
#ifndef CPS_DRV_H_
#define CPS_DRV_H_
#include <stddef.h>
#include <inttypes.h>
#include <asm/io.h>
/**
* \brief Read a 32-bit value from memory.
* \param reg address of the memory mapped hardware register
* \return the value at the given address
*/
#define CPS_REG_READ(reg) (readl((volatile uint32_t*)(reg)))
/**
* \brief Write a 32-bit address value to memory.
* \param reg address of the memory mapped hardware register
* \param value unsigned 32-bit value to write
*/
#define CPS_REG_WRITE(reg, value) (writel((uint32_t)(value), (volatile uint32_t*)(reg)))
/**
* \brief Subtitue the value of fld macro and concatinate with required string
* \param fld field name
*/
#define CPS_FLD_MASK(fld) (fld ## _MASK)
#define CPS_FLD_SHIFT(fld) (fld ## _SHIFT)
#define CPS_FLD_WIDTH(fld) (fld ## _WIDTH)
#define CPS_FLD_WOCLR(fld) (fld ## _WOCLR)
#define CPS_FLD_WOSET(fld) (fld ## _WOSET)
/**
* \brief Read a value of bit-field from the register value.
* \param reg register name
* \param fld field name
* \param reg_value register value
* \return bit-field value
*/
#define CPS_FLD_READ(fld, reg_value) (cps_fldread((uint32_t)(CPS_FLD_MASK(fld)), \
(uint32_t)(CPS_FLD_SHIFT(fld)), \
(uint32_t)(reg_value)))
/**
* \brief Write a value of the bit-field into the register value.
* \param reg register name
* \param fld field name
* \param reg_value register value
* \param value value to be written to bit-field
* \return modified register value
*/
#define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((uint32_t)(CPS_FLD_MASK(fld)), \
(uint32_t)(CPS_FLD_SHIFT(fld)), \
(uint32_t)(reg_value), (uint32_t)(value)))
/**
* \brief Set bit within the register value.
* \param reg register name
* \param fld field name
* \param reg_value register value
* \return modified register value
*/
#define CPS_FLD_SET(fld, reg_value) (cps_fldset((uint32_t)(CPS_FLD_WIDTH(fld)), \
(uint32_t)(CPS_FLD_MASK(fld)), \
(uint32_t)(CPS_FLD_WOCLR(fld)), \
(uint32_t)(reg_value)))
static inline uint32_t cps_fldread(uint32_t mask, uint32_t shift, uint32_t reg_value)
{
uint32_t result = (reg_value & mask) >> shift;
return (result);
}
/**
* \brief Write a value of the bit-field into the register value.
* \param mask mask for the bit-field
* \param shift bit-field shift from LSB
* \param reg_value register value
* \param value value to be written to bit-field
* \return modified register value
*/
static inline uint32_t cps_fldwrite(uint32_t mask, uint32_t shift, uint32_t reg_value, uint32_t value)
{
uint32_t new_value = (value << shift) & mask;
new_value = (reg_value & ~mask) | new_value;
return (new_value);
}
/**
* \brief Set bit within the register value.
* \param width width of the bit-field
* \param mask mask for the bit-field
* \param is_woclr is bit-field has 'write one to clear' flag set
* \param reg_value register value
* \return modified register value
*/
static inline uint32_t cps_fldset(uint32_t width, uint32_t mask, uint32_t is_woclr, uint32_t reg_value)
{
uint32_t new_value = reg_value;
/* Confirm the field to be bit and not write to clear type */
if ((width == 1U) && (is_woclr == 0U)) {
new_value |= mask;
}
return (new_value);
}
#endif /* CPS_DRV_H_ */

372
drivers/ram/k3-j721e/k3-j721e-ddrss.c Normal file
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@ -0,0 +1,372 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Texas Instruments' J721E DDRSS driver
*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <ram.h>
#include <asm/io.h>
#include <power-domain.h>
#include <wait_bit.h>
#include "lpddr4_obj_if.h"
#include "lpddr4_if.h"
#include "lpddr4_structs_if.h"
#include "lpddr4_ctl_regs.h"
#define SRAM_MAX 512
#define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80
#define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0
struct j721e_ddrss_desc {
struct udevice *dev;
void __iomem *ddrss_ss_cfg;
void __iomem *ddrss_ctrl_mmr;
struct power_domain ddrcfg_pwrdmn;
struct power_domain ddrdata_pwrdmn;
struct clk ddr_clk;
struct clk osc_clk;
u32 ddr_freq1;
u32 ddr_freq2;
u32 ddr_fhs_cnt;
};
static LPDDR4_OBJ *driverdt;
static lpddr4_config config;
static lpddr4_privatedata pd;
static struct j721e_ddrss_desc *ddrss;
#define TH_MACRO_EXP(fld, str) (fld##str)
#define TH_FLD_MASK(fld) TH_MACRO_EXP(fld, _MASK)
#define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT)
#define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH)
#define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR)
#define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET)
#define str(s) #s
#define xstr(s) str(s)
#define CTL_SHIFT 11
#define PHY_SHIFT 11
#define PI_SHIFT 10
#define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
char *i, *pstr= xstr(REG); offset = 0;\
for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
offset = offset * 10 + (*i - '0'); }\
} while (0)
static void j721e_lpddr4_ack_freq_upd_req(void)
{
unsigned int req_type, counter;
debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
true, 10000, false)) {
printf("Timeout during frequency handshake\n");
hang();
}
req_type = readl(ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
debug("%s: received freq change req: req type = %d, req no. = %d \n",
__func__, req_type, counter);
if (req_type == 1)
clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
else if (req_type == 2)
clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2);
else if (req_type == 0)
/* Put DDR pll in bypass mode */
clk_set_rate(&ddrss->ddr_clk,
clk_get_rate(&ddrss->osc_clk));
else
printf("%s: Invalid freq request type\n", __func__);
writel(0x1, ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
false, 10, false)) {
printf("Timeout during frequency handshake\n");
hang();
}
writel(0x0, ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
}
}
static void j721e_lpddr4_info_handler(const lpddr4_privatedata * pd,
lpddr4_infotype infotype)
{
if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE) {
j721e_lpddr4_ack_freq_upd_req();
}
}
static int j721e_ddrss_power_on(struct j721e_ddrss_desc *ddrss)
{
int ret;
debug("%s(ddrss=%p)\n", __func__, ddrss);
ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
if (ret) {
dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
return ret;
}
ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
if (ret) {
dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
return ret;
}
return 0;
}
static int j721e_ddrss_ofdata_to_priv(struct udevice *dev)
{
struct j721e_ddrss_desc *ddrss = dev_get_priv(dev);
phys_addr_t reg;
int ret;
debug("%s(dev=%p)\n", __func__, dev);
reg = dev_read_addr_name(dev, "cfg");
if (reg == FDT_ADDR_T_NONE) {
dev_err(dev, "No reg property for DDRSS wrapper logic\n");
return -EINVAL;
}
ddrss->ddrss_ss_cfg = (void *)reg;
reg = dev_read_addr_name(dev, "ctrl_mmr_lp4");
if (reg == FDT_ADDR_T_NONE) {
dev_err(dev, "No reg property for CTRL MMR\n");
return -EINVAL;
}
ddrss->ddrss_ctrl_mmr = (void *)reg;
ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
if (ret) {
dev_err(dev, "power_domain_get() failed: %d\n", ret);
return ret;
}
ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
if (ret) {
dev_err(dev, "power_domain_get() failed: %d\n", ret);
return ret;
}
ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk);
if (ret)
dev_err(dev, "clk get failed%d\n", ret);
ret = clk_get_by_index(dev, 1, &ddrss->osc_clk);
if (ret)
dev_err(dev, "clk get failed for osc clk %d\n", ret);
ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
if (ret)
dev_err(dev, "ddr freq1 not populated %d\n", ret);
ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2);
if (ret)
dev_err(dev, "ddr freq2 not populated %d\n", ret);
ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt);
if (ret)
dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
/* Put DDR pll in bypass mode */
ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
if (ret)
dev_err(dev, "ddr clk bypass failed\n");
return ret;
}
void j721e_lpddr4_probe(void)
{
uint32_t status = 0U;
uint16_t configsize = 0U;
status = driverdt->probe(&config, &configsize);
if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
|| (configsize > SRAM_MAX)) {
printf("LPDDR4_Probe: FAIL\n");
hang();
} else {
debug("LPDDR4_Probe: PASS\n");
}
}
void j721e_lpddr4_init(void)
{
uint32_t status = 0U;
if ((sizeof(pd) != sizeof(lpddr4_privatedata))
|| (sizeof(pd) > SRAM_MAX)) {
printf("LPDDR4_Init: FAIL\n");
hang();
}
config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
config.infohandler = (lpddr4_infocallback) j721e_lpddr4_info_handler;
status = driverdt->init(&pd, &config);
if ((status > 0U) ||
(pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) ||
(pd.ctlinterrupthandler != config.ctlinterrupthandler) ||
(pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) {
printf("LPDDR4_Init: FAIL\n");
hang();
} else {
debug("LPDDR4_Init: PASS\n");
}
}
void populate_data_array_from_dt(lpddr4_reginitdata * reginit_data)
{
int ret, i;
ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
(u32 *) reginit_data->denalictlreg,
LPDDR4_CTL_REG_COUNT);
if (ret)
printf("Error reading ctrl data\n");
for (i = 0; i < LPDDR4_CTL_REG_COUNT; i++)
reginit_data->updatectlreg[i] = true;
ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
(u32 *) reginit_data->denaliphyindepreg,
LPDDR4_PHY_INDEP_REG_COUNT);
if (ret)
printf("Error reading PI data\n");
for (i = 0; i < LPDDR4_PHY_INDEP_REG_COUNT; i++)
reginit_data->updatephyindepreg[i] = true;
ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
(u32 *) reginit_data->denaliphyreg,
LPDDR4_PHY_REG_COUNT);
if (ret)
printf("Error reading PHY data\n");
for (i = 0; i < LPDDR4_PHY_REG_COUNT; i++)
reginit_data->updatephyreg[i] = true;
}
void j721e_lpddr4_hardware_reg_init(void)
{
uint32_t status = 0U;
lpddr4_reginitdata reginitdata;
populate_data_array_from_dt(&reginitdata);
status = driverdt->writectlconfig(&pd, &reginitdata);
if (!status) {
status = driverdt->writephyindepconfig(&pd, &reginitdata);
}
if (!status) {
status = driverdt->writephyconfig(&pd, &reginitdata);
}
if (status) {
printf(" ERROR: LPDDR4_HardwareRegInit failed!!\n");
hang();
}
return;
}
void j721e_lpddr4_start(void)
{
uint32_t status = 0U;
uint32_t regval = 0U;
uint32_t offset = 0U;
TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
printf("LPDDR4_StartTest: FAIL\n");
hang();
}
status = driverdt->start(&pd);
if (status > 0U) {
printf("LPDDR4_StartTest: FAIL\n");
hang();
}
status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
printf("LPDDR4_Start: FAIL\n");
hang();
} else {
debug("LPDDR4_Start: PASS\n");
}
}
static int j721e_ddrss_probe(struct udevice *dev)
{
int ret;
ddrss = dev_get_priv(dev);
debug("%s(dev=%p)\n", __func__, dev);
ret = j721e_ddrss_ofdata_to_priv(dev);
if (ret)
return ret;
ddrss->dev = dev;
ret = j721e_ddrss_power_on(ddrss);
if (ret)
return ret;
driverdt = lpddr4_getinstance();
j721e_lpddr4_probe();
j721e_lpddr4_init();
j721e_lpddr4_hardware_reg_init();
j721e_lpddr4_start();
return ret;
}
static int j721e_ddrss_get_info(struct udevice *dev, struct ram_info *info)
{
return 0;
}
static struct ram_ops j721e_ddrss_ops = {
.get_info = j721e_ddrss_get_info,
};
static const struct udevice_id j721e_ddrss_ids[] = {
{.compatible = "ti,j721e-ddrss"},
{}
};
U_BOOT_DRIVER(j721e_ddrss) = {
.name = "j721e_ddrss",
.id = UCLASS_RAM,
.of_match = j721e_ddrss_ids,
.ops = &j721e_ddrss_ops,
.probe = j721e_ddrss_probe,
.priv_auto_alloc_size = sizeof(struct j721e_ddrss_desc),
};

2119
drivers/ram/k3-j721e/lpddr4.c Normal file
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File diff suppressed because it is too large Load Diff

825
drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h Normal file
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@ -0,0 +1,825 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/**********************************************************************
* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
*
* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
*
**********************************************************************
*/
#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
#define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU
#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_1024
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOSET 0U
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_1024
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0
#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_MASK 0x07000000U
#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_WIDTH 3U
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_1024
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0
#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH 32U
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_1025
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0
#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_1026
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_WIDTH 8U
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_1026
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x0F000000U
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_1026
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0
#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU
#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH 11U
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_1027
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_MASK 0x007F0000U
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0
#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U
#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_1028
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_MASK 0x00000700U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_WIDTH 3U
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__REG DENALI_PHY_1028
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOSET 0U
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG DENALI_PHY_1028
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOSET 0U
#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_1028
#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0
#define LPDDR4__DENALI_PHY_1029_READ_MASK 0x011F7F7FU
#define LPDDR4__DENALI_PHY_1029_WRITE_MASK 0x011F7F7FU
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_MASK 0x0000007FU
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U
#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_1029
#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_MASK 0x00007F00U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_WIDTH 7U
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__REG DENALI_PHY_1029
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_WIDTH 5U
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__REG DENALI_PHY_1029
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOSET 0U
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_1029
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0
#define LPDDR4__DENALI_PHY_1030_READ_MASK 0x01070301U
#define LPDDR4__DENALI_PHY_1030_WRITE_MASK 0x01070301U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1030
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_MASK 0x00000300U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_WIDTH 2U
#define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_1030
#define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_MASK 0x00070000U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_WIDTH 3U
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__REG DENALI_PHY_1030
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOSET 0U
#define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_1030
#define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0
#define LPDDR4__DENALI_PHY_1031_READ_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1031_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_WIDTH 27U
#define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_1031
#define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0
#define LPDDR4__DENALI_PHY_1032_READ_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1032_WRITE_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_WIDTH 6U
#define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_1032
#define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0
#define LPDDR4__DENALI_PHY_1033_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1033_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_1033
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0
#define LPDDR4__DENALI_PHY_1034_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1034_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_1034
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0
#define LPDDR4__DENALI_PHY_1035_READ_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1035_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_WIDTH 11U
#define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_1035
#define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_MASK 0x07FF0000U
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_WIDTH 11U
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_1035
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0
#define LPDDR4__DENALI_PHY_1036_READ_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1036_WRITE_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_WIDTH 11U
#define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_1036
#define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0
#define LPDDR4__DENALI_PHY_1037_READ_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1037_WRITE_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH 24U
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_1037
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0
#define LPDDR4__DENALI_PHY_1038_READ_MASK 0x03FFFFFFU
#define LPDDR4__DENALI_PHY_1038_WRITE_MASK 0x03FFFFFFU
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH 24U
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__REG DENALI_PHY_1038
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_MASK 0x03000000U
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_WIDTH 2U
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_1038
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0
#define LPDDR4__DENALI_PHY_1039_READ_MASK 0x01FF0F03U
#define LPDDR4__DENALI_PHY_1039_WRITE_MASK 0x01FF0F03U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH 2U
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__REG DENALI_PHY_1039
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_MASK 0x00000F00U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_WIDTH 4U
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__REG DENALI_PHY_1039
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_MASK 0x01FF0000U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_WIDTH 9U
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_1039
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0
#define LPDDR4__DENALI_PHY_1040_READ_MASK 0x07000001U
#define LPDDR4__DENALI_PHY_1040_WRITE_MASK 0x07000001U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOSET 0U
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__REG DENALI_PHY_1040
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_MASK 0x00000100U
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOSET 0U
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__REG DENALI_PHY_1040
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOSET 0U
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__REG DENALI_PHY_1040
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_MASK 0x07000000U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_WIDTH 3U
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_1040
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0
#define LPDDR4__DENALI_PHY_1041_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1041_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__REG DENALI_PHY_1041
#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0
#define LPDDR4__DENALI_PHY_1042_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1042_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__REG DENALI_PHY_1042
#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0
#define LPDDR4__DENALI_PHY_1043_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1043_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_1043
#define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0
#define LPDDR4__DENALI_PHY_1044_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1044_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_1044
#define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0
#define LPDDR4__DENALI_PHY_1045_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1045_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_1045
#define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0
#define LPDDR4__DENALI_PHY_1046_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1046_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_1046
#define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0
#define LPDDR4__DENALI_PHY_1047_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1047_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_1047
#define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0
#define LPDDR4__DENALI_PHY_1048_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1048_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_1048
#define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0
#define LPDDR4__DENALI_PHY_1049_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1049_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_1049
#define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0
#define LPDDR4__DENALI_PHY_1050_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1050_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_1050
#define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0
#define LPDDR4__DENALI_PHY_1051_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1051_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_1051
#define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0
#define LPDDR4__DENALI_PHY_1052_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1052_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_1052
#define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0
#define LPDDR4__DENALI_PHY_1053_READ_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1053_WRITE_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH 24U
#define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_1053
#define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0
#define LPDDR4__DENALI_PHY_1054_READ_MASK 0x3F3F03FFU
#define LPDDR4__DENALI_PHY_1054_WRITE_MASK 0x3F3F03FFU
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH 10U
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__REG DENALI_PHY_1054
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_MASK 0x003F0000U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_WIDTH 6U
#define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_1054
#define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_MASK 0x3F000000U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_WIDTH 6U
#define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_1054
#define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0
#define LPDDR4__DENALI_PHY_1055_READ_MASK 0x3F0F3F3FU
#define LPDDR4__DENALI_PHY_1055_WRITE_MASK 0x3F0F3F3FU
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH 6U
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__REG DENALI_PHY_1055
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_MASK 0x00003F00U
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_WIDTH 6U
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__REG DENALI_PHY_1055
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_MASK 0x000F0000U
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_WIDTH 4U
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__REG DENALI_PHY_1055
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_MASK 0x3F000000U
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_1055
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0
#define LPDDR4__DENALI_PHY_1056_READ_MASK 0xFFFFFF03U
#define LPDDR4__DENALI_PHY_1056_WRITE_MASK 0xFFFFFF03U
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_WIDTH 2U
#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__REG DENALI_PHY_1056
#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_MASK 0x0000FF00U
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_WIDTH 8U
#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__REG DENALI_PHY_1056
#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_MASK 0x00FF0000U
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_WIDTH 8U
#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__REG DENALI_PHY_1056
#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_MASK 0xFF000000U
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_WIDTH 8U
#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__REG DENALI_PHY_1056
#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0
#define LPDDR4__DENALI_PHY_1057_READ_MASK 0x01FFFFFFU
#define LPDDR4__DENALI_PHY_1057_WRITE_MASK 0x01FFFFFFU
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_WIDTH 8U
#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__REG DENALI_PHY_1057
#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_MASK 0x0000FF00U
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_WIDTH 8U
#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__REG DENALI_PHY_1057
#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_MASK 0x00FF0000U
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_WIDTH 8U
#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__REG DENALI_PHY_1057
#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET 0U
#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1057
#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0
#define LPDDR4__DENALI_PHY_1058_READ_MASK 0x3F03FFFFU
#define LPDDR4__DENALI_PHY_1058_WRITE_MASK 0x3F03FFFFU
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_WIDTH 8U
#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1058
#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_MASK 0x0000FF00U
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_WIDTH 8U
#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__REG DENALI_PHY_1058
#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_MASK 0x00030000U
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_WIDTH 2U
#define LPDDR4__PHY_ADR_DC_WEIGHT_0__REG DENALI_PHY_1058
#define LPDDR4__PHY_ADR_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_MASK 0x3F000000U
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_WIDTH 6U
#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__REG DENALI_PHY_1058
#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0
#define LPDDR4__DENALI_PHY_1059_READ_MASK 0x0101FFFFU
#define LPDDR4__DENALI_PHY_1059_WRITE_MASK 0x0101FFFFU
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_WIDTH 8U
#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__REG DENALI_PHY_1059
#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_MASK 0x0000FF00U
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_WIDTH 8U
#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__REG DENALI_PHY_1059
#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOSET 0U
#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__REG DENALI_PHY_1059
#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOSET 0U
#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__REG DENALI_PHY_1059
#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0
#define LPDDR4__DENALI_PHY_1060_READ_MASK 0x07FF3F01U
#define LPDDR4__DENALI_PHY_1060_WRITE_MASK 0x07FF3F01U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOSET 0U
#define LPDDR4__PHY_ADR_DC_CAL_START_0__REG DENALI_PHY_1060
#define LPDDR4__PHY_ADR_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_MASK 0x00003F00U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_1060
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0
#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_MASK 0x07FF0000U
#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_WIDTH 11U
#define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__REG DENALI_PHY_1060
#define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__FLD LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0
#define LPDDR4__DENALI_PHY_1061_READ_MASK 0x01FF01FFU
#define LPDDR4__DENALI_PHY_1061_WRITE_MASK 0x01FF01FFU
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_WIDTH 9U
#define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__REG DENALI_PHY_1061
#define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_MASK 0x01FF0000U
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_WIDTH 9U
#define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_1061
#define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0
#define LPDDR4__DENALI_PHY_1062_READ_MASK 0x01010000U
#define LPDDR4__DENALI_PHY_1062_WRITE_MASK 0x01010000U
#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_WIDTH 9U
#define LPDDR4__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1062
#define LPDDR4__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WOSET 0U
#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_0__REG DENALI_PHY_1062
#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WOSET 0U
#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0__REG DENALI_PHY_1062
#define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0
#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WOSET 0U
#define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1063
#define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0
#define LPDDR4__DENALI_PHY_1064_READ_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1064_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_WIDTH 8U
#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_1064
#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_MASK 0x00000700U
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_WIDTH 3U
#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__REG DENALI_PHY_1064
#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0
#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_MASK 0x07FF0000U
#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U
#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_1064
#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0
#define LPDDR4__DENALI_PHY_1065_READ_MASK 0x1F07FF1FU
#define LPDDR4__DENALI_PHY_1065_WRITE_MASK 0x1F07FF1FU
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK 0x0000001FU
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH 5U
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK 0x0007FF00U
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1065
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK 0x1F000000U
#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH 5U
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_1066_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1066_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1066
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH 5U
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1066
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_1067_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1067_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1067
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH 5U
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1067
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_1068_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1068_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1068
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH 5U
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1068
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_1069_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1069_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1069
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH 5U
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1069
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_1070_READ_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_1070_WRITE_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1070
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_MASK 0x000F0000U
#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_WIDTH 4U
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_1070
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0
#define LPDDR4__DENALI_PHY_1071_READ_MASK 0xFF3F07FFU
#define LPDDR4__DENALI_PHY_1071_WRITE_MASK 0xFF3F07FFU
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_WIDTH 11U
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_1071
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_MASK 0x003F0000U
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH 6U
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_1071
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_MASK 0xFF000000U
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH 8U
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_1071
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0
#define LPDDR4__DENALI_PHY_1072_READ_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_1072_WRITE_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_1072
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK 0x0003FF00U
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH 10U
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_1072
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET 0U
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_1072
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0
#define LPDDR4__DENALI_PHY_1073_READ_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1073_WRITE_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_WIDTH 4U
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_1073
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0
#define LPDDR4__DENALI_PHY_1074_READ_MASK 0x03FF010FU
#define LPDDR4__DENALI_PHY_1074_WRITE_MASK 0x03FF010FU
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH 4U
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_1074
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK 0x00000100U
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET 0U
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_1074
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_MASK 0x03FF0000U
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_WIDTH 10U
#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__REG DENALI_PHY_1074
#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0
#define LPDDR4__DENALI_PHY_1075_READ_MASK 0x0000FF01U
#define LPDDR4__DENALI_PHY_1075_WRITE_MASK 0x0000FF01U
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WOSET 0U
#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__REG DENALI_PHY_1075
#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_MASK 0x0000FF00U
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_WIDTH 8U
#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__REG DENALI_PHY_1075
#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0
#endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */

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/* SPDX-License-Identifier: BSD-3-Clause */
/**********************************************************************
* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
**********************************************************************
* WARNING: This file is auto-generated using api-generator utility.
* api-generator: 12.02.13bb8d5
* Do not edit it manually.
**********************************************************************
* Cadence Core Driver for LPDDR4.
**********************************************************************
*/
#ifndef LPDDR4_IF_H
#define LPDDR4_IF_H
#include <linux/types.h>
/** @defgroup ConfigInfo Configuration and Hardware Operation Information
* The following definitions specify the driver operation environment that
* is defined by hardware configuration or client code. These defines are
* located in the header file of the core driver.
* @{
*/
/**********************************************************************
* Defines
**********************************************************************/
/** Number of chip-selects */
#define LPDDR4_MAX_CS (2U)
/** Number of accessible registers for controller. */
#define LPDDR4_CTL_REG_COUNT (459U)
/** Number of accessible registers for PHY Independent Module. */
#define LPDDR4_PHY_INDEP_REG_COUNT (300U)
/** Number of accessible registers for PHY. */
#define LPDDR4_PHY_REG_COUNT (1423U)
/**
* @}
*/
/** @defgroup DataStructure Dynamic Data Structures
* This section defines the data structures used by the driver to provide
* hardware information, modification and dynamic operation of the driver.
* These data structures are defined in the header file of the core driver
* and utilized by the API.
* @{
*/
/**********************************************************************
* Forward declarations
**********************************************************************/
typedef struct lpddr4_config_s lpddr4_config;
typedef struct lpddr4_privatedata_s lpddr4_privatedata;
typedef struct lpddr4_debuginfo_s lpddr4_debuginfo;
typedef struct lpddr4_fspmoderegs_s lpddr4_fspmoderegs;
typedef struct lpddr4_reginitdata_s lpddr4_reginitdata;
/**********************************************************************
* Enumerations
**********************************************************************/
/** This is used to indicate whether the Controller, PHY, or PHY Independent module is addressed. */
typedef enum
{
LPDDR4_CTL_REGS = 0U,
LPDDR4_PHY_REGS = 1U,
LPDDR4_PHY_INDEP_REGS = 2U
} lpddr4_regblock;
/** Controller status or error interrupts. */
typedef enum
{
LPDDR4_RESET_DONE = 0U,
LPDDR4_BUS_ACCESS_ERROR = 1U,
LPDDR4_MULTIPLE_BUS_ACCESS_ERROR = 2U,
LPDDR4_ECC_MULTIPLE_CORR_ERROR = 3U,
LPDDR4_ECC_MULTIPLE_UNCORR_ERROR = 4U,
LPDDR4_ECC_WRITEBACK_EXEC_ERROR = 5U,
LPDDR4_ECC_SCRUB_DONE = 6U,
LPDDR4_ECC_SCRUB_ERROR = 7U,
LPDDR4_PORT_COMMAND_ERROR = 8U,
LPDDR4_MC_INIT_DONE = 9U,
LPDDR4_LP_DONE = 10U,
LPDDR4_BIST_DONE = 11U,
LPDDR4_WRAP_ERROR = 12U,
LPDDR4_INVALID_BURST_ERROR = 13U,
LPDDR4_RDLVL_ERROR = 14U,
LPDDR4_RDLVL_GATE_ERROR = 15U,
LPDDR4_WRLVL_ERROR = 16U,
LPDDR4_CA_TRAINING_ERROR = 17U,
LPDDR4_DFI_UPDATE_ERROR = 18U,
LPDDR4_MRR_ERROR = 19U,
LPDDR4_PHY_MASTER_ERROR = 20U,
LPDDR4_WRLVL_REQ = 21U,
LPDDR4_RDLVL_REQ = 22U,
LPDDR4_RDLVL_GATE_REQ = 23U,
LPDDR4_CA_TRAINING_REQ = 24U,
LPDDR4_LEVELING_DONE = 25U,
LPDDR4_PHY_ERROR = 26U,
LPDDR4_MR_READ_DONE = 27U,
LPDDR4_TEMP_CHANGE = 28U,
LPDDR4_TEMP_ALERT = 29U,
LPDDR4_SW_DQS_COMPLETE = 30U,
LPDDR4_DQS_OSC_BV_UPDATED = 31U,
LPDDR4_DQS_OSC_OVERFLOW = 32U,
LPDDR4_DQS_OSC_VAR_OUT = 33U,
LPDDR4_MR_WRITE_DONE = 34U,
LPDDR4_INHIBIT_DRAM_DONE = 35U,
LPDDR4_DFI_INIT_STATE = 36U,
LPDDR4_DLL_RESYNC_DONE = 37U,
LPDDR4_TDFI_TO = 38U,
LPDDR4_DFS_DONE = 39U,
LPDDR4_DFS_STATUS = 40U,
LPDDR4_REFRESH_STATUS = 41U,
LPDDR4_ZQ_STATUS = 42U,
LPDDR4_SW_REQ_MODE = 43U,
LPDDR4_LOR_BITS = 44U
} lpddr4_ctlinterrupt;
/** PHY Independent Module status or error interrupts. */
typedef enum
{
LPDDR4_PHY_INDEP_INIT_DONE_BIT = 0U,
LPDDR4_PHY_INDEP_CONTROL_ERROR_BIT = 1U,
LPDDR4_PHY_INDEP_CA_PARITY_ERR_BIT = 2U,
LPDDR4_PHY_INDEP_RDLVL_ERROR_BIT = 3U,
LPDDR4_PHY_INDEP_RDLVL_GATE_ERROR_BIT = 4U,
LPDDR4_PHY_INDEP_WRLVL_ERROR_BIT = 5U,
LPDDR4_PHY_INDEP_CALVL_ERROR_BIT = 6U,
LPDDR4_PHY_INDEP_WDQLVL_ERROR_BIT = 7U,
LPDDR4_PHY_INDEP_UPDATE_ERROR_BIT = 8U,
LPDDR4_PHY_INDEP_RDLVL_REQ_BIT = 9U,
LPDDR4_PHY_INDEP_RDLVL_GATE_REQ_BIT = 10U,
LPDDR4_PHY_INDEP_WRLVL_REQ_BIT = 11U,
LPDDR4_PHY_INDEP_CALVL_REQ_BIT = 12U,
LPDDR4_PHY_INDEP_WDQLVL_REQ_BIT = 13U,
LPDDR4_PHY_INDEP_LVL_DONE_BIT = 14U,
LPDDR4_PHY_INDEP_BIST_DONE_BIT = 15U,
LPDDR4_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 16U,
LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U
} lpddr4_phyindepinterrupt;
/** List of informations and warnings from driver. */
typedef enum
{
LPDDR4_DRV_NONE = 0U,
LPDDR4_DRV_SOC_PLL_UPDATE = 1U
} lpddr4_infotype;
/** Low power interface wake up timing parameters */
typedef enum
{
LPDDR4_LPI_PD_WAKEUP_FN = 0U,
LPDDR4_LPI_SR_SHORT_WAKEUP_FN = 1U,
LPDDR4_LPI_SR_LONG_WAKEUP_FN = 2U,
LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN = 3U,
LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN = 4U,
LPDDR4_LPI_SRPD_LONG_WAKEUP_FN = 5U,
LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN = 6U
} lpddr4_lpiwakeupparam;
/** Half Datapath mode setting */
typedef enum
{
LPDDR4_REDUC_ON = 0U,
LPDDR4_REDUC_OFF = 1U
} lpddr4_reducmode;
/** ECC Control parameter setting */
typedef enum
{
LPDDR4_ECC_DISABLED = 0U,
LPDDR4_ECC_ENABLED = 1U,
LPDDR4_ECC_ERR_DETECT = 2U,
LPDDR4_ECC_ERR_DETECT_CORRECT = 3U
} lpddr4_eccenable;
/** Data Byte Inversion mode setting */
typedef enum
{
LPDDR4_DBI_RD_ON = 0U,
LPDDR4_DBI_RD_OFF = 1U,
LPDDR4_DBI_WR_ON = 2U,
LPDDR4_DBI_WR_OFF = 3U
} lpddr4_dbimode;
/** Controller Frequency Set Point number */
typedef enum
{
LPDDR4_FSP_0 = 0U,
LPDDR4_FSP_1 = 1U,
LPDDR4_FSP_2 = 2U
} lpddr4_ctlfspnum;
/**********************************************************************
* Callbacks
**********************************************************************/
/**
* Reports informations and warnings that need to be communicated.
* Params:
* pD - driver state info specific to this instance.
* infoType - Type of information.
*/
typedef void (*lpddr4_infocallback)(const lpddr4_privatedata* pd, lpddr4_infotype infotype);
/**
* Reports interrupts received by the controller.
* Params:
* pD - driver state info specific to this instance.
* ctlInterrupt - Interrupt raised
* chipSelect - Chip for which interrupt raised
*/
typedef void (*lpddr4_ctlcallback)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt ctlinterrupt, uint8_t chipselect);
/**
* Reports interrupts received by the PHY Independent Module.
* Params:
* privateData - driver state info specific to this instance.
* phyIndepInterrupt - Interrupt raised
* chipSelect - Chip for which interrupt raised
*/
typedef void (*lpddr4_phyindepcallback)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt phyindepinterrupt, uint8_t chipselect);
/**
* @}
*/
/** @defgroup DriverFunctionAPI Driver Function API
* Prototypes for the driver API functions. The user application can link statically to the
* necessary API functions and call them directly.
* @{
*/
/**********************************************************************
* API methods
**********************************************************************/
/**
* Checks configuration object.
* @param[in] config Driver/hardware configuration required.
* @param[out] configSize Size of memory allocations required.
* @return CDN_EOK on success (requirements structure filled).
* @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints.
*/
uint32_t lpddr4_probe(const lpddr4_config* config, uint16_t* configsize);
/**
* Init function to be called after LPDDR4_probe() to set up the
* driver configuration. Memory should be allocated for drv_data
* (using the size determined using LPDDR4_probe) before calling this
* API. init_settings should be initialised with base addresses for
* PHY Indepenent Module, Controller and PHY before calling this
* function. If callbacks are required for interrupt handling, these
* should also be configured in init_settings.
* @param[in] pD Driver state info specific to this instance.
* @param[in] cfg Specifies driver/hardware configuration.
* @return CDN_EOK on success
* @return EINVAL if illegal/inconsistent values in cfg.
* @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) required by 'config' parameters.
*/
uint32_t lpddr4_init(lpddr4_privatedata* pd, const lpddr4_config* cfg);
/**
* Start the driver.
* @param[in] pD Driver state info specific to this instance.
*/
uint32_t lpddr4_start(const lpddr4_privatedata* pd);
/**
* Read a register from the controller, PHY or PHY Independent Module
* @param[in] pD Driver state info specific to this instance.
* @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
* @param[in] regOffset Register offset
* @param[out] regValue Register value read
* @return CDN_EOK on success.
* @return EINVAL if regOffset if out of range or regValue is NULL
*/
uint32_t lpddr4_readreg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t* regvalue);
/**
* Write a register in the controller, PHY or PHY Independent Module
* @param[in] pD Driver state info specific to this instance.
* @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
* @param[in] regOffset Register offset
* @param[in] regValue Register value to be written
* @return CDN_EOK on success.
* @return EINVAL if regOffset is out of range or regValue is NULL
*/
uint32_t lpddr4_writereg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t regvalue);
/**
* Read a memory mode register from DRAM
* @param[in] pD Driver state info specific to this instance.
* @param[in] readModeRegVal Value to set in 'read_modereg' parameter.
* @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices.
* @param[out] mmrStatus Status of mode register read(mrr) instruction.
* @return CDN_EOK on success.
* @return EINVAL if regNumber is out of range or regValue is NULL
*/
uint32_t lpddr4_getmmrregister(const lpddr4_privatedata* pd, uint32_t readmoderegval, uint64_t* mmrvalue, uint8_t* mmrstatus);
/**
* Write a memory mode register in DRAM
* @param[in] pD Driver state info specific to this instance.
* @param[in] writeModeRegVal Value to set in 'write_modereg' parameter.
* @param[out] mrwStatus Status of mode register write(mrw) instruction.
* @return CDN_EOK on success.
* @return EINVAL if regNumber is out of range or regValue is NULL
*/
uint32_t lpddr4_setmmrregister(const lpddr4_privatedata* pd, uint32_t writemoderegval, uint8_t* mrwstatus);
/**
* Write a set of initialisation values to the controller registers
* @param[in] pD Driver state info specific to this instance.
* @param[in] regValues Register values to be written
* @return CDN_EOK on success.
* @return EINVAL if regValues is NULL
*/
uint32_t lpddr4_writectlconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
/**
* Write a set of initialisation values to the PHY registers
* @param[in] pD Driver state info specific to this instance.
* @param[in] regValues Register values to be written
* @return CDN_EOK on success.
* @return EINVAL if regValues is NULL
*/
uint32_t lpddr4_writephyconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
/**
* Write a set of initialisation values to the PHY Independent Module
* registers
* @param[in] pD Driver state info specific to this instance.
* @param[in] regValues Register values to be written
* @return CDN_EOK on success.
* @return EINVAL if regValues is NULL
*/
uint32_t lpddr4_writephyindepconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
/**
* Read values of the controller registers in bulk (Set 'updateCtlReg'
* to read) and store in memory.
* @param[in] pD Driver state info specific to this instance.
* @param[out] regValues Register values which are read
* @return CDN_EOK on success.
* @return EINVAL if regValues is NULL
*/
uint32_t lpddr4_readctlconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
/**
* Read the values of the PHY module registers in bulk (Set
* 'updatePhyReg' to read) and store in memory.
* @param[in] pD Driver state info specific to this instance.
* @param[out] regValues Register values which are read
* @return CDN_EOK on success.
* @return EINVAL if regValues is NULL
*/
uint32_t lpddr4_readphyconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
/**
* Read the values of the PHY Independent module registers in bulk(Set
* 'updatePhyIndepReg' to read) and store in memory.
* @param[in] pD Driver state info specific to this instance.
* @param[out] regValues Register values which are read
* @return CDN_EOK on success.
* @return EINVAL if regValues is NULL
*/
uint32_t lpddr4_readphyindepconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
/**
* Read the current interrupt mask for the controller
* @param[in] pD Driver state info specific to this instance.
* @param[out] mask Value of interrupt mask
* @return CDN_EOK on success.
* @return EINVAL if mask pointer is NULL
*/
uint32_t lpddr4_getctlinterruptmask(const lpddr4_privatedata* pd, uint64_t* mask);
/**
* Sets the interrupt mask for the controller
* @param[in] pD Driver state info specific to this instance.
* @param[in] mask Value of interrupt mask to be written
* @return CDN_EOK on success.
* @return EINVAL if mask pointer is NULL
*/
uint32_t lpddr4_setctlinterruptmask(const lpddr4_privatedata* pd, const uint64_t* mask);
/**
* Check whether a specific controller interrupt is active
* @param[in] pD Driver state info specific to this instance.
* @param[in] intr Interrupt to be checked
* @param[out] irqStatus Status of the interrupt, TRUE if active
* @return CDN_EOK on success.
* @return EINVAL if intr is not valid
*/
uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr, bool* irqstatus);
/**
* Acknowledge a specific controller interrupt
* @param[in] pD Driver state info specific to this instance.
* @param[in] intr Interrupt to be acknowledged
* @return CDN_EOK on success.
* @return EINVAL if intr is not valid
*/
uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr);
/**
* Read the current interrupt mask for the PHY Independent Module
* @param[in] pD Driver state info specific to this instance.
* @param[out] mask Value of interrupt mask
* @return CDN_EOK on success.
* @return EINVAL if mask pointer is NULL
*/
uint32_t lpddr4_getphyindepinterruptmask(const lpddr4_privatedata* pd, uint32_t* mask);
/**
* Sets the interrupt mask for the PHY Independent Module
* @param[in] pD Driver state info specific to this instance.
* @param[in] mask Value of interrupt mask to be written
* @return CDN_EOK on success.
* @return EINVAL if mask pointer is NULL
*/
uint32_t lpddr4_setphyindepinterruptmask(const lpddr4_privatedata* pd, const uint32_t* mask);
/**
* Check whether a specific PHY Independent Module interrupt is active
* @param[in] pD Driver state info specific to this instance.
* @param[in] intr Interrupt to be checked
* @param[out] irqStatus Status of the interrupt, TRUE if active
* @return CDN_EOK on success.
* @return EINVAL if intr is not valid
*/
uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr, bool* irqstatus);
/**
* Acknowledge a specific PHY Independent Module interrupt
* @param[in] pD Driver state info specific to this instance.
* @param[in] intr Interrupt to be acknowledged
* @return CDN_EOK on success.
* @return EINVAL if intr is not valid
*/
uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr);
/**
* Retrieve status information after a failed init. The
* DebugStructInfo will be filled in with error codes which can be
* referenced against the driver documentation for further details.
* @param[in] pD Driver state info specific to this instance.
* @param[out] debugInfo status
* @return CDN_EOK on success.
* @return EINVAL if debugInfo is NULL
*/
uint32_t lpddr4_getdebuginitinfo(const lpddr4_privatedata* pd, lpddr4_debuginfo* debuginfo);
/**
* Get the current value of Low power Interface wake up time.
* @param[in] pD Driver state info specific to this instance.
* @param[in] lpiWakeUpParam LPI timing parameter
* @param[in] fspNum Frequency copy
* @param[out] cycles Timing value(in cycles)
* @return CDN_EOK on success.
* @return EINVAL if powerMode is NULL
*/
uint32_t lpddr4_getlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
/**
* Set the current value of Low power Interface wake up time.
* @param[in] pD Driver state info specific to this instance.
* @param[in] lpiWakeUpParam LPI timing parameter
* @param[in] fspNum Frequency copy
* @param[in] cycles Timing value(in cycles)
* @return CDN_EOK on success.
* @return EINVAL if powerMode is NULL
*/
uint32_t lpddr4_setlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
/**
* Get the current value for ECC auto correction
* @param[in] pD Driver state info specific to this instance.
* @param[out] eccParam ECC parameter setting
* @return CDN_EOK on success.
* @return EINVAL if on_off is NULL
*/
uint32_t lpddr4_geteccenable(const lpddr4_privatedata* pd, lpddr4_eccenable* eccparam);
/**
* Set the value for ECC auto correction. This API must be called
* before startup of memory.
* @param[in] pD Driver state info specific to this instance.
* @param[in] eccParam ECC control parameter setting
* @return CDN_EOK on success.
* @return EINVAL if on_off is NULL
*/
uint32_t lpddr4_seteccenable(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
/**
* Get the current value for the Half Datapath option
* @param[in] pD Driver state info specific to this instance.
* @param[out] mode Half Datapath setting
* @return CDN_EOK on success.
* @return EINVAL if mode is NULL
*/
uint32_t lpddr4_getreducmode(const lpddr4_privatedata* pd, lpddr4_reducmode* mode);
/**
* Set the value for the Half Datapath option. This API must be
* called before startup of memory.
* @param[in] pD Driver state info specific to this instance.
* @param[in] mode Half Datapath setting
* @return CDN_EOK on success.
* @return EINVAL if mode is NULL
*/
uint32_t lpddr4_setreducmode(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
/**
* Get the current value for Data Bus Inversion setting. This will be
* compared with the current DRAM setting using the MR3 register.
* @param[in] pD Driver state info specific to this instance.
* @param[out] on_off DBI read value
* @return CDN_EOK on success.
* @return EINVAL if on_off is NULL
*/
uint32_t lpddr4_getdbireadmode(const lpddr4_privatedata* pd, bool* on_off);
/**
* Get the current value for Data Bus Inversion setting. This will be
* compared with the current DRAM setting using the MR3 register.
* @param[in] pD Driver state info specific to this instance.
* @param[out] on_off DBI write value
* @return CDN_EOK on success.
* @return EINVAL if on_off is NULL
*/
uint32_t lpddr4_getdbiwritemode(const lpddr4_privatedata* pd, bool* on_off);
/**
* Set the mode for Data Bus Inversion. This will also be set in DRAM
* using the MR3 controller register. This API must be called before
* startup of memory.
* @param[in] pD Driver state info specific to this instance.
* @param[in] mode status
* @return CDN_EOK on success.
* @return EINVAL if mode is NULL
*/
uint32_t lpddr4_setdbimode(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode);
/**
* Get the current value for the refresh rate (reading Refresh per
* command timing).
* @param[in] pD Driver state info specific to this instance.
* @param[in] fspNum Frequency set number
* @param[out] cycles Refresh rate (in cycles)
* @return CDN_EOK on success.
* @return EINVAL if rate is NULL
*/
uint32_t lpddr4_getrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
/**
* Set the refresh rate (writing Refresh per command timing).
* @param[in] pD Driver state info specific to this instance.
* @param[in] fspNum Frequency set number
* @param[in] cycles Refresh rate (in cycles)
* @return CDN_EOK on success.
* @return EINVAL if rate is NULL
*/
uint32_t lpddr4_setrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
/**
* Handle Refreshing per chip select
* @param[in] pD Driver state info specific to this instance.
* @param[in] trefInterval status
* @return CDN_EOK on success.
* @return EINVAL if chipSelect is invalid
*/
uint32_t lpddr4_refreshperchipselect(const lpddr4_privatedata* pd, const uint32_t trefinterval);
#endif /* LPDDR4_IF_H */

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// SPDX-License-Identifier: BSD-3-Clause
/**********************************************************************
* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
**********************************************************************
* WARNING: This file is auto-generated using api-generator utility.
* api-generator: 12.02.13bb8d5
* Do not edit it manually.
**********************************************************************
* Cadence Core Driver for LPDDR4.
**********************************************************************
*/
#include "lpddr4_obj_if.h"
LPDDR4_OBJ *lpddr4_getinstance(void)
{
static LPDDR4_OBJ driver = {
.probe = lpddr4_probe,
.init = lpddr4_init,
.start = lpddr4_start,
.readreg = lpddr4_readreg,
.writereg = lpddr4_writereg,
.getmmrregister = lpddr4_getmmrregister,
.setmmrregister = lpddr4_setmmrregister,
.writectlconfig = lpddr4_writectlconfig,
.writephyconfig = lpddr4_writephyconfig,
.writephyindepconfig = lpddr4_writephyindepconfig,
.readctlconfig = lpddr4_readctlconfig,
.readphyconfig = lpddr4_readphyconfig,
.readphyindepconfig = lpddr4_readphyindepconfig,
.getctlinterruptmask = lpddr4_getctlinterruptmask,
.setctlinterruptmask = lpddr4_setctlinterruptmask,
.checkctlinterrupt = lpddr4_checkctlinterrupt,
.ackctlinterrupt = lpddr4_ackctlinterrupt,
.getphyindepinterruptmask = lpddr4_getphyindepinterruptmask,
.setphyindepinterruptmask = lpddr4_setphyindepinterruptmask,
.checkphyindepinterrupt = lpddr4_checkphyindepinterrupt,
.ackphyindepinterrupt = lpddr4_ackphyindepinterrupt,
.getdebuginitinfo = lpddr4_getdebuginitinfo,
.getlpiwakeuptime = lpddr4_getlpiwakeuptime,
.setlpiwakeuptime = lpddr4_setlpiwakeuptime,
.geteccenable = lpddr4_geteccenable,
.seteccenable = lpddr4_seteccenable,
.getreducmode = lpddr4_getreducmode,
.setreducmode = lpddr4_setreducmode,
.getdbireadmode = lpddr4_getdbireadmode,
.getdbiwritemode = lpddr4_getdbiwritemode,
.setdbimode = lpddr4_setdbimode,
.getrefreshrate = lpddr4_getrefreshrate,
.setrefreshrate = lpddr4_setrefreshrate,
.refreshperchipselect = lpddr4_refreshperchipselect,
};
return &driver;
}

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/* SPDX-License-Identifier: BSD-3-Clause */
/**********************************************************************
* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
**********************************************************************
* WARNING: This file is auto-generated using api-generator utility.
* api-generator: 12.02.13bb8d5
* Do not edit it manually.
**********************************************************************
* Cadence Core Driver for LPDDR4.
**********************************************************************
*/
#ifndef LPDDR4_OBJ_IF_H
#define LPDDR4_OBJ_IF_H
#include "lpddr4_if.h"
/** @defgroup DriverObject Driver API Object
* API listing for the driver. The API is contained in the object as
* function pointers in the object structure. As the actual functions
* resides in the Driver Object, the client software must first use the
* global GetInstance function to obtain the Driver Object Pointer.
* The actual APIs then can be invoked using obj->(api_name)() syntax.
* These functions are defined in the header file of the core driver
* and utilized by the API.
* @{
*/
/**********************************************************************
* API methods
**********************************************************************/
typedef struct lpddr4_obj_s
{
/**
* Checks configuration object.
* @param[in] config Driver/hardware configuration required.
* @param[out] configSize Size of memory allocations required.
* @return CDN_EOK on success (requirements structure filled).
* @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints.
*/
uint32_t (*probe)(const lpddr4_config* config, uint16_t* configsize);
/**
* Init function to be called after LPDDR4_probe() to set up the
* driver configuration. Memory should be allocated for drv_data
* (using the size determined using LPDDR4_probe) before calling
* this API. init_settings should be initialised with base addresses
* for PHY Indepenent Module, Controller and PHY before calling this
* function. If callbacks are required for interrupt handling, these
* should also be configured in init_settings.
* @param[in] pD Driver state info specific to this instance.
* @param[in] cfg Specifies driver/hardware configuration.
* @return CDN_EOK on success
* @return EINVAL if illegal/inconsistent values in cfg.
* @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) required by 'config' parameters.
*/
uint32_t (*init)(lpddr4_privatedata* pd, const lpddr4_config* cfg);
/**
* Start the driver.
* @param[in] pD Driver state info specific to this instance.
*/
uint32_t (*start)(const lpddr4_privatedata* pd);
/**
* Read a register from the controller, PHY or PHY Independent Module
* @param[in] pD Driver state info specific to this instance.
* @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
* @param[in] regOffset Register offset
* @param[out] regValue Register value read
* @return CDN_EOK on success.
* @return EINVAL if regOffset if out of range or regValue is NULL
*/
uint32_t (*readreg)(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t* regvalue);
/**
* Write a register in the controller, PHY or PHY Independent Module
* @param[in] pD Driver state info specific to this instance.
* @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
* @param[in] regOffset Register offset
* @param[in] regValue Register value to be written
* @return CDN_EOK on success.
* @return EINVAL if regOffset is out of range or regValue is NULL
*/
uint32_t (*writereg)(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t regvalue);
/**
* Read a memory mode register from DRAM
* @param[in] pD Driver state info specific to this instance.
* @param[in] readModeRegVal Value to set in 'read_modereg' parameter.
* @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices.
* @param[out] mmrStatus Status of mode register read(mrr) instruction.
* @return CDN_EOK on success.
* @return EINVAL if regNumber is out of range or regValue is NULL
*/
uint32_t (*getmmrregister)(const lpddr4_privatedata* pd, uint32_t readmoderegval, uint64_t* mmrvalue, uint8_t* mmrstatus);
/**
* Write a memory mode register in DRAM
* @param[in] pD Driver state info specific to this instance.
* @param[in] writeModeRegVal Value to set in 'write_modereg' parameter.
* @param[out] mrwStatus Status of mode register write(mrw) instruction.
* @return CDN_EOK on success.
* @return EINVAL if regNumber is out of range or regValue is NULL
*/
uint32_t (*setmmrregister)(const lpddr4_privatedata* pd, uint32_t writemoderegval, uint8_t* mrwstatus);
/**
* Write a set of initialisation values to the controller registers
* @param[in] pD Driver state info specific to this instance.
* @param[in] regValues Register values to be written
* @return CDN_EOK on success.
* @return EINVAL if regValues is NULL
*/
uint32_t (*writectlconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
/**
* Write a set of initialisation values to the PHY registers
* @param[in] pD Driver state info specific to this instance.
* @param[in] regValues Register values to be written
* @return CDN_EOK on success.
* @return EINVAL if regValues is NULL
*/
uint32_t (*writephyconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
/**
* Write a set of initialisation values to the PHY Independent Module
* registers
* @param[in] pD Driver state info specific to this instance.
* @param[in] regValues Register values to be written
* @return CDN_EOK on success.
* @return EINVAL if regValues is NULL
*/
uint32_t (*writephyindepconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
/**
* Read values of the controller registers in bulk (Set
* 'updateCtlReg' to read) and store in memory.
* @param[in] pD Driver state info specific to this instance.
* @param[out] regValues Register values which are read
* @return CDN_EOK on success.
* @return EINVAL if regValues is NULL
*/
uint32_t (*readctlconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
/**
* Read the values of the PHY module registers in bulk (Set
* 'updatePhyReg' to read) and store in memory.
* @param[in] pD Driver state info specific to this instance.
* @param[out] regValues Register values which are read
* @return CDN_EOK on success.
* @return EINVAL if regValues is NULL
*/
uint32_t (*readphyconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
/**
* Read the values of the PHY Independent module registers in
* bulk(Set 'updatePhyIndepReg' to read) and store in memory.
* @param[in] pD Driver state info specific to this instance.
* @param[out] regValues Register values which are read
* @return CDN_EOK on success.
* @return EINVAL if regValues is NULL
*/
uint32_t (*readphyindepconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
/**
* Read the current interrupt mask for the controller
* @param[in] pD Driver state info specific to this instance.
* @param[out] mask Value of interrupt mask
* @return CDN_EOK on success.
* @return EINVAL if mask pointer is NULL
*/
uint32_t (*getctlinterruptmask)(const lpddr4_privatedata* pd, uint64_t* mask);
/**
* Sets the interrupt mask for the controller
* @param[in] pD Driver state info specific to this instance.
* @param[in] mask Value of interrupt mask to be written
* @return CDN_EOK on success.
* @return EINVAL if mask pointer is NULL
*/
uint32_t (*setctlinterruptmask)(const lpddr4_privatedata* pd, const uint64_t* mask);
/**
* Check whether a specific controller interrupt is active
* @param[in] pD Driver state info specific to this instance.
* @param[in] intr Interrupt to be checked
* @param[out] irqStatus Status of the interrupt, TRUE if active
* @return CDN_EOK on success.
* @return EINVAL if intr is not valid
*/
uint32_t (*checkctlinterrupt)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr, bool* irqstatus);
/**
* Acknowledge a specific controller interrupt
* @param[in] pD Driver state info specific to this instance.
* @param[in] intr Interrupt to be acknowledged
* @return CDN_EOK on success.
* @return EINVAL if intr is not valid
*/
uint32_t (*ackctlinterrupt)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr);
/**
* Read the current interrupt mask for the PHY Independent Module
* @param[in] pD Driver state info specific to this instance.
* @param[out] mask Value of interrupt mask
* @return CDN_EOK on success.
* @return EINVAL if mask pointer is NULL
*/
uint32_t (*getphyindepinterruptmask)(const lpddr4_privatedata* pd, uint32_t* mask);
/**
* Sets the interrupt mask for the PHY Independent Module
* @param[in] pD Driver state info specific to this instance.
* @param[in] mask Value of interrupt mask to be written
* @return CDN_EOK on success.
* @return EINVAL if mask pointer is NULL
*/
uint32_t (*setphyindepinterruptmask)(const lpddr4_privatedata* pd, const uint32_t* mask);
/**
* Check whether a specific PHY Independent Module interrupt is
* active
* @param[in] pD Driver state info specific to this instance.
* @param[in] intr Interrupt to be checked
* @param[out] irqStatus Status of the interrupt, TRUE if active
* @return CDN_EOK on success.
* @return EINVAL if intr is not valid
*/
uint32_t (*checkphyindepinterrupt)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr, bool* irqstatus);
/**
* Acknowledge a specific PHY Independent Module interrupt
* @param[in] pD Driver state info specific to this instance.
* @param[in] intr Interrupt to be acknowledged
* @return CDN_EOK on success.
* @return EINVAL if intr is not valid
*/
uint32_t (*ackphyindepinterrupt)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr);
/**
* Retrieve status information after a failed init. The
* DebugStructInfo will be filled in with error codes which can be
* referenced against the driver documentation for further details.
* @param[in] pD Driver state info specific to this instance.
* @param[out] debugInfo status
* @return CDN_EOK on success.
* @return EINVAL if debugInfo is NULL
*/
uint32_t (*getdebuginitinfo)(const lpddr4_privatedata* pd, lpddr4_debuginfo* debuginfo);
/**
* Get the current value of Low power Interface wake up time.
* @param[in] pD Driver state info specific to this instance.
* @param[in] lpiWakeUpParam LPI timing parameter
* @param[in] fspNum Frequency copy
* @param[out] cycles Timing value(in cycles)
* @return CDN_EOK on success.
* @return EINVAL if powerMode is NULL
*/
uint32_t (*getlpiwakeuptime)(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
/**
* Set the current value of Low power Interface wake up time.
* @param[in] pD Driver state info specific to this instance.
* @param[in] lpiWakeUpParam LPI timing parameter
* @param[in] fspNum Frequency copy
* @param[in] cycles Timing value(in cycles)
* @return CDN_EOK on success.
* @return EINVAL if powerMode is NULL
*/
uint32_t (*setlpiwakeuptime)(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
/**
* Get the current value for ECC auto correction
* @param[in] pD Driver state info specific to this instance.
* @param[out] eccParam ECC parameter setting
* @return CDN_EOK on success.
* @return EINVAL if on_off is NULL
*/
uint32_t (*geteccenable)(const lpddr4_privatedata* pd, lpddr4_eccenable* eccparam);
/**
* Set the value for ECC auto correction. This API must be called
* before startup of memory.
* @param[in] pD Driver state info specific to this instance.
* @param[in] eccParam ECC control parameter setting
* @return CDN_EOK on success.
* @return EINVAL if on_off is NULL
*/
uint32_t (*seteccenable)(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
/**
* Get the current value for the Half Datapath option
* @param[in] pD Driver state info specific to this instance.
* @param[out] mode Half Datapath setting
* @return CDN_EOK on success.
* @return EINVAL if mode is NULL
*/
uint32_t (*getreducmode)(const lpddr4_privatedata* pd, lpddr4_reducmode* mode);
/**
* Set the value for the Half Datapath option. This API must be
* called before startup of memory.
* @param[in] pD Driver state info specific to this instance.
* @param[in] mode Half Datapath setting
* @return CDN_EOK on success.
* @return EINVAL if mode is NULL
*/
uint32_t (*setreducmode)(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
/**
* Get the current value for Data Bus Inversion setting. This will
* be compared with the current DRAM setting using the MR3
* register.
* @param[in] pD Driver state info specific to this instance.
* @param[out] on_off DBI read value
* @return CDN_EOK on success.
* @return EINVAL if on_off is NULL
*/
uint32_t (*getdbireadmode)(const lpddr4_privatedata* pd, bool* on_off);
/**
* Get the current value for Data Bus Inversion setting. This will
* be compared with the current DRAM setting using the MR3
* register.
* @param[in] pD Driver state info specific to this instance.
* @param[out] on_off DBI write value
* @return CDN_EOK on success.
* @return EINVAL if on_off is NULL
*/
uint32_t (*getdbiwritemode)(const lpddr4_privatedata* pd, bool* on_off);
/**
* Set the mode for Data Bus Inversion. This will also be set in DRAM
* using the MR3 controller register. This API must be called
* before startup of memory.
* @param[in] pD Driver state info specific to this instance.
* @param[in] mode status
* @return CDN_EOK on success.
* @return EINVAL if mode is NULL
*/
uint32_t (*setdbimode)(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode);
/**
* Get the current value for the refresh rate (reading Refresh per
* command timing).
* @param[in] pD Driver state info specific to this instance.
* @param[in] fspNum Frequency set number
* @param[out] cycles Refresh rate (in cycles)
* @return CDN_EOK on success.
* @return EINVAL if rate is NULL
*/
uint32_t (*getrefreshrate)(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
/**
* Set the refresh rate (writing Refresh per command timing).
* @param[in] pD Driver state info specific to this instance.
* @param[in] fspNum Frequency set number
* @param[in] cycles Refresh rate (in cycles)
* @return CDN_EOK on success.
* @return EINVAL if rate is NULL
*/
uint32_t (*setrefreshrate)(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
/**
* Handle Refreshing per chip select
* @param[in] pD Driver state info specific to this instance.
* @param[in] trefInterval status
* @return CDN_EOK on success.
* @return EINVAL if chipSelect is invalid
*/
uint32_t (*refreshperchipselect)(const lpddr4_privatedata* pd, const uint32_t trefinterval);
} LPDDR4_OBJ;
/**
* In order to access the LPDDR4 APIs, the upper layer software must call
* this global function to obtain the pointer to the driver object.
* @return LPDDR4_OBJ* Driver Object Pointer
*/
extern LPDDR4_OBJ *lpddr4_getinstance(void);
#endif /* LPDDR4_OBJ_IF_H */

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/* SPDX-License-Identifier: BSD-3-Clause */
/**********************************************************************
* Copyright (C) 2012-2018 Cadence Design Systems, Inc.
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
**********************************************************************
* Cadence Core Driver for LPDDR4.
**********************************************************************
*/
#ifndef LPDDR4_PRIV_H
#define LPDDR4_PRIV_H
#define PRODUCT_ID (0x1046U)
#define VERSION_0 (0x54d5da40U)
#define VERSION_1 (0xc1865a1U)
#define BIT_MASK (0x1U)
#define BYTE_MASK (0xffU)
#define NIBBLE_MASK (0xfU)
#define WORD_SHIFT (32U)
#define WORD_MASK (0xffffffffU)
#define SLICE_WIDTH (0x100)
/* Number of Data slices */
#define DSLICE_NUM (4U)
/*Number of Address Slices */
#define ASLICE_NUM (1U)
/* Number of accessible registers in each slice */
#define DSLICE0_REG_COUNT (140U)
#define DSLICE1_REG_COUNT (140U)
#define DSLICE2_REG_COUNT (140U)
#define DSLICE3_REG_COUNT (140U)
#define ASLICE0_REG_COUNT (52U)
#define PHY_CORE_REG_COUNT (140U)
#define CTL_OFFSET 0
#define PI_OFFSET (((uint32_t)1) << 11)
#define PHY_OFFSET (((uint32_t)1) << 12)
/* BIT[17] on INT_MASK_1 register. */
#define CTL_INT_MASK_ALL ((uint32_t)LPDDR4_LOR_BITS - WORD_SHIFT)
/* Init Error information bits */
#define PLL_READY (0x3U)
#define IO_CALIB_DONE ((uint32_t)0x1U << 23U)
#define IO_CALIB_FIELD ((uint32_t)NIBBLE_MASK << 28U)
#define IO_CALIB_STATE ((uint32_t)0xBU << 28U)
#define RX_CAL_DONE ((uint32_t)BIT_MASK << 4U)
#define CA_TRAIN_RL (((uint32_t)BIT_MASK << 5U) | ((uint32_t)BIT_MASK << 4U))
#define WR_LVL_STATE (((uint32_t)NIBBLE_MASK) << 13U)
#define GATE_LVL_ERROR_FIELDS (((uint32_t)BIT_MASK << 7U) | ((uint32_t)BIT_MASK << 6U))
#define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | (((uint32_t)BYTE_MASK) << 16U))
#define DQ_LVL_STATUS (((uint32_t)BIT_MASK << 26U) | (((uint32_t)BYTE_MASK) << 18U))
#endif /* LPDDR4_PRIV_H */

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/* SPDX-License-Identifier: BSD-3-Clause */
/**********************************************************************
* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
**********************************************************************
* WARNING: This file is auto-generated using api-generator utility.
* api-generator: 12.02.13bb8d5
* Do not edit it manually.
**********************************************************************
* Cadence Core Driver for LPDDR4.
**********************************************************************
*/
#ifndef LPDDR4_STRUCTS_IF_H
#define LPDDR4_STRUCTS_IF_H
#include <linux/types.h>
#include "lpddr4_if.h"
/** @defgroup DataStructure Dynamic Data Structures
* This section defines the data structures used by the driver to provide
* hardware information, modification and dynamic operation of the driver.
* These data structures are defined in the header file of the core driver
* and utilized by the API.
* @{
*/
/**********************************************************************
* Structures and unions
**********************************************************************/
/**
* Configuration of device.
* Object of this type is used for probe and init functions.
*/
struct lpddr4_config_s
{
/** Base address of controller registers */
struct lpddr4_ctlregs_s* ctlbase;
/** Information/warning handler */
lpddr4_infocallback infohandler;
/** Controller interrupt handler */
lpddr4_ctlcallback ctlinterrupthandler;
/** PHY Independent Module interrupt handler */
lpddr4_phyindepcallback phyindepinterrupthandler;
};
/**
* Structure contains private data for Core Driver that should not be used by
* upper layers. This is not a part of API and manipulating of those data may cause
* unpredictable behavior of Core Driver.
*/
struct lpddr4_privatedata_s
{
/** Base address of controller registers */
struct lpddr4_ctlregs_s* ctlbase;
/** Information/warning handler */
lpddr4_infocallback infohandler;
/** Controller interrupt handler */
lpddr4_ctlcallback ctlinterrupthandler;
/** PHY Independent Module interrupt handler */
lpddr4_phyindepcallback phyindepinterrupthandler;
};
/** Structure to contain debug information reported by the driver. */
struct lpddr4_debuginfo_s
{
/** PLL Lock error. */
bool pllerror;
/** I/O calibration error. */
bool iocaliberror;
/** RX offset error. */
bool rxoffseterror;
/** CA training error. */
bool catraingerror;
/** Write levelling error. */
bool wrlvlerror;
/** Gate Level error. */
bool gatelvlerror;
/** Read Level error. */
bool readlvlerror;
/** Write DQ training error. */
bool dqtrainingerror;
};
/** Frequency Set Point mode register values */
struct lpddr4_fspmoderegs_s
{
/** MR1 register data for the FSP. */
uint8_t mr1data_fn[LPDDR4_MAX_CS];
/** MR2 register data for the FSP. */
uint8_t mr2data_fn[LPDDR4_MAX_CS];
/** MR3 register data for the FSP. */
uint8_t mr3data_fn[LPDDR4_MAX_CS];
/** MR11 register data for the FSP. */
uint8_t mr11data_fn[LPDDR4_MAX_CS];
/** MR12 register data for the FSP. */
uint8_t mr12data_fn[LPDDR4_MAX_CS];
/** MR13 register data for the FSP. */
uint8_t mr13data_fn[LPDDR4_MAX_CS];
/** MR14 register data for the FSP. */
uint8_t mr14data_fn[LPDDR4_MAX_CS];
/** MR22 register data for the selected frequency. */
uint8_t mr22data_fn[LPDDR4_MAX_CS];
};
/** Structure to hold data set to initalise registers. */
struct lpddr4_reginitdata_s
{
/** Register initialisation data for the Controller. */
uint32_t denalictlreg[LPDDR4_CTL_REG_COUNT];
/** Should be set to true, if the corresponding denaliCtlReg element has been updated. */
bool updatectlreg[LPDDR4_CTL_REG_COUNT];
/** Register initialisation data for PHY independent module. */
uint32_t denaliphyindepreg[LPDDR4_PHY_INDEP_REG_COUNT];
/** Should be set to true, if the corresponding denaliPhyIndepReg element has been updated. */
bool updatephyindepreg[LPDDR4_PHY_INDEP_REG_COUNT];
/** Register initialisation data for the PHY. */
uint32_t denaliphyreg[LPDDR4_PHY_REG_COUNT];
/** Should be set to true, if the corresponding denaliPhyReg element has been updated. */
bool updatephyreg[LPDDR4_PHY_REG_COUNT];
};
#endif /* LPDDR4_STRUCTS_IF_H */