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https://github.com/brain-hackers/u-boot-brain
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a8c13c777e
Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
52 lines
1.2 KiB
C
52 lines
1.2 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_STRUCTS_IF_H
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#define LPDDR4_STRUCTS_IF_H
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#include <linux/types.h>
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#include "lpddr4_if.h"
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struct lpddr4_config_s {
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struct lpddr4_ctlregs_s *ctlbase;
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lpddr4_infocallback infohandler;
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lpddr4_ctlcallback ctlinterrupthandler;
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lpddr4_phyindepcallback phyindepinterrupthandler;
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};
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struct lpddr4_privatedata_s {
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struct lpddr4_ctlregs_s *ctlbase;
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lpddr4_infocallback infohandler;
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lpddr4_ctlcallback ctlinterrupthandler;
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lpddr4_phyindepcallback phyindepinterrupthandler;
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};
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struct lpddr4_debuginfo_s {
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u8 pllerror;
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u8 iocaliberror;
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u8 rxoffseterror;
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u8 catraingerror;
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u8 wrlvlerror;
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u8 gatelvlerror;
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u8 readlvlerror;
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u8 dqtrainingerror;
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};
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struct lpddr4_fspmoderegs_s {
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u8 mr1data_fn[LPDDR4_INTR_MAX_CS];
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u8 mr2data_fn[LPDDR4_INTR_MAX_CS];
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u8 mr3data_fn[LPDDR4_INTR_MAX_CS];
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u8 mr11data_fn[LPDDR4_INTR_MAX_CS];
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u8 mr12data_fn[LPDDR4_INTR_MAX_CS];
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u8 mr13data_fn[LPDDR4_INTR_MAX_CS];
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u8 mr14data_fn[LPDDR4_INTR_MAX_CS];
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u8 mr22data_fn[LPDDR4_INTR_MAX_CS];
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};
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#endif /* LPDDR4_STRUCTS_IF_H */
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