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https://github.com/brain-hackers/u-boot-brain
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![Bin Meng](/assets/img/avatar_default.png)
Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs are accessed indirectly via the message port and not the traditional MSR mechanism. Only UC, WT and WB cache types are supported. We configure all the fixed range MTRRs with common values (VGA RAM as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as WB, which significantly improves the boot time performance. With this commit, it takes only 2 seconds for U-Boot to boot to shell on Intel Galileo board. Previously it took about 6 seconds. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
393 lines
11 KiB
C
393 lines
11 KiB
C
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mmc.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mtrr.h>
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#include <asm/pci.h>
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#include <asm/post.h>
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#include <asm/processor.h>
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#include <asm/arch/device.h>
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#include <asm/arch/msg_port.h>
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#include <asm/arch/quark.h>
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static struct pci_device_id mmc_supported[] = {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
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};
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/*
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* TODO:
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*
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* This whole routine should be removed until we fully convert the ICH SPI
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* driver to DM and make use of DT to pass the bios control register offset
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*/
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static void unprotect_spi_flash(void)
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{
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u32 bc;
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qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc);
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bc |= 0x1; /* unprotect the flash */
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qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc);
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}
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static void quark_setup_mtrr(void)
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{
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u32 base, mask;
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int i;
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disable_caches();
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/* mark the VGA RAM area as uncacheable */
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msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000,
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MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
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msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000,
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MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
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/* mark other fixed range areas as cacheable */
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msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000,
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
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msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000,
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
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msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000,
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
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msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000,
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
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for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++)
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msg_port_write(MSG_PORT_HOST_BRIDGE, i,
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
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/* variable range MTRR#0: ROM area */
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mask = ~(CONFIG_SYS_MONITOR_LEN - 1);
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base = CONFIG_SYS_TEXT_BASE & mask;
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msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM),
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base | MTRR_TYPE_WRBACK);
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msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM),
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mask | MTRR_PHYS_MASK_VALID);
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/* variable range MTRR#1: eSRAM area */
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mask = ~(ESRAM_SIZE - 1);
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base = CONFIG_ESRAM_BASE & mask;
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msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM),
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base | MTRR_TYPE_WRBACK);
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msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM),
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mask | MTRR_PHYS_MASK_VALID);
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/* enable both variable and fixed range MTRRs */
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msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE,
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MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN);
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enable_caches();
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}
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static void quark_setup_bars(void)
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{
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/* GPIO - D31:F0:R44h */
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qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
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CONFIG_GPIO_BASE | IO_BAR_EN);
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/* ACPI PM1 Block - D31:F0:R48h */
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qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
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CONFIG_ACPI_PM1_BASE | IO_BAR_EN);
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/* GPE0 - D31:F0:R4Ch */
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qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
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CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);
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/* WDT - D31:F0:R84h */
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qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
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CONFIG_WDT_BASE | IO_BAR_EN);
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/* RCBA - D31:F0:RF0h */
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qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
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CONFIG_RCBA_BASE | MEM_BAR_EN);
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/* ACPI P Block - Msg Port 04:R70h */
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msg_port_write(MSG_PORT_RMU, PBLK_BA,
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CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);
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/* SPI DMA - Msg Port 04:R7Ah */
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msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
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CONFIG_SPI_DMA_BASE | IO_BAR_EN);
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/* PCIe ECAM */
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msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
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CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
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msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
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CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
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}
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static void quark_pcie_early_init(void)
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{
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/*
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* Step1: Assert PCIe signal PERST#
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*
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* The CPU interface to the PERST# signal is platform dependent.
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* Call the board-specific codes to perform this task.
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*/
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board_assert_perst();
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/* Step2: PHY common lane reset */
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msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_PHY_LANE_RST);
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/* wait 1 ms for PHY common lane reset */
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mdelay(1);
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/* Step3: PHY sideband interface reset and controller main reset */
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msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG,
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PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST);
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/* wait 80ms for PLL to lock */
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mdelay(80);
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/* Step4: Controller sideband interface reset */
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msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_SB_RST);
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/* wait 20ms for controller sideband interface reset */
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mdelay(20);
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/* Step5: De-assert PERST# */
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board_deassert_perst();
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/* Step6: Controller primary interface reset */
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msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_PRI_RST);
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/* Mixer Load Lane 0 */
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msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0,
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(1 << 6) | (1 << 7));
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/* Mixer Load Lane 1 */
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msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1,
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(1 << 6) | (1 << 7));
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}
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static void quark_usb_early_init(void)
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{
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/* The sequence below comes from Quark firmware writer guide */
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msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT,
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1 << 1, (1 << 6) | (1 << 7));
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msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_COMPBG,
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(1 << 8) | (1 << 9), (1 << 7) | (1 << 10));
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msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
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msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL1, 1 << 1);
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msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_PLL1,
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(1 << 3) | (1 << 4) | (1 << 5), 1 << 6);
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msg_port_alt_clrbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
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msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24);
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}
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static void quark_thermal_early_init(void)
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{
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/* The sequence below comes from Quark firmware writer guide */
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/* thermal sensor mode config */
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msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
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(1 << 3) | (1 << 4) | (1 << 5), 1 << 5);
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msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
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(1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) |
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(1 << 12), 1 << 9);
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msg_port_alt_setbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 14);
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msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 17);
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msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 18);
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msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG2, 0xffff, 0x011f);
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msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff, 0x17);
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msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3,
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(1 << 8) | (1 << 9), 1 << 8);
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msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff000000);
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msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG4,
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0x7ff800, 0xc8 << 11);
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/* thermal monitor catastrophic trip set point (105 celsius) */
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msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff, 155);
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/* thermal monitor catastrophic trip clear point (0 celsius) */
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msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff0000, 50 << 16);
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/* take thermal sensor out of reset */
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msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG4, 1 << 0);
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/* enable thermal monitor */
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msg_port_setbits(MSG_PORT_RMU, TS_MODE, 1 << 15);
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/* lock all thermal configuration */
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msg_port_setbits(MSG_PORT_RMU, RMU_CTRL, (1 << 5) | (1 << 6));
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}
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static void quark_enable_legacy_seg(void)
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{
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msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2,
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HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
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}
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int arch_cpu_init(void)
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{
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int ret;
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post_code(POST_CPU_INIT);
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#ifdef CONFIG_SYS_X86_TSC_TIMER
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timer_set_base(rdtsc());
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#endif
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ret = x86_cpu_init_f();
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if (ret)
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return ret;
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/*
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* Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
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* are accessed indirectly via the message port and not the traditional
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* MSR mechanism. Only UC, WT and WB cache types are supported.
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*/
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quark_setup_mtrr();
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/*
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* Quark SoC has some non-standard BARs (excluding PCI standard BARs)
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* which need be initialized with suggested values
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*/
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quark_setup_bars();
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/*
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* Initialize PCIe controller
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*
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* Quark SoC holds the PCIe controller in reset following a power on.
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* U-Boot needs to release the PCIe controller from reset. The PCIe
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* controller (D23:F0/F1) will not be visible in PCI configuration
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* space and any access to its PCI configuration registers will cause
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* system hang while it is held in reset.
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*/
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quark_pcie_early_init();
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/* Initialize USB2 PHY */
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quark_usb_early_init();
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/* Initialize thermal sensor */
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quark_thermal_early_init();
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/* Turn on legacy segments (A/B/E/F) decode to system RAM */
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quark_enable_legacy_seg();
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unprotect_spi_flash();
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return 0;
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}
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int print_cpuinfo(void)
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{
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post_code(POST_CPU_INFO);
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return default_print_cpuinfo();
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}
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void reset_cpu(ulong addr)
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{
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/* cold reset */
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x86_full_reset();
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}
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static void quark_pcie_init(void)
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{
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u32 val;
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/* PCIe upstream non-posted & posted request size */
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qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG,
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CCFG_UPRS | CCFG_UNRS);
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qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG,
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CCFG_UPRS | CCFG_UNRS);
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/* PCIe packet fast transmit mode (IPF) */
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qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF);
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qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF);
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/* PCIe message bus idle counter (SBIC) */
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qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val);
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val |= MBC_SBIC;
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qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val);
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qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val);
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val |= MBC_SBIC;
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qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val);
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}
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static void quark_usb_init(void)
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{
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u32 bar;
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/* Change USB EHCI packet buffer OUT/IN threshold */
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qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar);
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writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01);
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/* Disable USB device interrupts */
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qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar);
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writel(0x7f, bar + USBD_INT_MASK);
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writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK);
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writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS);
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}
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int arch_early_init_r(void)
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{
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quark_pcie_init();
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quark_usb_init();
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return 0;
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}
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int cpu_mmc_init(bd_t *bis)
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{
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return pci_mmc_init("Quark SDHCI", mmc_supported,
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ARRAY_SIZE(mmc_supported));
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}
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void cpu_irq_init(void)
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{
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struct quark_rcba *rcba;
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u32 base;
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qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
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base &= ~MEM_BAR_EN;
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rcba = (struct quark_rcba *)base;
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/*
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* Route Quark PCI device interrupt pin to PIRQ
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*
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* Route device#23's INTA/B/C/D to PIRQA/B/C/D
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* Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
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*/
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writew(PIRQC, &rcba->rmu_ir);
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writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
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&rcba->d23_ir);
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writew(PIRQD, &rcba->core_ir);
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writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
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&rcba->d20d21_ir);
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}
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int arch_misc_init(void)
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{
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return pirq_init();
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}
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void board_final_cleanup(void)
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{
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struct quark_rcba *rcba;
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u32 base, val;
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qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
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base &= ~MEM_BAR_EN;
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rcba = (struct quark_rcba *)base;
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/* Initialize 'Component ID' to zero */
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val = readl(&rcba->esd);
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val &= ~0xff0000;
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writel(val, &rcba->esd);
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/* Lock HMBOUND for security */
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msg_port_setbits(MSG_PORT_HOST_BRIDGE, HM_BOUND, HM_BOUND_LOCK);
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return;
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}
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