Priyanka Jain f6b96ff665 armv8: lsch3: Use SVR based timer base address detection ... Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>		2016-11-22 11:37:31 -08:00
..
clock.h	armv8/fsl_lsch3: Change arch to fsl-layerscape	2015-10-29 10:34:00 -07:00
config.h	armv8: fsl-layerscape: Move DDR config options to Kconfig	2016-10-06 09:59:11 -07:00
cpu.h	armv8: fsl_lsch2: Add LS1046A SoC support	2016-07-26 09:02:23 -07:00
fdt.h	armv8/ls1043aqds: add LS1043AQDS board support	2015-11-30 09:11:10 -08:00
fsl_serdes.h	fsl: serdes: ensure accessing the initialized maps of serdes protocol	2016-09-14 14:06:49 -07:00
immap_lsch2.h	armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539	2016-10-06 09:57:36 -07:00
immap_lsch3.h	armv8: lsch3: Use SVR based timer base address detection	2016-11-22 11:37:31 -08:00
imx-regs.h	armv8/fsl_lsch3: Change arch to fsl-layerscape	2015-10-29 10:34:00 -07:00
ls2080a_stream_id.h	armv8: ls2080a: update stream ID partitioning info	2016-03-21 12:42:12 -07:00
mmu.h	armv8/fsl_lsch3: Change arch to fsl-layerscape	2015-10-29 10:34:00 -07:00
mp.h	armv8: fsl-layerscape: Fix "cpu status" command	2016-10-06 09:56:57 -07:00
ns_access.h	fsl: csu: add an API to set R/W permission to PCIe	2016-09-14 14:07:08 -07:00
ppa.h	ARMv8/layerscape: Add FSL PPA support	2016-07-19 11:33:53 -07:00
soc.h	armv8: lsch3: Use SVR based timer base address detection	2016-11-22 11:37:31 -08:00
speed.h	armv8/fsl_lsch3: Change arch to fsl-layerscape	2015-10-29 10:34:00 -07:00