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f5b6fb7c1b
u-boot-brain/arch/powerpc/cpu/mpc8xxx
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York Sun f5b6fb7c1b powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers 
The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-05 10:13:50 -06:00
..
ddr powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers 2011-03-05 10:13:50 -06:00
cpu.c powerpc/p2040: Add various p2040 specific information 2011-01-19 22:58:23 -06:00
fdt.c powerpc/8xxx: Refactor SRIO initialization into common code 2011-01-14 01:32:21 -06:00
fsl_lbc.c powerpc/85xx: Add the workaround for erratum ELBC-A001 (enable on P4080) 2011-01-14 01:32:22 -06:00
Makefile powerpc/8xxx: Refactor SRIO initialization into common code 2011-01-14 01:32:21 -06:00
srio.c powerpc/8xxx: Refactor SRIO initialization into common code 2011-01-14 01:32:21 -06:00