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powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers

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The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
York Sun 2011-03-02 14:24:11 -08:00 committed by Kumar Gala
parent 8e29ebabf8
commit f5b6fb7c1b
1 changed files with 14 additions and 6 deletions
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20
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
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@ -333,6 +333,9 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
unsigned char acttoact_mclk;
/* Last write data pair to read command issue interval (tWTR) */
unsigned char wrtord_mclk;
/* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
static const u8 wrrec_table[] = {
1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
@ -371,6 +374,8 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
wrrec_mclk = wrrec_table[wrrec_mclk - 1];
if (popts->OTF_burst_chop_en)
wrrec_mclk += 2;
@ -810,6 +815,12 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
unsigned int bl; /* BL: Burst Length */
unsigned int wr_mclk;
/*
* DDR_SDRAM_MODE doesn't support 9,11,13,15
* Please refer JEDEC Standard No. 79-3E for Mode Register MR0
* for this table
*/
static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
const unsigned int mclk_ps = get_memory_clk_period_ps();
int i;
@ -853,13 +864,10 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
* 1=fast exit DLL on (tXP)
*/
dll_on = 1;
wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
if (wr_mclk >= 12)
wr = 6;
else if (wr_mclk >= 9)
wr = 5;
else
wr = wr_mclk - 4;
wr = wr_table[wr_mclk - 5];
dll_rst = 0; /* dll no reset */
mode = 0; /* normal mode */