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https://github.com/brain-hackers/u-boot-brain
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f3f8c564a1
ls2085a_common.h contains hard-coded information for NOR/NAND flash, I2C, DDR, etc. These are platform specific. Move them out of common header file and placed into respective board header files. Move TEXTBASE to 1MB offset to fit NOR flash with up to 1MB sector size. Enable command auto complete. Update prompt symbol. Set fdt_high to 0xa0000000 because Linux requires that the fdt be 8-byte aligned and below 512 MiB. Besides ensuring compliance with the 512 MiB limit, this avoids problems with the dtb being misaligned within the FIT image. Change the MC FW, MC DPL and Debug server NOR addresses in compliance with the NOR flash layouts for 128MB flash. Add PCIe macros. Enable "loadb" command. Disable debug server. Enable workaround for erratum A008511. Stop reset on panic for postmortem debugging. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
138 lines
5.3 KiB
C
138 lines
5.3 KiB
C
/*
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* Copyright 2014, Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_
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#define _ASM_ARMV8_FSL_LSCH3_CONFIG_
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#include <fsl_ddrc_version.h>
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#define CONFIG_SYS_PAGE_SIZE 0x10000
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#ifndef L1_CACHE_BYTES
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#define L1_CACHE_SHIFT 6
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#endif
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#define CONFIG_MP
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
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/* Link Definitions */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
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#define CONFIG_SYS_IMMR 0x01000000
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#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
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#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
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#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
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#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
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#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
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#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
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#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
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#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
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#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
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#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
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#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
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#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
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0x18A0)
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/* SP (Cortex-A5) related */
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#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
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#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
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#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
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#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
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(CONFIG_SYS_FSL_SP_ADDR + 0x0008)
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#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
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(CONFIG_SYS_FSL_SP_ADDR + 0x1000)
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#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
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#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
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#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
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#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
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#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
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#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
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#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
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#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
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/* TZ Protection Controller Definitions */
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#define TZPC_BASE 0x02200000
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#define TZPCR0SIZE_BASE (TZPC_BASE)
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#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
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#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
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#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
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#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
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#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
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#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
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#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
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#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
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#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
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/* TZ Address Space Controller Definitions */
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#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
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#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
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#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
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#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
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#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
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#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
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#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
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#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
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#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
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#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
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#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
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#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
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#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE 0x06000000
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#define GICR_BASE 0x06100000
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/* SMMU Defintions */
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#define SMMU_BASE 0x05000000 /* GR0 Base */
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/* DDR */
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#define CONFIG_SYS_FSL_DDR_LE
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#define CONFIG_VERY_BIG_RAM
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#ifdef CONFIG_SYS_FSL_DDR4
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#define CONFIG_SYS_FSL_DDRC_GEN4
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#else
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#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
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#endif
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#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
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#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
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/* IFC */
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#define CONFIG_SYS_FSL_IFC_LE
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/* PCIe */
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#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
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#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
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#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
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#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
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#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
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#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
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#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
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#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
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#ifdef CONFIG_LS2085A
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#define CONFIG_MAX_CPUS 16
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CONFIG_NUM_DDR_CONTROLLERS 3
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
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#else
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#error SoC not defined
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#endif
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#ifdef CONFIG_LS2085A
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#define CONFIG_SYS_FSL_ERRATUM_A008336
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#define CONFIG_SYS_FSL_ERRATUM_A008511
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#define CONFIG_SYS_FSL_ERRATUM_A008514
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#define CONFIG_SYS_FSL_ERRATUM_A008585
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#endif
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#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
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