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a615dfda8c
Do maintain a 200 usecs period of stable power and clock before asserting the CKE signal and sending commands, have at least 200 DRAM clock cycles pass after initialization before data access. Signed-off-by: Anatolij Gustschin <agust@denx.de> |
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.. | ||
cpu | ||
include/asm | ||
lib | ||
config.mk |