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mpc512x: Adjust the DRAM init sequence to the datasheet spec

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Do maintain a 200 usecs period of stable power and clock before
asserting the CKE signal and sending commands, have at least 200
DRAM clock cycles pass after initialization before data access.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
This commit is contained in:
Anatolij Gustschin 2013-02-08 00:03:49 +00:00 committed by Wolfgang Denk
parent fcc7fe4251
commit a615dfda8c
2 changed files with 17 additions and 1 deletions
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17
arch/powerpc/cpu/mpc512x/fixed_sdram.c
View File

@ -99,7 +99,19 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config,
sync_law(&im->sysconf.ddrlaw.ar);
/* DDR Enable */
out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN);
/*
* the "enable" combination: DRAM controller out of reset,
* clock enabled, command mode -- BUT leave CKE low for now
*/
i = MDDRC_SYS_CFG_EN & ~MDDRC_SYS_CFG_CKE_MASK;
out_be32(&im->mddrc.ddr_sys_config, i);
/* maintain 200 microseconds of stable power and clock */
udelay(200);
/* apply a NOP, it shouldn't harm */
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_DDRCMD_NOP);
/* now assert CKE (high) */
i |= MDDRC_SYS_CFG_CKE_MASK;
out_be32(&im->mddrc.ddr_sys_config, i);
/* Initialize DDR Priority Manager */
out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
@ -148,6 +160,9 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config,
out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0);
out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config);
/* Allow for the DLL to startup before accessing data */
udelay(10);
msize = get_ram_size(CONFIG_SYS_DDR_BASE, CONFIG_SYS_MAX_RAM_SIZE);
/* Fix DDR Local Window for new size */
out_be32(&im->sysconf.ddrlaw.ar, __ilog2(msize) - 1);

1
arch/powerpc/include/asm/immap_512x.h
View File

@ -351,6 +351,7 @@ typedef struct ddr512x {
/* MDDRC SYS CFG and Timing CFG0 Registers */
#define MDDRC_SYS_CFG_EN 0xF0000000
#define MDDRC_SYS_CFG_CKE_MASK 0x40000000
#define MDDRC_SYS_CFG_CMD_MASK 0x10000000
#define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF