mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-03 00:33:45 +09:00
ef00227551
This gives boards flexibility to assign other than default addresses to each DDR controller. For example, DDR controler 2 can have 0 as the base and DDR controller 1 has higher memory. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
||
---|---|---|
.. | ||
74xx_7xx | ||
mpc5xx | ||
mpc5xxx | ||
mpc8xx | ||
mpc8xxx | ||
mpc83xx | ||
mpc85xx | ||
mpc86xx | ||
mpc512x | ||
mpc824x | ||
mpc8220 | ||
mpc8260 | ||
ppc4xx |