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ec9cdaaa13
It turns out that in rare cases, current analytical approach to detect correct DRAM bus width and rank on H6 doesn't work. On some TV boxes with DDR3, incorrect DRAM configuration triggers write leveling error which immediately stops initialization process. Exact reason why this error appears isn't known. However, if correct configuration is used, initalization works without problem. In order to fix this issue, simply try another configuration when any kind of error appears during initialization, not just those related to rank and bus width. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Tested-by: Thomas Graichen <thomas.graichen@googlemail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
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| arc | ||
| arm | ||
| m68k | ||
| microblaze | ||
| mips | ||
| nds32 | ||
| nios2 | ||
| powerpc | ||
| riscv | ||
| sandbox | ||
| sh | ||
| x86 | ||
| xtensa | ||
| .gitignore | ||
| Kconfig | ||
| u-boot-elf.lds | ||