Ye Li eae4e0f3c1 i.MX7ULP: Workaround APLL PFD2 to 345.6Mhz ... The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider set to 1. This frequecy is out of ULP A0 spec. The MAX rate for GPU is 350Mhz. So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28) to workaround the problem. The correct fix should let GPU handle the clock rate in kernel. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>		2019-10-08 16:35:16 +02:00
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clock.c	i.MX7ULP: Workaround APLL PFD2 to 345.6Mhz	2019-10-08 16:35:16 +02:00
iomux.c	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
Kconfig	i.MX7ULP: Add CONFIG_MX7ULP to kconfig	2019-10-08 16:35:16 +02:00
Makefile	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
pcc.c	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
scg.c	i.MX7ULP: Fix SPLL/APLL clock rate calculation issue	2019-10-08 16:35:16 +02:00
soc.c	i.MX7ULP: Fix system reset after a7 rtc alarm expired.	2019-10-08 16:35:16 +02:00