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https://github.com/brain-hackers/u-boot-brain
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74f04490f2
Add device trees describing possible uses of mezzanine cards depending on the SERDES protocol employed. This patch adds DPAA2 networking support for the following protocols on each SERDES block: * SD #1: 3, 7, 19, 20 * SD #2: 11 Each SERDES block has a different device tree file per protocol supported, where the IO SLOTs used are enabled and PHYs located on the mezzanine cards are described. Also, dpmac nodes are edited and their associated phy-connection-type and phy-handle are added. Top DTS files are also added for each combination of protocol on the 3 SERDES blocks. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
170 lines
2.7 KiB
Plaintext
170 lines
2.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS common device tree source
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*
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* Copyright 2018-2019 NXP
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*
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*/
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#include "fsl-lx2160a.dtsi"
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&dpmac17 {
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status = "okay";
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phy-handle = <&rgmii_phy1>;
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phy-connection-type = "rgmii-id";
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};
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&dpmac18 {
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status = "okay";
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phy-handle = <&rgmii_phy2>;
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phy-connection-type = "rgmii-id";
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};
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&emdio1 {
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status = "okay";
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};
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&emdio2 {
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status = "okay";
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};
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&esdhc0 {
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status = "okay";
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};
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&esdhc1 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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u-boot,dm-pre-reloc;
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fpga@66 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "simple-mfd";
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reg = <0x66>;
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mux-mdio@54 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mdio-mux-i2creg";
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reg = <0x54>;
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#mux-control-cells = <1>;
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mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
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mdio-parent-bus = <&emdio1>;
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mdio@00 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00>;
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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};
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mdio@08 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40>;
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rgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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};
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emdio1_slot1: mdio@c0 { /* I/O Slot #1 */
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reg = <0xC0>;
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device-name = "emdio1_slot1";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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emdio1_slot2: mdio@c8 { /* I/O Slot #2 */
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reg = <0xC8>;
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device-name = "emdio1_slot2";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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emdio1_slot3: mdio@d0 { /* I/O Slot #3 */
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reg = <0xD0>;
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device-name = "emdio1_slot3";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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emdio1_slot4: mdio@d8 { /* I/O Slot #4 */
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reg = <0xD8>;
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device-name = "emdio1_slot4";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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emdio1_slot5: mdio@e0 { /* I/O Slot #5 */
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reg = <0xE0>;
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device-name = "emdio1_slot5";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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emdio1_slot6: mdio@e8 { /* I/O Slot #6 */
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reg = <0xE8>;
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device-name = "emdio1_slot6";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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emdio1_slot7: mdio@f0 { /* I/O Slot #7 */
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reg = <0xF0>;
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device-name = "emdio1_slot7";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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emdio1_slot8: mdio@f8 { /* I/O Slot #8 */
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reg = <0xF8>;
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device-name = "emdio1_slot8";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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i2c-mux@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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rtc@51 {
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compatible = "pcf2127-rtc";
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reg = <0x51>;
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};
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};
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};
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};
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&sata0 {
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status = "okay";
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};
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&sata1 {
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status = "okay";
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};
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&sata2 {
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status = "okay";
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};
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&sata3 {
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status = "okay";
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};
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